A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect

Transcription

1 A Novel Gate-Level NBTI Delay Degradaton Model wth Stackng Effect Hong Luo 1,YuWang 1,KuHe 1, Rong Luo 1, Huazhong Yang 1,,andYuanXe 2, 1 Crcuts and Systems Dvson, Dept. of EE, Tsnghua Unv., Bejng, , P.R. Chna luohong99@mals.thu.edu.cn 2 CSE Department, Pennsylvana State Unversty, Unversty Park, PA, USA yuanxe@cse.psu.edu Abstract. In ths paper, we propose a gate-level NBTI delay degradaton model, where the stress voltage varablty due to PMOS transstors stackng effect s consdered for the frst tme. Expermental results show that our gate-level NBTI delay degradaton model results n a tghten upper bound for crcut performance analyss. The tradtonal crcut degradaton analyss leads to on average 59.3% overestmaton. The pn reorderng technque can mtgate on average 6.4% performance degradaton n our benchmark crcuts. 1 Introducton As technology scales, accelerated agng effect [1] for nanoscale devces poses as a key challenge for desgners to fnd countermeasures that effectvely mtgate the degradaton and prolong system s lfetme. Negatve bas temperature nstablty (NBTI), whch has deleterous effect on the threshold voltage and the drve current of PMOS transstors, s emergng as one of the major relablty concerns [2]. Due to NBTI effect, the threshold voltage of PMOS transstor s shfted, carrer moblty and dran current are reduced [3], and the performance degradaton occurs [4,5,6]. The NBTI phenomena can be classfed as statc NBTI and dynamc NBTI. Statc NBTI s under the DC stress condton, and the detaled physcal mechansm was descrbed n [7]. The mpact of electrc and envronment parameters (such as electrc feld across the oxde and temperature) on the nterface trap generaton was studed n [8, 9]. Dynamc NBTI under the AC stress condton leads to a less severe parameter s shft over long tme because of the recovery phenomenon [4, 9, 10, 11]. Many analytcal NBTI models have been proposed recently. The mpact of NBTI on the worst case performance degradaton of dgtal crcuts was analyzed n [12]. An analytcal model for mult-cycle dynamc NBTI was proposed n [13], where a recurson process was used to evaluate the NBTI effect. A predctve NBTI model was proposed n [14, 15], the effect of varous process and desgn parameters was descrbed. An accurate and fast close-form analytcal model was proposed n [16], where temperatureaware NBTI modelng was also consdered. Ths work was supported by grants from 863 program of Chna (No. 2006AA01Z224), and NSFC (No , No ). Yuan Xe s work was supported n part by NSF CAREER and MARCO/DRAPA- GSRC. N. Azemard and L. Svensson (Eds.): PATMOS 2007, LNCS 4644, pp , c Sprnger-Verlag Berln Hedelberg 2007

2 A Novel Gate-Level NBTI Delay Degradaton Model 161 Most of these prevous proposed NBTI models may suffer from naccuracy or hgh computatonal complexty, and gate-level NBTI modelng s stll n ts nfancy. In ths paper, based on an accurate and fast close-form analytcal model [16], we propose a gate-level NBTI delay degradaton model consderng stackng effect. Our contrbuton n ths paper dstngushes tself n the followng aspects: A sngle transstor analytcal NBTI model s extended to a novel gate-level model, whch for the frst tme consders the varablty of the stress voltage due to stackng effect; A novel accurate gate-level delay model for V th degradaton s frst proposed. A tghtened upper bound for crcut performance degradaton can be acheved wth our new gate-level delay model. The rest of the paper s organzed as follows. In Secton 2, we frst revew prevous NBTI models, then our model consderng the varablty of the stress voltage due to stackng effect s descrbed. In Secton 3, the new gate-level delay model s presented based on tradtonal delay analyss. The smulaton results of the ALU benchmark crcuts are shown and analyzed n Secton 4. Fnally, Secton 5 concludes the paper. Note that the smulaton results n the followng sectons are based on a standard cell lbrary constructed usng the PTM 90nm bulk CMOS model [17]. V dd = 1.2V, V th = 200mV are set for all the transstors n the crcuts. The operaton tme s set to s (about 10yr). 2 NBTI Model 2.1 Prevous NBTI Models A threshold voltage degradaton ΔV th s caused by the nterface trap generaton due to PMOS NBTI effect, whch s descrbed by [18] ΔV th = (1 + m) q en t (t) (1) C ox where m represents equvalent V th shfts due to moblty degradaton, q e s the electronc charge, C ox s the gate oxde capactance, and N t (t) s the nterface trap generaton due to PMOS NBTI effect. The nterface trap generaton s often descrbed by the reacton-dffuson (R-D) model [19]. An analytcal soluton exsts under the DC stress condton, whch s regarded as statc NBTI model, kf N 0 N t (t)=1.16 (D H t) 1/4 = Bt 1/4 (2) k r where N 0 s the concentraton of ntal nterface defects; k f s dssocaton rate whch depends on electrc feld across the gate oxde, and k r s constant self-annealng rate; and D H s the correspondng dffuson coeffcent [19].

3 162 H. Luo et al. Interface traps ΔN t ( cm -2 ) Tme = s k f = 0.01s -1 k r = cm 3 /s N 0 = cm -2 D H = cm 2 /s 6.0 Kumar Our model Duty cycle (Our model) 9.08 (Kumar) 8.89 Fg. 1. Comparson between Kumar s and our models In the mult-cycle dynamc NBTI model proposed by Kumar et al. [13], the nterface trap generaton can be evaluated by a recurson formula, [ ( ) ] N t [(n + p s )T ]=Nt 0 Nt (nt) 4 1/4 p s + (3) where Nt 0 = BT 1/4 1 p,andβ = s 2 ; T and p s are the perod and the duty cycle of the stress waveform, respectvely. Actually, Eq. (3) descrbes a tght upper bound of all the relaxaton phases. A close-form equaton was proposed n [16] usng the fttng approach. The model n [16] can descrbe the dynamc NBTI effect wth the same accuracy but faster. In ths paper, we use the same method n [16] to construct our dynamc NBTI model. Eq. (3) n Kumar s model [13] s used as the fttng target functon. Hence, the nterface trap generaton can be descrbed as kf N 0 N t (t)=1.16 ξ (p s ) (D H t) 1/4 (4) k r where ξ (p s )=p 0.27p s s. The comparson between Kumar s and our model s shown n Fg. 1, and the Maxmum Error of N t (t) s 2.14% ( cm 2 from our model, and cm 2 from Kumar s model n Fg. 1). 2.2 Our Novel Gate-Level NBTI Model wth Stackng Effect Tradtonally, the estmaton method of V th degradaton n a logc gate due to NBTI s as follows: the PMOS transstors and ther correspondng nputs are frst assumed to be mutually ndependent; then the V th degradaton of each PMOS transstor s analyzed ndependently based on Eq. (4); fnally, the maxmum value s chosen to be the V th degradaton of the gate and can be used to calculate the delay degradaton of the gate. N 0 t

4 A Novel Gate-Level NBTI Delay Degradaton Model 163 FS PS R FS PS R 0 T 2T (n 1)T nt FS PS Cycle 1 Cycle 2 Cycle n R t FS FS FS PS R PS R PS 0 T 2T (n 1)T nt Cycle 1 Cycle 2 Cycle n R t Fg. 2. Stress waveform appled to the gate of the PMOS transstor (R s relaxaton, and FS, PS are full stress, partal stress, respectvely) Obvously, the above method s not accurate n the gate-level NBTI analyss, because the stackng effect s not consdered. In [14], V th varablty due to the body effect n the transstor stack was consdered, but only the statc NBTI effect was analyzed. In ths secton, a novel gate-level NBTI model wth stackng effect s proposed based on the transstor-level NBTI model gven n Secton 2.1. In ths paper, the stress voltage varablty due to stackng effect n the logc gate s consdered. Because of the resstance of the transstors, the nternal nodes are based at a mddle voltage, whch leads to dfferent V gs of the PMOS transstors. Therefore, when the PMOS transstor s under stress, t s not always V dd based. We denote the stress condton under V dd as full stress (FS), and the stress under a lower voltage as partal stress (PS). Before the new V th degradaton model wth stackng effect s proposed, the nterface trap generaton due to dynamc PMOS NBTI effect mxed wth full stress and partal stress should be analyzed. The random aperodc sgnal can be converted to determnstc perodc waveform, based on the sgnal probablty (SP). Wth the same SP, the NBTI effect wll be the same [6]. Hence, we use the waveform shown n Fg. 2 as the nput of PMOS transstor. In the frst waveform, the full stress phase s ahead of the partal stress phase n one cycle; and the second waveform shows the reversed condton. From the numerc smulaton based on the reacton-dffuson model [19], we fnd that the order of these phases have neglgble mpact on the fnal generaton of nterface traps. Fg. 3 shows the comparson between the stress waveforms n Fg. 2 and the error s 0.18% ( cm 2 vs cm 2 ). In the followng part of ths paper, we assume that full stress s always ahead of partal stress n a cycle. Fg. 4 shows the numerc smulated nterface trap generaton due to dynamc NBTI under dfferent tme rato of full stress phase to partal stress phase. We fnd that the mxed effect of these two stress phases can be derved by weghted averagng the full stress and partal stress effect, whch s descrbed as N t,mxed = p FS p PS N t,fs + N t,ps (5) p FS + p PS p FS + p PS where N t,fs s the nterface trap generaton f all stress phases are full stress ; and N t,ps s the nterface trap generaton f all stress phases are partal stress. The parameters p FS and p PS are sgnal probabltes of full stress and partal stress, respectvely. By

5 164 H. Luo et al. Interface traps ΔN t ( cm -2 ) FS: k f = 0.01s -1 PS: k f = 0.004s Operaton tme (s) (PS ahead) 5.51 (FS ahead) 5.50 FS ahead of PS PS ahead of FS Fg. 3. The mpact of the stress phases order on nterface trap generaton Interface traps ΔN t ( cm -2 ) % FS 60% PS 30% FS, 30% PS 40% FS, 20% PS 20% FS, 40% PS Operaton tme (s) Fg. 4. The analyss of mxed NBTI effect of full stress and partal stress calculatng, we fnd the maxmum error occurs at 30% FS, 30% PS. The smulated trap generaton s cm 2 as shown n Fg. 4, and by Eq. (5), the estmated nterface trap generaton s cm 2. Therefore, the maxmum error s 2.18%. However, n a transstor stack, the PMOS transstors can be based at varous voltages, so there exsts more than one partal stress condton. Therefore the law descrbed above s extended to more than two dfferent stress condtons. Frst, we number these stress condtons as S 0,S 1,S 2,...,andS 0 s always the full stress condton. The sgnal probabltes of these stress condtons are p 0, p 1, p 2,..., respectvely, and the sgnal probablty of relaxaton condton s denoted as r; so the duty cycle p s of all the stress condtons s p s = p = 1 r (6) where the number of s s related to the number of PMOS transstors n the stack.

6 A Novel Gate-Level NBTI Delay Degradaton Model 165 As the threshold voltage degradaton s proportonal to the nterface trap generaton, the fnal V th degradaton due to PMOS NBTI effect wth more than one stress condton s modeled accordng to Eq. (5) as p ΔV th = ΔV th, (7) p s where ΔV th, s the correspondng threshold voltage degradaton f all the stress phases are S. Accordng to Eq. (1) and (4), ΔV th, s expressed as ΔV th, = η p s 0.27p s t 1/4 (8) and the parameter η s decded by the predctve model proposed n [14], η = A T ox C ox (V gs, V th ) exp( E ox, ) exp( E a E 0 k b T ) (9) where V gs, s the stress voltage correspondng to dfferent stress phase due to stackng effect frst descrbed n ths paper, and other parameters are the same as n [14]. If only one full stress condton s consdered, that s p s = p 0, Eq. (7) can be smplfed as 0.27p ΔV th = ΔV th,0 = η 0 p s s t 1/4 (10) whch conssts wth the NBTI model n secton Gate-Level Delay Degradaton Analyss 3.1 Tradtonal Gate Delay Model Prevously, the propagaton delay of a gate can be approxmately expressed as [18] t pd = C LV dd C L V dd L eff = I d μc ox W eff (V gs V th ) α (11) where α s the velocty saturaton ndex, and C L contans the parastc capactance. The shft n the transstor threshold voltage ΔV t can be derved usng Eq. (10). Hence, wth the Taylor seres expanson, the delay degradaton Δt pd for the gate s derved as Δt pd = αδv th V gs V th t pd0 (12) where t pd0 s the orgnal delay of the gate wthout any V th degradaton, and can be extracted from thrd-party tme analyss tools. 3.2 Our Novel Gate-Level Delay Model The proposed NBTI model wth stackng effect descrbed n Secton 2.2 leads to dfferent V th degradaton for each PMOS transstor n a logc gate, but the gate delay model

7 166 H. Luo et al. D C B A V dd M0 u M1 v M2 w M3 Y M4 M5 M6 M7 C L Fg. 5. The schematc of NOR4 gate descrbed n Secton 3.1 s ncapable to handle ths stuaton. So a novel gate-level delay model s proposed n ths paper. An NOR4 gate s used to llustrate our dervaton, and the schematc s shown n Fg. 5, where C L s the external load capactance. If the V th degradaton of these PMOS transstors are small, the gate delay can be consdered lnear wth ΔV th and C L, t pd = t pd0 + Δt pd = t pd0 + [(α C L + β )ΔV th,m ], = 0,1,2,3 (13) where the parameters α and β descrbe the effect of chargng external load capactance C L and nternal parastc capactance respectvely, and they only depend on the gate type. In order to use the exstng results extracted from the tmng analyss tools drectly, the term C L n Eq. (13) should be elmnated. From Eq. (11), we can derve another lnear equaton, that the orgnal propagaton delay s lnear wth external load capactance C L, t pd0 = P C L + Q (14) where P s the load delay factor, and Q descrbes the ntrnsc delay. From Eq. (13) and (14), t pd can be derved as [( ) ] tpd0 Q t pd = t pd0 + α + β ΔV th,m P = t pd0 + t pd0 g = α P, h = (g ΔV th,m )+ (h ΔV th,m ) (15) ( β Q ) P α where g and h only depend on the gate type. In the standard-cell desgn, the parameters g and h of all the gates n the cell lbrary can be calculated n advance, and then a lookup table s created. (16)

8 A Novel Gate-Level NBTI Delay Degradaton Model 167 Table 1. Threshold voltage degradaton n NOR4 gate Transstor M0 M1 M2 M3 ΔV th 25.7mV 20.6mV 14.5mV 5.5mV Table 2. Comparson between the tradtonal gate delay analyss and our gate-level delay model Gate Orgnal delay Hspce Our model Tradtonal model Type t pd0 Δt pd Δt pd Estmaton error Δt pd Overestmaton NOR ps 6.9ps 7.0ps 1.4% 10.5ps 50.0% NOR ps 5.7ps 5.8ps 1.8% 8.4ps 44.8% NOR ps 4.7ps 4.7ps 0.0% 6.1ps 29.8% INV 83.5ps 3.6ps 3.6ps 0.0% 3.6ps 0.0% We demonstrate the mpact of stress voltage varablty due to stackng effect on NBTI analyss. The sgnal probabltes of all the nput patterns are equal. The V th degradaton of all the PMOS transstors n NOR4 gate are shown n Table 1. We can see that transstor M0, whch s closest to the power supply as shown n Fg. 5, has the largest threshold voltage degradaton; whle M3 has the smallest threshold voltage degradaton. Therefore, the gate-level delay analyss s necessary for accurate estmaton of NBTI effect. The comparson between tradtonal gate delay analyss and our novel gate-level delay model s shown n Table 2. The thrd column of Table 2 s the gate delay degradaton wth stackng effect smulated by Hspce, and the fourth column s calculated by our delay model, whle the estmaton error of our model s shown n the ffth column. These data demonstrate that our gate-level delay model s accurate enough for delay analyss. If the tradtonal approach s used to analyze the gate delay degradaton, the worst case ΔV th,m0 = 25.7mV s set as ΔV th n Eq. (12), and the results are shown n the sxth column. We can see that the tradtonal gate delay analyss overestmates the delay degradaton, and these overestmatons compared to our model are shown n the seventh column. We can see that more transstors n PMOS stack lead more overestmaton: 29.8% overestmaton n NOR2 gate, whle 50.0% n NOR4 gate. From Table 2, we can also see that n the gate wth no stackng effect, as nverter (INV) and AND gate, gate-level delay analyss leads to the same result wth tradtonal analyss. Only the result for INV gate s lsted n Table 2 for brevty. 4 Expermental Results In ths secton, some ALU crcuts and c6288 crcut n ISCAS85 are used as the benchmarks to nvestgate the effect on the crcut performance degradaton usng our NBTI delay degradaton model. As stackng effect leads to dfferent V th degradaton of the PMOS transstors, the gate delay can be mnmzed usng pn reorderng technque just as that n leakage mnmzaton [20]. The enumeraton searchng pn reorderng technque s used n our experment just to estmate the upper bound of our gate-level model n mtgatng crcut performance degradaton due to NBTI.

9 168 H. Luo et al. Table 3. Delay degradaton of benchmark crcuts Crcuts R stack Orgnal delay No stackng effect Stackng effect Pn reorderng t pd0 (ns) Δt pd,ns (ps) Δt pd,ws (ps) Δt pd,pr (ps) array4 61/ array8 347/ bk16 47/ bk32 124/ booth9 277/ ks16 31/ ks32 138/ log16 135/ log32 268/ pm8 278/ pm / c / Avg. N/A N/A 59.3% 0.0% -6.4% The results are shown n Table 3. The crcuts array4 and array8 are 4x4 and 8x8 array multplers; bk16 and bk32 are 16-bt and 32-bt Brent Kung adders; booth9 s 9x9 booth multpler; ks16 and ks32 are 16-bt and 32-bt Kogge Stone adders; log16 and log32 are 16-bt and 32-bt log shfter; and pm8 and pm16 are 8x8 and 16x16 parallel multplers. R stack s the rato of gates wth PMOS transstor stack. The orgnal delay t pd0 s extracted from an STA tool. The delay degradaton wth no stackng effect Δt pd,ns s evaluated usng transstor-level NBTI model Eq. (4) and gate delay model Eq. (12). The delay degradaton wth stackng effect Δt pd,ws s evaluated usng our novel gatelevel NBTI and delay model Eq. (7) and (15). In Table 3, we use the ffth column (Δt pd,ws ) as the standard data, whch the fourth and sxth columns are compared to. We can see that from Table 3, the tradtonal method brngs on average 59.3% overestmaton of the crcut delay degradaton. The pn reorderng technque leads to on average 6.4% mprovement of crcut performance. The overestmaton of the crcut delay degradaton and the mprovement of crcut performance by pn reorderng technque depend on not only R stack, but also the contrbuton of gates wth PMOS stack to the crtcal paths n the crcut. For example, ks32 leads to 129.4% overestmaton of delay degradaton, much larger than pm16, although R stack of ks32 s less than that of pm16. bk32 and ks32 have almost the same R stack,andthe overestmatons of delay degradaton are both large, but bk32 has a larger mprovement of crcut performance by pn reorderng. Almost all the gates n c6288 crcut are NOR2, the overestmaton of crcut delay degradaton s 23.4%, very close to the overestmaton of a sngle NOR2 gate: 29.8%. 5 Concluson Negatve bas temperature nstablty s emergng as one of the major crcut performance degradaton concerns. Fast and accurate analyss of NBTI-nduced crcut degradaton s mportant for crcut desgners to fnd mtgaton solutons. In ths paper, we

10 A Novel Gate-Level NBTI Delay Degradaton Model 169 use a smple close-form analytcal V th degradaton model for PMOS to develop a novel gate-level NBTI and delay model. The stress voltage varablty due to PMOS transstors stackng effect s for the frst tme consdered n gate-level NBTI modelng. The tradtonal analyss of gate delay degradaton due to NBTI results n 50.0% overestmaton for an NOR4 gate, whle n the crcut performance degradaton analyss, the maxmum overestmaton s 130.2% n 16-bt Brent Kung adder (bk16) crcut. The mtgaton of performance degradaton by pn reorderng technque can reach up to 35.1% n 32-bt Brent Kung adder (bk32) crcut. References 1. Borkar, S.: Desgnng relable systems from unrelable components: The challenges of transstor varablty and degradaton. Mcro, IEEE 25(6), 10 16, (2005) 2. Huard, V., Denas, M., Parthasarathy, C.: NBTI degradaton: From physcal mechansms to modellng. Mcroelectron. Relab. 46(1), 1 23 (2006) 3. Kufluoglu, H., Alam, M.A.: Theory of nterface-trap-nduced NBTI degradaton for reduced cross secton MOSFETs. IEEE Trans. Electron Devces 53(5), (2006) 4. Wttmann, R., Puchner, H., Hnh, L., Cerc, H., Gehrng, A., Selberherr, S.: Impact of NBTIdrven parameter degradaton on lfetme of a 90nm p-mosfet. In: Proc. Intl. Integrated Relab. Workshop Fnal Report, pp (2005) 5. Reddy, V., Krshnan, A.T., Marshall, A., Rodrguez, J., Natarajan, S., Rost, T., Krshnan, S.: Impact of negatve bas temperature nstablty on dgtal crcut relablty. Mcroelectron. Relab. 45(1), (2005) 6. Kumar, S., Km, C., Sapatnekar, S.: Impact of NBTI on SRAM Read Stablty and Desgn for Relablty. In: Proc. ISQED, pp (2006) 7. Ogawa, S., Shono, N.: Generalzed dffuson-reacton model for the low-feld charge-buldup nstablty at the S-SO 2 nterface. Physcal Revew B 51(7), (1995) 8. Alam, M., Mahapatra, S.: A comprehensve model of PMOS NBTI degradaton. Mcroelectron. Relab. 45(1), (2005) 9. Mahapatra, S., Saha, D., Varghese, D., Kumar, P.: On the generaton and recovery of nterface traps n MOSFETs subjected to NBTI, FN, and HCI stress. IEEE Trans. Electron Devce 53(7), (2006) 10. Chen, G., L, M., Ang, C., Zheng, J., Kwong, D.: Dynamc NBTI of p-mos transstors and ts mpact on MOSFET scalng. IEEE Electron Dev. Lett. 23(12), (2002) 11. Mahapatra, S., Bharath Kumar, P., Dale, T., Sana, D., Alam, M.: Mechansm of negatve bas temperature nstablty n CMOS devces: degradaton, recovery and mpact of ntrogen. In: IEDM Tech. Dg., pp (2004) 12. Paul, B., Kang, K., Kufluoglu, H., Alam, M., Roy, K.: Impact of NBTI on the temporal performance degradaton of dgtal crcuts. IEEE Electron Dev. Lett. 26(8), (2005) 13. Kumar, S., Km, C., Sapatnekar, S.: An Analytcal Model for Negatve Bas Temperature Instablty. In: Proc. IEEE/ACM ICCAD, pp (2006) 14. Vattkonda, R., Wang, W., Cao, Y.: Modelng and Mnmzaton of PMOS NBTI Effect for Robust Nanometer Desgn. In: Proc. DAC, pp (2006) 15. Bhardwaj, S., Wang, W., Vattkonda, R., Cao, Y., Vrudhula, S.: Predctve Modelng of the NBTI Effect for Relable Desgn. In: Proc. CICC, pp (2006) 16. Luo, H., Wang, Y., He, K., Luo, R., Yang, H., Xe, Y.: Modelng of PMOS NBTI Effect Consderng Temperature Varaton. In: Proc. ISQED, pp (2007)

11 170 H. Luo et al. 17. Nanoscale Integraton and Modelng Group, ASU: Predctve Technology Model (PTM) 18. Paul, B., Kang, K., Kufluoglu, H., Alam, M., Roy, K.: Temporal Performance Degradaton under NBTI: Estmaton and Desgn for Improved Relablty of Nanoscale Crcuts. In: Proc. DATE, vol. 1, pp. 1 6 (2006) 19. Staths, J., Zafar, S.: The negatve bas temperature nstablty n MOS devces: A revew. Mcroelectron. Relab. 46(2-4), (2006) 20. Sultana, A., Sylvester, D., Sapatnekar, S.: Transstor and pn reorderng for gate oxde leakage reducton n dual Tox crcuts. In: Proc. ICCD, pp (2004)