Sleep Transistor Distribution in Row-Based MTCMOS Designs

Transcription

1 Sleep Transstor Dstrbuton n Row-Based MTCMOS Desgns Chanseok Hwang 1, Peng Rong 2, Massoud Pedram 3 1 Samsung Electroncs, Seoul, South Korea 2 LSI Logc Corp, Mlptas, CA, USA 3 Unversty of Southern Calforna, Los Angeles, CA, USA Abstract - The Mult-Threshold CMOS (MTCMOS) technology has become a popular technque for standby power reducton. Ths technology utlzes hgh-vth sleep transstors to reduce subthreshold leakage currents durng the standby mode of CMOS VLSI Crcuts. The performance of MTCMOS crcuts strongly depends on the sze of the sleep transstors and the parastcs on the vrtual ground network. Gven a placed net lst of a row-based MTCMOS desgn and the number of sleep transstor cells on each standard cell row, ths paper ntroduces an optmal algorthm for lnearly placng the allocated sleep transstors on each standard cell row so as to mnmze the performance degradaton of the MTCMOS crcut, whch s n part due to unwanted voltage drops on ts vrtual ground network. Expermental results show that, compared to exstng methods of placng the sleep transstors on cell rows, the proposed technque results n up to 11% reducton n the crtcal path delay of the crcut. 1. INTRODUCTION Leakage power n modern CMOS VLSI crcuts has become a component comparable to dynamc power dsspaton. Typcally, the subthreshold leakage current domnates the devce off-state leakage due to low V th transstors employed n logc cell blocks n order to mantan the crcut swtchng speed n spte of decreasng V DD levels [1]. The Mult- Threshold CMOS (MTCMOS) technque can sgnfcantly reduce the subthreshold leakage currents durng the crcut sleep (standby) mode by addng hgh-v th power swtches (sleep transstors) to low-v th logc cell blocks [2] [3]. Ths s because the stacked hgh-v th sleep transstor connected to the bottom of the pull-down network of all logc cells n the crcut acts as a hgh-resstance element durng the sleep mode, whch lmts the leakage current from V dd to ground lnes. At the same tme, because of the stack effect, the subthreshold leakage of the low-v th transstors n the logc block tself goes down. Ths leakage reducton s preferably acheved wth small performance degradaton because, durng the actve mode of the crcut, the sleep transstor s fully on (.e., t operates n the lnear mode), and thus, all low-v th logc cells n the MTCMOS logc block can swtch very fast. Permsson to make dgtal or hard copes of all or part of ths work for personal or classroom use s granted wthout fee provded that copes are not made or dstrbuted for proft or commercal advantage and that copes bear ths notce and the full ctaton on the frst page. To copy otherwse, or republsh, to post on servers or to redstrbute to lsts, requres pror specfc permsson and/or a fee. GLSVLSI 07, March 11 13, 2007, Stresa-Lago Maggore, Italy. Copyrght 2007 ACM /07/ $5.00. Unfortunately, the stuaton s dfferent n real desgns. More precsely, durng the actve mode of the crcut operaton, the hgh-v th sleep transstor acts as a small lnear resstance placed at the bottom of the transstor stack to ground, causng the propagaton delay of the cells n the logc block to ncrease. In addton, the vrtual ground network tself acts as a dstrbuted RC network, whch causes the voltage of the vrtual ground node to rse even further, thereby degradng the swtchng speed of the logc cells even more (cf. Fg.1.) The former effect s a functon of the sze of the sleep transstor whereas the latter effect s a functon of the physcal dstance of the logc cell from the sleep transstor. Fgure 1. (a) MTCMOS crcut structure, (b) The crcut model wth vrtual ground nterconnect and sleep transstor modeled as resstors, R and R s, respectvely Fgure 1(a) depcts a logc block, LB, n whch a group of low-v th logc cells are frst connected to the vrtual ground node and then through a hgh-v th sleep transstor, S, to the actual ground, GND [2]. Fgure 1(b) models the vrtual ground nterconnecton and the hgh-v th sleep transstor, whch behaves lke a lnear resstor n the actve mode of the crcut operaton [4], as resstors R and R s, respectvely. The vrtual ground s at voltage V x above the actual ground,.e., V = I ( Rs+ R) where I s the current flowng through the X vrtual ground sub-network and the sleep transstor. The voltage drop across R s + R reduces the gate over-drve voltage of MTCMOS logc cells (.e., ther V gs value) from V to dd Vdd Vx. In ths paper, we present an optmal algorthm for placng sleep transstors for the standard cell-based layout desgn, whch mnmzes the performance degradaton of MTCMOS crcuts due to the nterconnect resstance of the vrtual ground network. We dscuss prevous works n secton 2, ntroduce the problem formulaton and the proposed method

2 n secton 3 and 4, respectvely. Then, we present experment results n secton 5 and conclude n secton PRIOR WORK Optmal szng of the sleep transstors (STs) has been actvely researched snce the MTCMOS technology was ntroduced. One of the most conservatve approaches s the dedcaton of one ST to each logc cell and the optmzaton of ndvdual STs, whch s known as fne-graned leakage control [5] [6]. Ths approach makes t easer to do RT-level sgn off by usng standard statc tmng analyss technques whereas t tends to ncur large area overhead [7]. Other approaches [8] [9] group logc gates based on ther current dscharge patterns n a gven swtchng cycle so that sleep transstors of gates wth mutually exclusve current dscharge patterns are merged together, thereby, reducng the area overhead. In [8], the authors frst sze the sleep transstor of each logc cell so as to mpose an upper bound on the performance degradaton of the cell durng the actve mode of the crcut operaton. Next, they calculate the dscharge current patterns of all logc cells n the crcut based on a unt delay model, and fnally, merge the sleep transstors of cells wth non-overlappng dscharge current waveforms. In [9], the authors use a more precse delay model to do the same steps, presentng several heurstc technques for effcent gate clusterng. In [10], the authors use average current consumpton values of logc gates to determne the sleep transstor wdth needed to satsfy a requred crcut speed based on the assumpton that the crcut speed depends only weakly on the crcut operatng pattern for suffcently large sleep transstor szes. In other approaches [11] [12], the authors selectvely apply the MTCMOS technology for gates belongng to tmng-crtcal paths of a crcut, where low-v th gates are only used n the tmng-crtcal paths. Recently, a number of approaches have begun to consder the nterconnect resstance of the vrtual ground lne as one of the crucal factors that affect the performance of MTCMOS crcuts. In [13], the authors model both sleep transstors and vrtual ground nterconnects as resstors, and thereby, consder a resstve-only network when computng szes of the dstrbuted sleep transstors. In [14] [15], the authors show that the delay and output slew of a gate wth the MTCMOS technology ncrease lnearly wth vrtual ground length, and then take ths parameter nto account when modelng the delay of MTCMOS gates. Ths paper addresses the automatc placement of sleep transstors consderng the nterconnect resstance of the vrtual ground n standard cell-based layout desgn. In [7] [16], the authors provde desgn methodologes that treat a ST as a standalone lbrary cell and then calculate and allocate a number of sleep transstor cells (STCs) on each cell row. The STCs are then placed at one or the other corner of each row on a row-by-row bass. In these methods, all cells n a row share all of the STCs and the vrtual ground lne n the same row. The man advantages of these approaches are that (a) they are fully compatble wth the exstng standard-cell physcal desgn flow and (2) they result n a shorter reactvaton tme when extng the sleep state [16]. However, these approaches do not consder the voltage drop due to the vrtual ground nterconnect n decdng the locaton of STCs. In practce, they tend to over-estmate the sze of sleep transstors needed on each cell row so as to compensate for the voltage drop due to vrtual ground nterconnect resstance. Wth contnued process scalng, the wre segments n the ground network become more resstve, causng more area overhead. In addton, the performance degradaton of a logc cell that s far away from the STCs may greatly affect the overall crcut performance f the logc cell happens to le on a tmng-crtcal path of the crcut. Therefore, n ths paper, we shall address the queston of how to place STCs for the standard cell-based layout desgn so that the performance degradaton of MTCMOS crcuts due to the nterconnect resstance of the vrtual ground lne s mnmzed. 3. PROBLEM FORMULATION The problem of sleep transstor dstrbuton can be descrbed as follows. Gven a placement of MTCMOS desgn n the row-based layout and the dstrbuton of sleep transstor cells on each row, the objectve s to determne an optmal placement of sleep transstor cells such that the performance degradaton of the MTCMOS crcut due to the voltage drop of the vrtual ground lne s mnmzed. Let s focus on the sleep transstor dstrbuton n row y. Let C={c, =1,2,,n} denote the set of logc cells n row y, and S={s j, j=1,2,,m} denote the set of STCs to be placed on the row. n and m denote the cell and STC counts, respectvely. We defne the performance loss of a logc cell c C n the actve mode as follows: PL( c ) =ΔTc ( ) SLc ( ) (1) where T(c ) denotes the addtonal propagaton delay of cell c that results from the resstance of the vrtual ground. SL(c ) s the slack avalable for cell c before nsertng the STCs. The slack tmes are calculated by dong statc tmng analyss (STA) on the crcut. Usng the well-known alpha-power delay model [17], the cell propagaton delay n the presence of a sleep transstor and vrtual ground nterconnects s gven by Cload, Vdd T ( c ) (2) ( Vdd I STC ( RSTC + R) VtL ) α where C load, and V tl denote the capactve loadng seen by cell I and the threshold voltage of the low V th transstors n the cell, respectvely. R STC denotes the STC resstance, R denotes the nterconnect resstance, and I STC (R STC +R ) s the source voltage at the bottom of the NMOS-secton of the logc cell. Thus, we may calculate T(c ) as Δ Tc ( ) = Tc ( ) Tc ( ) R = 0 (3) R s dependent on the dstances between c and STCs on ths cell row, s j S. Accordngly, T(c ) s a functon f of these dstances: Δ Tc ( ) = f( xs xc, xs xc,..., xs xc ) (4) 1 2 m where x c and x sj denote the horzontal coordnates of logc cell c and STC s j, respectvely. Furthermore, to a frst order, T(c ) s domnated by the poston of the sleep transstor that

3 s closest to c. Let d denote the mnmal dstance between c and any of the sleep transstors,.e., d = mn( xs x,,..., ) 1 c x s x 2 c x s x m c (5) We may approxmate equaton (4) by ΔTc ( ) gd ( ) (6) Now, n equaton (2), R may be replaced wth r d, where r s the wre resstance per unt length of the vrtual ground network. By usng Taylor Seres Expanson of the rght-hand sde of equaton (2), we can obtan functon g n equaton (6): T ( c) R Δ T ( c) = d R d = 0 d That s, Δ Tc ( ) = w d αcload, ISTC r Vdd where w = κ 1 ( Vdd ISTC Rs VtL ) α + κ s a proportonalty coeffcent Thus the performance loss can be wrtten as PL( c ) = w d SLc ( ) (9) We next defne a cost fgure, Φ, for the STC placement: Φ= max PL( c ) (10) 1 n It s mportant to balance the current flowng through each sleep transstor n the actve mode. Otherwse, a sleep transstor that carres too much current wll sgnfcantly ncrease the vrtual ground voltage n ts physcal neghborhood, hence, t wll decrease the performance of the cells n the regon. Thus, the optmzaton problem for STC dstrbuton may be formulated as Mnmze Φ (11) subject to Is I, 1,2,..., j s j = m (12) max where I sj denotes the total current passng through STC s j and I smax s an upper bound on the current flowng through the STC. (The ratonale s that when t was decded that cell row R should have m sleep transstors on t, that decson was n part based on the assumpton that no sleep transstor wll have to carry more than I smax.) The mnmum Φ value wll be denoted by Φ mn. 4. PROPOSED APPROACH In ths secton, we present an optmal soluton to the STC dstrbuton problem where m<n. For m n, t s easy to see that Φ mn can be acheved trvally by enforcng x s =x c, =1,2,,n. Let P={p j, j=1,2,,m} denote a partton of the set of cells C n row R. Let x pj denote coordnate of the rghtmost cell n p j. Defnton 1: A vald partton s a partton that satsfes the followng two constrants: 1) x p1 <x p2 < <x pm ; 2) any cell c belongng to secton p j satsfes the condton that x pj-1 <x c x pj. All vald parttons compose the vald partton space, Ω. (7) (8) Defnton 2: A true soluton to the STC placement s a vald partton that addtonally satsfes the followng: 1) there s exactly one sleep transstor s j n each secton p j ; 2) wthn each secton Φ pj max { g( x s x ) ( )} j c SL c c p (13) j s mnmum. All true solutons compose true soluton space, Σ. Lemma 1: Consder a true soluton σ on the vald partton P={p j, j=1,2,,m}. Defne Ψ= max Φ pj, where Φ pj s 1 j m defned n equaton (13). We have: Φ Ψ. Proof: Assume Φ= g( xs x ) ( ) j c SL c, where c s a cell and s j s the sleep transstor assocated wth secton p j. There are two cases to consder. Frst, f c p j, then Φ Φp, j Ψ, and the proof s complete. Second, f c p j, assume c p k (wth sleep transstor s k ), then from equaton (5): Φ g( xs x ) ( ) k c SL c Φpk Ψ. Lemma 2: Let Σ m denote the true soluton space for m sleep transstors and Ψ* m denote the mnmal Ψ value on space Σ m. The followng monotone property holds: m 1 <m 2, there exsts Ψ* m2 Ψ* m1. Proof: Gven m<n, assume σ m Σ m s a true soluton on a vald partton P. There must exst a secton p j that contans more than one cell. The correspondng sleep transstor s denoted by s j. Dvde p j nto two new sectons p j and p j+1, where p j+1 contans only cell c, the rghtmost one n p j,.e., x c =x pj. Obvously, the new partton P after ths dvson s also a vald partton. Now add a new sleep transstor for partton P and assgn t to locaton x c. Thus Φ p j+1 = SL(c ), whch s less than Φ pj based on defnton (13). A new true soluton σ m+1 Σ m+1 on the vald partton P can be obtaned by shftng s j so that Φ p j s mnmzed whle keepng other sleep transstors unaffected. From Defnton 2, there exsts Φ p j Φ pj, whch leads to Ψ σm+1 Ψ σm. Snce σ m s arbtrarly selected, the proof s complete. Theorem 1: The soluton wth a mnmal Ψ value n space Σ s an optmal soluton to the STC dstrbuton problem defned by equatons (11) and (12). Proof: Let σ* denote the soluton n space Σ m that has the mnmal Ψ value. Assume σ opt s an optmal soluton to the problem defned by equatons (11) and (12). Based on σ opt, we can construct a vald partton P of set C as follows. Frst, we sort sleep transstors n an ncreasng order of ther coordnates. Next, each cell s assgned to the secton correspondng to ts closest sleep transstor. Let m denote the number of sectons n P, where m m. Notce that m may be less than m because t s possble that a sleep transstor s not the closest one to any cell. Smlar to the proof of Lemma 1, we can easly show that Φσ Ψ. Conversely, from opt σopt the constructon procedure for partton P, we know

4 c p j, PL( c ) = g( xs xc ) SLc ( ), thus j Φ pj = max PL( c ) Φ, whch s followed by σ opt c p j Ψ σ = max Φ opt p, j Φ. So we have Φ σ σ =Ψ. opt opt σopt 1 j m Snce P s a vald partton for m sleep transstors, accordng to Lemmas 1 and 2 and because m m, t follows that Φ * * * * σ Ψ σ =Ψ m Ψ m ' Ψ σ =Φ opt σ. So σ* must opt also be an optmal soluton to the STC dstrbuton optmzaton problem and Φ mn =Ψ *. σ Based on Theorem 1, a smple approach for solvng the STC dstrbuton problem s to examne all possble vald parttons and select the true soluton wth the mnmal Ψ value. However, for n cells and m sleep transstors n a row, the number of vald parttons s 1 Cm n 1. In the case that n m=n/2, n 1 2 C m 1. So f n and m are large, the bruteforce approach wll be mpractcal. 2π We present an effcent dynamc programmng approach to search for the optmal soluton. Before descrbng the approach, we frst re-formulate the current balance constrant on STCs to facltate ts ncorporaton nto the proposed approach. By assumng a unform current dstrbuton n the row, the maxmal current constrant can be descrbed as a lmt on the number of cells that any secton n a vald partton can nclude. Let pn j denote the number of cells n secton j and pn max denote the preset upper bound of pn j. Constrant (12) can be restated as pnj pnmax, j = 1,2,..., m (14) pnmax n / m Assume the cell set C n row R s already sorted from left to rght. Defne functon Γ(, j, k) to represent the mnmal Φ value for k sleep transstors on a subset of cells n C from c to c j, where 1 j n, 1 k m. Thus Φ mn =Γ(1, n, m). From Theorem 1, we have Γ (1, jk, ) = mn max( Γ(1, j lk, 1), Γ( j l+ 1, j,1)) max( j ( k 1) pnmax,1) l l mn( pnmax, j) (15) and Γ (, j,1) = mnmax gl ( xs xc ) SL( c ) l l xs l j (16) In equaton (15), l denotes the number of cells n the rghtmost secton between c 1 and c j. Accordng to constrant (14), l should be no greater than pn max ; on the other hand, l has to be large enough so that the remanng cells can be put nto the remanng k 1 sectons. The pseudo-code for the optmal STC dstrbuton algorthm s presented n Fgure 2. Frst, Equaton (16) s solved for all Γ(, j,1) values, 1 j n, whch are stored n a table wth a dmenson of n n. The proposed dynamc programmng approach utlzes a table Γ(j), 1 j n, where each entry holds the computed value of Γ(1, j, k) durng the k th teraton; and table I(j, k), where each entry stores the l value n equaton (15) whch leads to the mnmal Γ(1, j, k). Lnes 3 to 9 embody the dynamc programmng teratons of updatng values n tables Γ(j) and I(j, k). The decrement of j from n to ensures that the updated entres of table Γ(j) wll not be used n the same k teratons, and thus, enables an nplace operaton. The procedure n Lne 11 traces back through ponters held n table I(j, k) and works as follows. Read the value n the I(j, k) entry. Assume I(j, k)=l, then assgn cells from c l+1 to c j to secton p k. Next, go to entry I(j l, k 1) and secton p k 1. Ths process contnues untl k=1. Fnally, after partton P s constructed, the coordnates of sleep transstors are obtaned by solvng Equaton (16) over each correspondng secton n P. STC Dstrbuton Algorthm INPUT: x c, =1,2,,n, coordnates of n cells n a row R; m, number of sleep transstor cells to be placed n R OUTPUT: Φ mn and x sj, j=1,2,,m, coordnates of m sleep transstor cells 1. Γ(,j,1) soluton to equaton (16),,j, 1 j n 2. Γ(j) Γ(1, j,1), j, 1 j n 3. for k = 2:m 4. for j=n:1 // j decrement 5. t 6. for l = max(j (k 1)pn max,1):mn(pn max, j k) 7. t mn (t, max(γ(, j l), Γ 1 (j l+1, j))) 8. I(k, j) l 9. Γ(j) t 10. Φ mn = Γ(n) 11. Trace back from I(m,n), and construct partton P of cells 12. x sj soluton to equaton (16) for each secton p j n partton P, j=1,2,,m Fgure 2. Optmal STC dstrbuton algorthm n a row It takes only O(n pn max ) teratons to calculate table Γ(, j,1); and n each teraton equaton (16) s solved once, whch n turn requres O(pn max ) multplcatons and addtons. Dynamc programmng emboded between lne 3 to 9 takes O(nm pn max ) teratons to obtan Φ mn, and fnally the traceback procedure n lne 11 takes m steps. Thus, the total tmng complexty s O(nm pn max + n pn max 2 ), snce m<n. Smlarly, table Γ(1, j, k) occupes O(n pn max ) memory space, and table I(j, k) O(nm). Thus the spatal complexty of ths algorthm s O(n pn max + nm). 5. EXPERIMENTAL RESULTS We used ISCAS benchmark crcuts and SIS to generate optmzed gate level netlsts; all benchmarks were frst optmzed by usng the SIS scrpt.rugged and dong tmngdrven technology mappng based on an ndustral-strength 90nm ASIC desgn lbrary. All benchmarks were run on SUN Ultra Spark II machne. We set the hgh V th values for PMOS

5 and NMOS as 303mV and 260mV, and the low V th values for PMOS and NMOS as 250mV and 200mV, respectvely. In our experments, we frst generated detaled row-based cell placements for the generated benchmark crcuts by usng the tmng-drven placer of [18]. We then calculated the number of sleep transstor cells to be placed at each row based on the Average Current Method (ACM) of [10], where the sze of every sleep transstor cell s determned so that ts on resstance, R s, comes out to be about 300Ω. Next we appled the proposed Optmal ST dstrbuton technque (from here we call t OSTD) for each placement row, whch s followed by a layout adjustment to remove overlaps between logc cells and sleep transstor cells. We compare OSTD wth the other sleep transstor cell placement methods used n [9], where all sleep transstor cells are located at the corners of each row so that they do not dsturb the exstng placement (from here we call ths method CSTD for Corner-based ST dstrbuton), n terms of the total wre length and crtcal path delay. In addton, we mplement another sleep transstor cell placement method, whch dstrbutes the sleep transstor cells unformly on the row, thereby, spacng equally between sleep transstors on the same row (from here we call ths method USTD for Unform ST dstrbuton.) We also compare OSTD wth USTD n terms of the crtcal path delay. To obtan these results, we perform global routng after the placement of sleep transstor cells so that the wrng loads of all nets may be accurately calculated. Next, we extract cell locatons and nterconnect parastcs and nput the whole extracted netlst to HSPICE so that we measure the crtcal path delay for the benchmark crcuts. To mnmze the smulaton tme, we run STA before HSPICE smulaton to dentfy the set of PI-PO crtcal paths and then apply nput vectors that cause the propagaton of an event along these paths. We therefore run HSPICE smulaton only for the nput vectors producng the transtons along the STA-dentfed tmng-crtcal paths. Fgure 3 presents transent smulatons of the vrtual ground lne of the frst row n the layout of crcut C7552, operatng at a supply voltage of 1V. Compared to CSTD, OSTD reduces the vrtual ground bounce by about 50%, from 250mV to 180mV. Ths reducton of vrtual ground bounce tends to mprove the performance of the crcut. (a) CSTD (b) OSTD Fgure 3. Smulaton results for vrtual ground bounce Table 1 shows comparson results between OSTD and CSTD n terms of crtcal path delay and wre length. For each crcut benchmark, we generated 10 dfferent placement solutons (correspondng to dfferent random seeds for the tmng-drven placer.) Therefore, we also generated 10 dfferent sets of wre lengths and crtcal path delays, and reported n Table 1 only the mean values of each fgure of mert.) Based on these results, we conclude that OSTD reduces the crtcal path delay by an average of 11% at the cost of an average of 0.7% ncrease n the total wre length for the benchmark crcuts. The ncreased total wre length s caused by pushng or pullng some logc cell durng the layout adjustment step needed to remove the overlaps between the sleep transstors and logc cells. The last column n Table 1 shows the runtme of OSTD algorthm for the benchmark crcuts. Table 2 shows comparson results between OSTD and USTD n terms of the crtcal path delay. OSTD reduces the crtcal path delay by an average 3.8% compared to USTD. Notce that we lmted ourselves to small crcut benchmarks due to the lack of capacty by Hspce to smulate large crcuts. We expect that the advantage of our proposed method (OSTD) over CSTD and USTD becomes more pronounced as the number of logc cells n the crcut ncreases. Table 2 Comparsons of Crcut Performance between USTD and OSTD Crtcal Path Delay (ns) Crcut Reducton USTI OSTI C % C % C % C % C % C % C % C % C % Avg. 3.84%

6 6. CONCLUSION An optmal sleep transstor cells placement methodology for MTCMOS crcuts was presented. The presented algorthm provdes optmal locatons of sleep transstor cells for the standard cell-based layout desgn so that the performance degradaton of MTCMOS crcut due to the nterconnect resstance of the vrtual ground network s mnmzed. References [1] F. Fallah and M. Pedram, "Standby and actve leakage current control and mnmzaton n CMOS VLSI crcuts." IEICE Trans. on Electroncs, Vol. E88 C, No. 4, pp , Apr [2] S. Mutoh, T. Dousek, Y. Matsuya, T. Aok, S. Shgematsu, and J. Yamada, 1-v power supply hghspeed dgtal crcut technology wth multthresholdvoltage CMOS, IEEE J. Sold-State Crcuts, vol. 30, pp , Aug [3] S. Mutoh, S. Shgematsu, Y. Matsuya, H. Fukuda, and J. Yamada, A 1-v multthreshold-voltage CMOS dgtal sgnal processor for moble phone applcaton, IEEE J. Sold-State Crcuts, vol. 31, pp , Nov [4] J. Kao, A. Chandrakasan, and D. Antonads, Transstor szng ssues and tool for mult-threshold CMOS technology, n Proc. IEEE/ACM Desgn Automaton Conf., 1997, pp [5] V. Khandelwal and A. Srvastava, Leakage control through fne-graned placement and szng of sleep transstors, n Proc. ACM/IEEE Int. Conf. on Computer Aded Desgn, 2004, pp [6] B. H. Calhoun, F A. Honore, and A. Chandrakasan, Desgn methodology for fne-graned leakage control n MTCMOS, n Int. Symp. Low Power Electroncs and Desgn, 2003, pp [7] H. Won, K. Km, K. Jeong, K. Park, K. Cho, and J. Kong, An MTCMOS desgn methodology and ts applcaton to moble computng, n Int. Symp. Low Power Electroncs and Desgn, 2003, pp [8] J. Kao, S. Narenda, and A. Chandrakasan, MTCMOS herarchcal szng based on mutual exclusve dscharge patterns, n Proc. ACM/IEEE Desgn Automaton Conf, 1988, pp Crcut [9] M. Ans, S. Areb, and M. Elmasry, Desgn and optmzaton of Mult-threshold CMOS crcut, IEEE Trans. Computer-Aded Desgn of Integrated Crcuts Systems, vol. 22, pp , Oct [10] S. Mutoh, S. Shgematsu, Y. Gotoh, and S. Konaka, Desgn method of MTCMOS power swtch for lowvoltage hgh-speed LSIs, n Proc. Asan and South Pacfc Desgn Automaton Conf, 1999, pp [11] K. Usam, N. Kawabe, M. Kozum, K. Seta, and T. Furusawa, Automated selectve mult-threshold desgn for ultra-low standby applcatons, n Int. Symp. Low Power Electroncs and Desgn, 2002, pp [12] T. Ktahara, N. Kawabe, F. Mnam, K. Seta, and T. Furusawa, Area-effcent selectve mult-threshold CMOS desgn methodology for standby leakage power reducton, n Proc. Desgn Automaton and Test n Europe, 2005, pp [13] C. Long and L. He, Dstrbuted sleep transstor network for power reducton, IEEE Trans. Computer- Aded Desgn of Integrated Crcuts Systems, vol. 12, pp , Sep [14] N. Ohkubo and K, Usam, Delay modelng and statc tmng analyss for MTCMOS crcuts, n Proc. Asan and South Pacfc Desgn Automaton Conf, 2006, pp [15] C. Hwang, C. Kang, and M. Pedram, Gate szng and replcaton to mnmze the effects of vrtual ground parastc resstances n MTCMOS desgns, n Int. Symp. Qualty Electronc Desgn, 2006, pp [16] P. Babghan, L. Benn, A. Mac, and E. Mac, Postlayout leakage power mnmzaton based on dstrbuted sleep transstor nserton, n Int. Symp. Low Power Electroncs and Desgn, 2004, pp [17] T. Sakura and A. Newton, Alpha-power law MOSFET model and ts applcatons to CMOS nverter delay and other formulas, IEEE J. Sold-State Crcuts, vol. 25, pp , Apr [18] C. Hwang and M. Pedram, Tmng-drven placement based on monotone cell orderng constrants, n Proc. Asan and South Pacfc Desgn Automaton Conf, 2006, pp Table 1 Comparsons of Crcut Performance between CSTD and OSTD CSTI Wre length OSTI Increase Crtcal Path Delay (ns) CSTI OSTI Reducton CPU (sec) C % % 0.01 C % % 0.01 C % % 0.01 C % % 0.01 C % % 0.01 C % % 0.01 C % % 0.02 C % % 0.02 C % % 0.02 Avg. 0.69% 11.22%