AN EFFICIENT TECHNIQUE FOR DEVICE AND INTERCONNECT OPTIMIZATION IN DEEP SUBMICRON DESIGNS. Jason Cong Lei He

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1 AN EFFICIENT TECHNIQUE FOR DEVICE AND INTERCONNECT OPTIMIZATION IN DEEP SUBMICRON DESIGNS Jason Cong Le He Department of Computer Scence Unversty of Calforna, Los Angeles, CA ABSTRACT In ths paper, we formulate a new class of optmzaton problem, named the general CH-posynomal program, and reveal the general domnance property. We propose an ef- cent algorthm based on the extended local renement operaton to compute lower and upper bounds of the exact soluton to the general CH-posynomal program. We apply the algorthm to solve the smultaneous transstor and nterconnect szng (STIS) problem under the table-based devce model, and the global nterconnect szng and spacng (GISS) problem wth consderaton of the crosstalk capactance. Experment results show that our algorthm can handle many devce and nterconnect modelng ssues n deep submcron desgns and s very ecent. 1. INTRODUCTION The nterconnect delay has become the domnant factor n determnng the crcut performance n deep submcron (DSM) desgns. Many optmzaton technques have been proposed to reduce nterconnect delay, ncludng nterconnect topology optmzaton, buer nserton, and devce and nterconnect szng (see [1] for a comprehensve survey). In ths paper, we study the smultaneous devce and nterconnect szng problem n the context of DSM desgns. Several recent studes [2, 3, 4, 5, 6, 7] consdered the smultaneous devce and nterconnect szng problem. However, most of these works used over smpled models for devces and nterconnects, whch are not capable of modelng many DSM ssues. For example, a gate of sze d s modeled by an eectve resstor r d = r0=d, where r0 s the eectve resstance of the unt-sze gate, and s assumed ndependent of the sze, nput waveform slope, and output load of the gate. Moreover, the capactance for wre of wdth w and length l s gven by c a w l + cf l, where ca and c f are unt-area capactance and frnge capactance for the wre. Both are assumed to be constants. These assumptons, however, are no longer realstc, especally for DSM desgns. For example, n Table 1, we computed the eectve drver resstance r0 va HSPICE smulaton for an nverter under the rsng nput (.e., r0 of the n-transstor n the nverter) based on the representatve Permsson to make dgtal or hard copes of all or part of ths work for personal or classroom use s granted wthout fee provded that copes are not made or dstrbuted for proft or commercal advantage and that copes bear ths notce and the full ctaton on the frst page. To copy otherwse, to republsh, to post on servers or to redstrbute to lsts, requres pror specfc permsson and/or a fee. ISPD 98, Aprl 6-8, 1998, Monterey, CA USA 2000 ACM ISBN x/98/04 $ sze = 100x n-transstor p-transstor c l / t t 0.05ns 0.1ns 0.2ns 0.05ns 0.1ns 0.2ns 0.225pF pF pF pF pF sze = 400x n-transstor p-transstor c l / t t 0.05ns 0.1ns 0.2ns 0.05ns 0.1ns 0.2ns 0.501pF pF pF pF pF Table 1. Unt-sze resstance r0 for a n-transstor of derent szes, nput transton tmes (t t) and output loads (c l). 0:18m technology n SIA roadmap [8] for two derent szes (100x and 400x of the mnmum sze). Derent combnatons of nput transton tmes and output loads are used for measurng. As one can see, r0 s clearly not a constant. Its value may der by a factor of 2. We also computed the capactance of a vctm wre centered between two neghborng wres n the same layer and both top and down grounds two-layer away from the vctm (see Fgure 1). We use a 3D eld solver FastCap [9] and geometrc parameters for the 0:18m technology n [8]. Fgure 2.(a) depcts the ground capactance (c g)between the vctm and grounds, wth each curve for derent wre wdths under a specc spacng as shown n Fgure 1. It s seen that nether c a nor c f s a constant because none of these curves s lnear and derent curves have derent ntercepts. The total capactance of the vctm s c total = c g + c x, where c s the crosstalk capactance between the vctm and the neghborng wres. One can dene the eectve-frnge capactance c ef = c f +c x as n [10], and compute c total = c a w l +cef l. We also obtaned c ef under xed ptch-spacngs 1 for derent wdths (see Fgure 2.(b)). Clearly, c ef s a not a constant, ether. We say that a devce model s a smple model f t assumes that r0 s a constant, and a capactance model s a smple model f t assumes that both c a and c ef are constants. In contrast, a devce model s a general model f t can handle a non-constant r0, and a capactance model s a general 1 As shown n Fgure 1, spacng means edge-to-edge spacng, whch s dstngushed from ptch-spacng.

2 spacng ptch-spacng wdth spacng Fgure 1. The geometrc structure for capactance extracton. ground cap(ff/um) space = 0.33 space = 0.66 space = 0.99 space = wdth (um) (a) effectve-frnge cap (ff/mu) pt ch-space = 1.10 ptch-space = wdth (um) Fgure 2. (a) Ground capactances gven by Fast- Cap; (b) Eectve-frnge capactance for xed ptchspacngs. model f t does not assume that c a and c ef are constants (varable c ef s necessary to handle c x). Smple devce and capactance models were used n most prevous work, except a few recent works where more accurate models were used. In [4], a sequental quadratc programmng method s used to solve the smultaneous gate szng and wre szng problem under both smple gate model and a voltage-ramp gate model (a general model). The latter model acheves better results but s 10x slower. Two very recent works [11, 10] consder crosstalk capactance between neghborng wres. However, both assumes that c a and c f are constants (but allow varable c x). Moreover, the runtme at these algorthms s already hgh. For example, t took 1379 seconds to optmze a 16-bt bus of 320 wre segments n [10]. In ths paper, we solve the smultaneous transstor and nterconnect szng (STIS) problem under the table-based devce model, and the global nterconnect szng and spacng (GISS) problem wth consderaton of the crosstalk capactance. Our algorthms are capable to apply arbtrarly accurate models for devce delay and wre capactances, usng table-lookup and/or hgh-order complex characterstc functons, yet stll guarantee to compute the lower and upper bounds of the exact soluton very ecently. Our mplementaton uses table-based models, where devcedelay tables are generated usng HSPICE smulatons, and wre-capactance tables are generated usng 3D extractons. These table entres are very accurate, and nterpolaton and extrapolaton are used for data ponts not n the tables. These table-based models are wdely used n ndustry for vercatons, but seldom for layout optmzaton. Experment results show that our algorthms are very eectve and extremely ecent. Compared wth STIS results n [6] and GISS results n [10], up to 16.5% and 11% delay reductons are obtaned, respectvely. Meanwhle, a 100x speedup over the algorthm n [10] s acheved. (b) Our algorthm s based on a new class of optmzaton problem formulated n ths paper. We call t the general CH-posynomal program, and present ts formulaton and property n Secton 2. We solve the smultaneous transstor and nterconnect szng (STIS) problem under a table-based devce model n Secton 3., and the global nterconnect szng and spacng (GISS) problem consderng the crosstalk capactance n Secton 4. We conclude the paper n Secton 5. Proofs of all theorems are gven n a techncal report [12]. 2. THEORY OF CH-POSYNOMIAL PROGRAMS 2.1. Revew of smple and bounded-varaton CHposynomal programs In [6], the CH-posynomal (Cong-He posynomal) s dened as a functon of postve vector X = f j =1; ;ng wth the followng form: mx mx nx nx f(x) = x p ) (b qj(x) x q j ) p=0 q=0 =1 j=1;j6= where a p(x) 0 and b qj(x) 0 (1) ( ap(x) Then, the smple CH-posynomal and bounded-varaton CH-posynomal are dened as the followng: Denton 1 (Smple CH-posynomal) Eqn. (1) s a smple CH-posynomal f coecents a p(x) and b qj(x) are constants. Denton 2 (Bounded-Varaton CH-posynomal) Eqn. (1) s a bounded-varaton CH-posynomal f coecents satsfy the followng condtons: () for any p and, a p(x) s a functon dependng only on. Wth respect to an ncrease of, a p(x) monotoncally ncreases for any p, but a p(x) stll monotoncally decreases for any p 6= 0. x p ()for any q and j, b qj(x) s a functon dependng only on x j. Wth respect to an ncrease of x j, b qj(x) monotoncally decrease for any q, but b qj(x) x q j stll monotoncally ncreases for any q 6= 0. Note that the bounded-varaton CH-posynomal s orgnally called the general CH-posynomal n [6]. In ths paper, we rename t and use the name general CH-posynomal to refer to a more general formulaton dened n Denton 5 later on. We dene the CH-posynomal program as an optmzaton problem to mnmze a CH-posynomal Eqn. (1), subject to L X U (.e., l x u for =1; ;n). It may bea smple or bounded-varaton CH-posynomal program. The domnance property s revealed based on followng concepts: Denton 3 (Domnance Relaton) For two vectors X and X 0, we say that X domnates X 0 (denoted byx X 0 ) f x 0 for =1; ;n. Denton 4 (Local Renement Operaton) For a soluton vector (or smply, a soluton) X 0, the local renement operaton wth respect to any partcular varable and functon f(x) s to mnmze f(x) by only varyng whle keepng all values of other x 0 j(j 6= ) n X 0 and usng coecents wth respect to X 0 n case of a bounded-varaton CH-posynomal. Such an operaton s also called LR operaton n short. The resultng soluton s called the local renement of X 0 (wth respect to ). 46

3 Theorem 1 (Domnance Property) Let f(x) be a smple or bounded-varaton CH-posynomal, and X an exact soluton to mnmze f(x). For any soluton X 0 of f(x), f X 0 domnatng X,alocal renement of X 0 stll domnates X ;fx 0 domnated byx,alocal renement of X 0 s stll domnated byx Theory of general CH-posynomal program In ths paper, we propose the followng general CHposynomal. Denton 5 (General CH-posynomal) Gven a lower bound L and an upper bound U of the solutons, Eqn. (1) s a general CH-posynomal, f coecents are functons of vector X, and for L X U, the value of any coecent s bounded,.e., for any p and, there exst a mn p such that a mn p exst b mn qj a p(x) a max p and b max qj such that b mn qj and a max p, and for any q and j, there b qj(x) b max qj. We extend our denton of local renement operaton to consder a general CH-posynomal program to mnmze a general CH-posynomal. Denton 6 (Extended Local Renement Operaton) For any soluton X 0, the extended local renement operaton wth respect to any partcular varable and general CH-posynomal f(x) s to mnmze f(x) only by varyng whle keepng the value of any x 0 j(j 6= ) n X 0 and usng the followng coecents: () For X 0 X and any p, we use a max p nstead of a p(x 0 ) for a p(x 0 ) x p a pj (X 0 ) x p j for b p(x 0 ) x p and any, and a mn pj nstead of a pj(x 0 ) for and any j 6= ; we also use b mn p nstead of b p(x 0 ) and any, and bmax pj nstead of b pj(x 0 ) for b pj(x 0 ) x p j and j 6=. () For X 0 X and any p, we use a mn p nstead of a p(x 0 ) for a p(x 0 ) x p a pj (X 0 ) x p j and any, and a max pj nstead of a pj(x 0 ) for and any j 6= ; we also use b max p nstead of b p(x 0 ) for b p(x 0 ) x p b pj(x 0 ) x p j and any j 6=. and any, and b mn pj nstead of b pj(x 0 ) for We say that the result soluton s the extended local renement of X 0 (wth respect to ). Later on, we use ELR to denote the extended local renement. We have proved the followng theorem: Theorem 2 (General Domnance Property) Let X be an exact soluton to mnmze a general CH-posynomal f(x). For any X 0 domnatng X, an extendedlocal renement of X 0 stll domnates X ;For any X 0 domnated by X, an extendedlocal renement of X 0 s stll domnated by X. We say that a soluton X s the lower bound of the exact soluton X f X s domnated by X, and X s an upper bound of X f X domnates X.Alower or upper bound s ELR-tght f t can not be mproved by any ELR operaton. Based on the general domnance property, we propose a smple ELR-based algorthm (see Table 2) to compute the ELR-tght lower and upper bounds. Startng wth the ntal lower and upper bounds (L and U), the algorthm carres out nterleave passes of lower- and upper-bound computatons. A pass of lower bound computaton s to perform an ELR operaton on every of a lower 1. Intalze lower and upper bounds; 2. If lower and upper bounds do not meet 3. Perform ELR operaton on every of lower bound; 4. Perform ELR operaton on every of upper bound; 5. Goto 2 f there s any mprovement n 3 and 4; 6. Return ELR-tght lower and upper bounds; Table 2. ELR-based bound-computaton algorthm bound X. The ELR operatons can be n any order. Because X s domnated by X, ts extended local renement becomes closer to X but s stll a lower bound. Smlarly, a pass of upper bound computaton s to perform an ELR operaton on any of an upper bound X. The teraton of passes s stopped when the lower and upper bounds meet for every, or both bounds are ELR-tght. Because the range of coecents n a general CH-posynomal depend on the sze of the soluton space, lower- and upper-bound computatons are carred out alternately to narrow the range of the coecents. The algorthm s optmal n the sense that there exsts an exact soluton wthn the result ELR-tght lower and upper bounds. We wll use the algorthm to solve the devce and wre szng problems to be formulated n the next secton under general devce and capactance models. 3. STIS PROBLEM USING GENERAL DEVICE MODEL 3.1. Problem Formulaton We use the transstor szng formulaton n ths paper. Smlar to [6], our delay formulaton s based on the delay for a stage. A stage s dened as a DC-connected path from apower supply (ether the Vdd or the ground) to the gate node of a transstor, contanng both transstors and wres. The delay of a stage P (N s;n t) wth N s the source and N t beng the snk can be wrtten as Eqn. (2) under the Elmore delay model. t(p X (N s;n t); X) X = f(; j) r0() c a(j) x j + ;j ;j X + g() r0() r0() h()+x +X f(; j) r0() c ef(j) h() r0() (2) where s the wdth for a transstor M or a wre E, r0() s the unt-sze resstance, and c a() and c ef() are the unt-area and eectve-frnge capactances. Coecents f(; j); g() and h() are determned by the transstor netlst and routng topology. In order to smultaneously mnmze delays along multple crtcal paths, t s proposed to mnmze the weghted delay t(x) of all stages n the set of crtcal paths denoted as P: X t(x) = t(p (N s;n t); X) (3) P(N s;n t)2p where the weght ndcates the crtcalty of stage P (N s;n t). After we elmnate those terms ndependent of X, Eqn. (3) s re-wrtten as t(x) = X ;j F (; j) r0() c a(j) x j + X ;j F (; j) r0() c ef(j) 47

4 X + G() r0() +X H() r0() (4) where F (; j); G() and H() are weghted functons of f(; j); g() and h(), respectvely. We formulate the followng smultaneous transstor and nterconnect szng (STIS) problem: Formulaton 1 Gven the lower and upper bounds (L and U) for the wdth of each transstor and wre, the STIS problem s to determne a wdth for each transstor and wre (or equvalently, a szng soluton X, L X U) such that the weghted delay through multple crtcal paths gven by Eqn. (4) s mnmzed. Note that a sequence of szng problems to mnmze weghted delay can be used to mnmze the maxmum delay by adjustng the weght assgnment based on the Lagrangan-relaxaton method as n [5]. Therefore, we focus on how to mnmze weghted delay n ths paper. In addton, we nd dscrete wdth from a nte wdth set determned by the technology. Ths dscrete szng formulaton s more practcal and more dcult than the contnuous szng formulaton Property and Algorthm When r0, c a and c ef are constants under the smple models, Eqn. (4) s a smple CH-posynomal. In ths case, the STIS problem s a smple CH-posynomal problem solved n [6]. Because the smple models are no longer vald for DSM desgns, we study the STIS problem under a general devce model where r0 s not a constant. For smplcty, we assume that c a and c ef are constants, and wll remove the assumpton n Secton 4. The table-based model s a general model. In our tablebased model, as shown n Table 1, values for r0 are precomputed and stored n three-dmensonal tables ndexed by the transstor sze, nput slope and output load. Ths model could be very accurate dependng on the table sze. Gven the fact that r0 depends on the transstor sze, nput transton tme and output load and that there s a large range for r0, r0 s unlkely a functon of any sngle szng varable. It s necessary to treat t as a functon of the whole szng soluton X. Therefore, wehave the followng Theorem 3: Theorem 3 The STIS problem under the table-based devce model s a general CH-posynomal program. Based on Theorem 3, the ELR-based algorthm (Table 2) can be used to compute the lower and upper bounds for the exact soluton to the STIS problem. The ELR operaton s used for transstors. In an ELR operaton on a transstor M for the lower bound computaton, we use r0 mn () (nstead of r0()), and r0 max (j) (nstead of r0(j)) for any transstor M j other than M, where r0 mn () s the mnmum possble value for r0() and r0 max (j) s the maxmum possble value for r0(j). Symmetrcally, n an ELR operaton on M for the upper bound computaton, we use r0 max () (nstead of r0()) for M, and r0 mn (j) (nstead of r0(j)) for any transstor M j other than M, where r0 max () s the maxmum possble value for r0() and r0 mn (j) s the mnmum possble value for r0(j). We determne the mnmum and maxmum values for r0 accordng to current lower and upper bounds. We assume that r0 ncreases wth respect to an ncrease of the transstor sze and nput transton tme (the nput t t), but t decreases wth respect to an ncrease of output load c l. Therefore, r0 mn () for M can be obtaned by table lookup usng the lower bound of sze, the lower bound of the nput t t and the upper bound of c l.we use c l under the current upper bound of the szng soluton as the upper bound of c l. We set two ntal lower and upper bounds for t t, and update these two bounds durng optmzaton procedure by assumng that the lower bound of the output t t for M occurs when M s drven by alower bound of the nput t t and s drvng the upper bound of c l. Symmetrcally, r0 max () sdetermned usng the upper bound of, the upper bound of nput t t and the lower bound of c l. As the lower and upper bounds of szng soluton move closer durng the ELR-based optmzaton procedure, the range of r0 s also narrowed. In general, the closer the values for r0 max and r0 mn, the tghter the lower and upper bounds gven by the ELR operatons. Because the unt-sze resstance r0() s a constant for each wre segment E,we can smply use the LR operaton for E. In addton, the optmal wre wdths are monotonc wthn each wre segment. Therefore, we use the bundled renement operaton [13] nstead of LR operaton for wre segment E. The bundled renement operaton s a speedup scheme for the LR operaton, and shown to be 100x faster than the LR operaton for the wreszng problem. Let L 0 and U 0 be the lower and upper bounds gven by the above bound computaton procedure. If L 0 and U 0 are dentcal, we obtan the exact soluton to the STIS problem under the table-based devce model. Otherwse, we traverse all wre segments and transstors by teratve LR operatons untl there s no mprovement n the last round of traversal. Ths procedure s bounded by L 0 and U 0, and s nvoked twce startng wth L 0 and U 0, respectvely. We use the better soluton from the two runs as the nal soluton. Even though ths type of LR operaton may lead to further mprovement over L 0 and U 0, n general, t does not leads to a lower or upper bound of the exact soluton Experment results In ths secton, we apply our STIS algorthm to two global nets. One s a 2cm lne wth 5 buers optmally nserted for delay mnmzaton. The other s a buered tree, the dclk net n a spread spectrum IF transcever chp desgn [14]. There are 117 drvers and 37 buers wth total wre length of m. We use parameters based on the 0.18 m technology gven n [8]. The wre sheet-resstance R2 = 0:0638. Based on parameters gven n [8], we generate devce tables usng HSPICE, and use c a and c ef values when the wre s 1:10m wde and neghborng wres are 1:65m away. We compare szng solutons obtaned under derent devce models, smple model versus table-based model. We also use derent szng formulatons, smultaneous gate and wre szng (sgws) versus smultaneous transstor and wre szng (sts). There are four combnatons, ncludng sgws/smple and sts/smple usng the LR-based algorthm as n [6], and sts/smple and sts/table usng new developed ELR-based algorthm. The value for r0 n the smple model s determned under the typcal nput, devce sze and output load. We assume the xed rato between p- and n- transstors for the gate szng formulaton s smply 1.0. For both nets, we nd the optmal wre wdth for each 10m-long wre, and assume that allowable transstor szes are multples of 0.18m between 0.18m and 144m and allowable wre wdths are multples of 0.56m between 0.56m and 5.6 m. Table 3 gves expermental comparson between derent 48

5 net sgws/smple sgws/table sts/smple sts/table sgws/smple sgws/table sts/smple sts/table convergence for transstors convergence for wre dclk 85.8% 83.2% 87.7% 86.7% 99.4% 95.9% 97.1% 95.2% lne 60.0% 100% 70.0% 60.0%) 98.4% 70.9% 88.4% 72.9% average wdth / average gap (for transstors, m) average wdth / average gap (for wres, m) dclk 5.39/ / / / / / / /0.030 lne 108/ / / / / / / /0.091 maxmum delay (ns) runtme (s) dclk (-6.4%) 1.132(-2.3%) (-15.1%) lne (-0.4%) 0.751(-8.6%) 0.694(-16.5%) Table 3. Comparsons between derent devce and wre szng algorthms: sgws/smple { smultaneous gate and wre szng under smple model, sts/smple { smultaneous transstor and wre szng under smple model, and sts/table { smultaneous transstor and wre szng under table-based model. szng formulatons. We computed convergence for transstors and wres. A transstor or wre s convergent f ts lower and upper bounds gven by the LR- or ELR-based algorthms are dentcal. It s seen that the convergence are not sgncantly derent. For example, transstors n dclk net have about 85% transstor convergent under all four formulatons. We also computed the average wdth and the average gap between lower and upper bounds. The ELR-based algorthm does gve larger gap than the LRbased algorthm. However, the derence s small. Overall, the average gap s only 1% of the average wdth, except for transstors n net dclk. Therefore, the ELR-based algorthm gves solutons whch are close to the exact soluton under the table-based devce model. Gven that the ELR-tght lower and upper bounds are close to each other, we smply use the lower bound as the nal soluton. We computed the maxmum delays va HSPICE usng the dstrbute RC model and the level-3 MOSFET model. When compared wth the sgws/smple formulaton, sgws/smple, sts/smple and sts/table formulatons reduce the maxmum delay by up to 6.4%, 8.6%, 16.5%, respectvely. The solutons under the table-based devce model are consstently better than those under the smple devce model. Although the ELR-based algorthms for the table-based devce model has longer runtmes, the maxmum runtme s just 3.17 seconds. Therefore, our ELRbased algorthms s eectve ecent for the STIS problem. 4. GISS PROBLEM CONSIDERING CROSSTALK CAPACITANCE The constant c a and c ef are assumed for the STIS problem n Secton 3. We proceed to remove ths assumpton by usng a general capactance model. For smplcty of presentaton, we assume that the devce szes are xed and study the global (mult-net) wre szng and spacng (GISS) problem n ths secton. However, our algorthm and mplementaton are able to use general models for both devce and capactance at the same tme Problem formulaton Our general capactance model s a 2D model smpled from the 2.5D model n [15]. We consder the area, frnge and crosstalk capactances for a wre n the 2D model. We assume that c a and c ef are functons of wdths and spacngs (see Fgure 1). Based on ths assumpton, we rst use a 3D eld solver lke FastCap to buld tables for c a and c ef under derent wdth and spacng combnatons. Then, table lookup s used durng layout optmzaton to obtan c a and c ef for the gven wre wdth and spacng. neghborng wre E1 E2 neghborng wre (a) Symmetrc wreszng neghborng wre E1 E2 neghborng wre (b) Asymmetrc wreszng Fgure 3. (a) Symmetrc wre szng, and (b) Asymmetrc wre szng. Our GISS formulaton was rst presented n [10]. It assumes that an ntal layout s a pror gven and that the ntal central-lnes and ntal ptch-spacngs dened by the ntal layout reman unchanged durng the szng procedure. Even though c a() and c ef () for a wre segment E are functons of wdth and spacngs n the 2D capactance model, they are functons only explctly depends on wdth. Therefore, we can stll use the delay formulaton Eqn. (4). We consder two wre szng formulatons. One s the symmetrc wre szng formulaton, where wres are always symmetrc wth respect to ntal central-lnes as llustrated n Fgure 3(a). In contrast, n the asymmetrc wre szng formulaton shown n Fgure 3(b), wres of same wdths are asymmetrc wth respect to ntal central-lnes, and has smaller capactance and delay. Gven that neghborng wres are n general asymmetrcally away from nterested nets, the asymmetrc wre szng formulaton s capable to further reduce the nterconnect delay. In the asymmetrc formulaton, the wre szng soluton for wre segment E s needed to be represented by a par of wdths (x ", x# ), where x" s the wdth of the wre above (or left to) the ntal central-lne when E s a horzontal (or vertcal) segment, and x # s the wdth of the wre on the other sde of the ntal central-lne. In order to mantan the connectvty, we assume that x " and x# are at least W mn=2, where W mn s the mnmum wre wdth set by the manufacture technology. We rst present algorthms for the symmetrc wre szng formulaton, then extend the algorthms to consder the asymmetrc wre szng formulaton Algorthm for symmetrc GISS problem We often observes the followng (lke the case of ptchspacng = 1.10 m n Fgure 2.(b)): 49

6 Observaton 1 In a geometrc structure as n Fgure 1 where the central wre E has two neghborng wres at equal and xed ptch-spacngs, f the wdth of E ncreases symmetrcally wth respect to ts ntal central-lne, then c a() decreases, but both c a() and c ef () ncrease. We have proved that Theorem 4 The GISS problem s a bounded-varaton CHposynomal program f each wre segment satses Observaton 1 for any vald wdths (and spacngs). In ths case, the LR operaton can be used to replace the ELR operaton n the ELR-based algorthm (Table 2). For example, to tghten a lower bound for a horzontal wre E,we assume that ts neghborng wres have lower-bound wdth and dene top spacng s " and down spacng s # for E.We derve unt area-capactance c a(;s " ;s# ) and unt eectve-frnge capactance c ef(;s " ;s# ) accordng to x, s " and s# and perform an LR operaton on x. The result local renement of moves closer to but remans smaller than x, the wdth of E n the exact soluton to the GISS problem as a bounded-varaton CH-posynomal program. Smlarly, we assume that neghborng wres have upperbound wdths n order to perform an LR operaton on the upper-bound wdth of wre E. Observaton 1 does not always hold. For example, for a large enough ntal-spacng, f wdth ncreases (and spacng decreases), then c f decreases and c ncreases, whch results n c ef = c f + c x beng a non-monotonc functon of wre wdth and Observaton 1 fals (see the case of ptch-spacng = 2.2m n Fgure 2.(b)). Therefore, wehave Theorem 5: Theorem 5 The GISS problem under the general capactance model s a general CH-posynomal program. In the case, the ELR operaton s needed n the ELR-based algorthm (Table 2). Let c mn a () and c max a () be maxmum and mnmum values for c a(), and c mn ef () and c max ef () be the mnmum and maxmum values for c ef (). Wth respect to these values and delay formulaton Eqn. (4), we perform the ELR operaton for the lower-bound computaton on a wre E,by usng c max a () and c mn ef () (nstead of c a() and c ef()) for E, and usng c mn 0 (j) and c mn ef (j) (nstead of c0(j) and c a(j)) for any edge E j other than E. Smlarly, the ELR operaton for the upper-bound computaton of E can be performed by usng c mn a () and c max ef () (nstead of c a() and c ef ()) for E, and usng c max 0 (j) and c max ef (j) (nstead of c0(j) and c a(j)) for any edge E j other than E. We combne LR and ELR operatons n our boundcomputaton algorthm. When workng on a wre E,we rst check capactance values wth respect to all vald wdths and spacngs of E, then use ether an LR or an ELR operaton accordng to Observaton 1. If the result wre wdth s for E, then x " = x# = =2. Therefore, startng wth the mnmum and maxmum symmetrc wre szng solutons for all wre segments, the algorthm leads to lower and upper bounds of the exact global soluton to the symmetrc GISS problem Algorthm for asymmetrc GISS problem We rst extend the domnance relaton for the asymmetrc wre szng formulaton. We say that the wre szng soluton X domnates another soluton X 0 (denote as X X 0 ), f (x " ;x# ) (x0" ;x 0# ) (.e., x " x0" and x # x0# ) holds for any wre segment E. A lower and upper bound of the exact soluton to the asymmetrc GISS problem wll be determned accordng to the new denton of domnance relaton. We solve the asymmetrc GISS problem by augmentng the bound-computaton algorthm presented n Secton 4.2. Each LR or ELR operaton gves only the total-wdth, whch salower or upper bound of the optmal total-wdth x for E.To obtan an asymmetrc wre szng soluton, we need to map nto x " and x#, whch are respectve wdths for the \two peces" of wres around the ntal central-lne of E.Physcally, ths mappng s equvalent toembed a wre wth total-wdth around the ntal central-lne of E. Ths embeddng also aects the LR and ELR operatons n the subsequent steps.we propose to perform a conservatve embeddng rght after any LR or ELR operaton. Ths augmented algorthm wll lead to the lower and upper bounds of the exact soluton to the asymmetrc GISS problem. In the conservatve embeddng, wthout loss of generalty, we assume that E s a horzontal wre. We keep lower and upper bounds for the wdths of both upper-pece and lowerpece of E. Let x " and x " be current lower and upper bounds for the upper-pece wdth x ", and x # and x # be current lower and upper bounds for the lower-pece wdth x #. When we obtan a total-wdth n the lower-bound computaton, we update the lower bound of the lower-pece wdth as, x ", whch s the derence between the the lower bound of the total-wdth and the upper bound for the upper-pece wdth and s a conservatve lower bound for the lower-pece wdth. Smlarly, we update the lower bound of the upper-pece wdth as, x #. Note that the sum of the lower bounds of wdths for the two pece wres may be less than the lower bound of the total-wdth n the conservatve embeddng. Symmetrcally, when we obtan a total-wdth n the upper-bound computaton, the new x " = x, x#, and the new x# = x, x". The conservatve embeddng s also used to prove the asymmetrc eectvefrngng property n [10]. We also propose a greedy embeddng. We assume that neghborng wres of E have ther lower- (upper-) bound wdths durng lower- (upper-) bound computaton for E, and then nd x " and x # such that x " + x# = and the capactance for E s mnmzed. Ths heurstc embeddng leads to good expermental results as dscussed n [12] Experment results We have tested our GISS algorthm on a 16-bt parallel bus structure. In ths bus, each bt s a 1cm lne wth a 119 drver resstance and a 12.0fF snk capactance. We assume that these lnes are ntal equally spaced and nd an asymmetrc wre szng for every 500m-long wre segment. In addton, the mnmum wre wdth s 0:22m. The mnmum spacng s 0:33m. The allowable wre wdths are from 0.22 to 1.1 m, wth the ncremental step of 0.11 m. The capactance tables are generated usng 3D eld solver FastCap for the 0.18m technology n [8]. We call the GISS algorthm presented n ths paper GISS/ELR algorthm. An alternatve GISS algorthm was presented n [10] based on bottom-up dynamc programmng technque. It computes lower and upper bounds for the exact soluton to the asymmetrc GISS problem when c a and c f are constants, and we denote t as GISS/FAF. It may be extended to use varable c0 and c f n a general capactance model. In ths case, the exact soluton may be 50

7 ptch- Average Delay (ns) Run Tme (s) spacng MIN GISS/FAF GISS/VAF GISS/ELR GISS/VAF GISS/ELR 2x (-48%) 0.79(-48%) 0.79(-48%) x (-58%) 0.53(-60%) 0.52(-61%) x (-64%) 0.42(-67%) 0.42(-67%) x (-69%) 0.37(-70%) 0.36(-71%) x (-70%) 0.34(-72%) 0.32(-74%) Table 4. Comparson of derent szng algorthm when szng 16-bt buses under 2x-6x mnmum ptchspacng. MIN s the mnmum wre wdth (and thus maxmum spacng) soluton; GISS/FAF and GISS/VAF are bottom-up dynamc programmng algorthms; GISS/ELR s the algorthm presented n ths paper. outsde the range dened by the resultng lower and upper bounds, and we denote t as GISS/VAF. We optmzed the bus for derent ntal ptch-spacngs, from 2x to 6x of the mnmum ptch-spacng (0.55m). We report the average HSPICE delay among all snks n Table 4. The MIN s the soluton wth mnmum wre wdth and thus largest spacng to reduce the couplng capactance. It serves as the base for delay comparson. GISS/FAF and GISS/VAF further use a greedy algorthm to obtan nal solutons wthn the lower and upper bounds, whereas GISS/ELR uses the lower bound as the nal soluton due to ts hgher convergence. All GISS algorthms lead to solutons much better than the MIN soluton. Because the GISS problem s no longer a bounded-varaton CH-posynomal program n case of large ptch-spacngs, GISS/ELR acheves more mprovement (11% better than GISS/FAF and 5.9% better than GISS/VAF for 6x mnmum ptch-spacng). GISS/ELR s also 100x faster and uses much less memory. Detaled analyss on memory usage and convergence of bounds s ncluded n [12]. 5. CONCLUSIONS We formulated a new class of optmzaton problem, named the general CH-posynomal program, and propose an algorthm to compute lower and upper bounds of the exact soluton to the general CH-posynomal program. We appled the algorthm to solve devce and wre szng problems, wth consderaton of DSM ssues lke the table-based models for devce delay and nterconnect capactances ncludng crosstalk capactance between neghborng wres. Our algorthm acheves more delay reducton when compared wth prevous work, and s also extremely ecent. We plan to extend the algorthm to consder the hgher-order delay model n the future. We beleve that our general CH-posynomal formulaton and the bound-computaton algorthm can also be appled to other optmzaton problems n the CAD eld. ACKNOWLEDGMENTS Ths work s partally supported the NSF Young Investgator Award MIP and a grant from Intel Corporaton under the Calforna MICRO program. The authors would lke to thank the anonymous revewers for helpful comments. REFERENCES [1] J. Cong, L. He, C.-K. Koh, and P. H. Madden, \Performance optmzaton of VLSI nterconnect layout," Integraton, the VLSI Journal, vol. 21, pp. 1{94, [2] J. Cong and C.-K. Koh, \Smultaneous drver and wre szng for performance and power optmzaton," n Proc. Int. Conf. on Computer Aded Desgn, pp. 206{ 212, Nov [3] J. Llls, C. K. Cheng, and T. T. Y. Ln, \Optmal wre szng and buer nserton for low power and a generalzed delay model," n Proc. Int. Conf. on Computer Aded Desgn, pp. 138{143, Nov [4] N. Menezes, R. Baldck, and L. T. Plegg, \A sequental quadratc programmng approach to concurrent gate and wre szng," n Proc. Int. Conf. on Computer Aded Desgn, pp. 144{151, [5] C. P. Chen, Y. W. Chang, and D. F. Wong, \Fast performance-drven optmzaton for buered clock trees based on Lagrangan relaxaton," n Proc. Desgn Automaton Conf, pp. 405{408, [6] J. Cong and L. He, \An ecent approach to smultaneous transstor and nterconnect szng," n Proc. Int. Conf. on Computer-Aded Desgn, pp. 181{186, Nov [7] C. Chu and D. F. Wong, \A new approach to smultaneous buer nserton and wre szng," n Proc. Int. Conf. on Computer Aded Desgn, pp. 614{621, [8] Semconductor Industry Assocaton, Natonal Technology Roadmap for Semconductors, [9] K. Nabors and J. Whte, \Fastcap: A multpole accelerated 3-d capactance extracton program," n IEEE Trans. on Computer-Aded Desgn of Integrated Crcuts and Systems, pp. 1447{1459, Nov [10] J. Cong, L. He, C. Koh, and Z. Pan, \Global nterconnect szng and spacng wth consderaton of couplng capactance," Tech. Rep , UCLA CS Dept, [11] L. Vandenberghe, S. Boyd, and A. E. Gamal, \Optmal wre and transstor szng for crcuts wth non-tree topology," n Proc. Int. Conf. on Computer Aded Desgn, pp. 252{259, [12] J. Cong and L. He, \Theory and algorthm of local renement based optmzaton wth applcaton to transstor and nterconnect szng," Tech. Rep , UCLA CS Dept, Sept [13] J. Cong and L. He, \Optmal wreszng for nterconnects wth multple sources," n Proc. Int. Conf. on Computer Aded Desgn, pp. 568{574, Nov [14] C. Chen, P. Yang, E. Cohen, R. Jan, and H. Samuel, \A 12.7Mchp/s all-dgtal BPSK drect sequence spread-spectrum IF transcever n 1.2m CMOS," n Proc. IEEE Int. Sold-State Crcuts Conf., pp. 30{31, [15] J. Cong, L. He, A. B. Kahng, D. Noce, S. N., and S. H.-C. Yen, \Analyss and justcaton of a smple, practcal 2 1/2-d capactance extracton methodology," n Proc. Desgn Automaton Conf, pp. 627{632,