VLSI Circuit Performance Optimization by Geometric Programming

Transcription

1 Annals of Operatons Research 05, 37 60, Kluwer Academc Publshers. Manufactured n The Netherlands. VLSI Crcut Performance Optmzaton by Geometrc Programmng CHRIS CHU cnchu@astate.edu Department of Electrcal and Computer Engneerng, Iowa State Unversty, Ames, IA 500, USA D.F. WONG wong@cs.utexas.edu Department of Computer Scences, Unversty of Texas at Austn, Austn, TX 7872, USA Abstract. Delay of VLSI crcut components can be controlled by varyng ther szes. In other words, performance of VLSI crcuts can be optmzed by changng the szes of the crcut components. In ths paper, we defne a specal type of geometrc program called unary geometrc program. We show that under the Elmore delay model, several commonly used formulatons of the crcut component szng problem consderng delay, chp area and power dsspaton can be reduced to unary geometrc programs. We present a greedy algorthm to solve unary geometrc programs optmally and effcently. When appled to VLSI crcut component szng, we prove that the runtme of the greedy algorthm s lnear to the number of components n the crcut. In practce, we demonstrate that our unary-geometrc-program based approach for crcut szng s hundreds of tmes or more faster than other approaches. Keywords: VLSI desgn, unary geometrc programmng, crcut performance optmzaton, transstor szng, gate szng, wre szng, Lagrangan relaxaton. Introducton Snce the nventon of ntegrated crcuts almost 40 years ago, szng of crcut components (e.g., transstors and wre segments) has always been an effectve technque to acheve desrable crcut performance. The reason s both resstance and capactance of a crcut component are functons of the component sze. Snce the delay of a crcut component can be modeled as a product of the resstance of the component and the capactance of the subcrcut drven by the component, the delay of a crcut can be mnmzed by szng of crcut components. Both transstor/gate szng [6,2,5,6,2] and wre szng [2,4,7,9,8,20] have been shown to be effectve to reduce crcut delay. Transstor szng s the problem of changng the channel length of transstors. Gate szng s bascally the same as transstor szng. Gate s a collecton of transstors workng together to perform a specfc logc functon. Gate szng refers to the problem of szng the transstors nsde a gate smultaneously by the same factor. Wre szng refers to the problem of determnng the wdth of the wres at every pont along the wres. To make the desgn and fabrcaton process eas- Ths work was partally supported by the Texas Advanced Research Program under Grant No and by a grant from the Intel Corporaton.

2 38 CHU AND WONG er, wres are usually dvded nto fxed-length segments and every pont n a segment s szed to the same wdth. Snce transstor/gate szes affect wre-szng solutons and wre szes affect transstor/gate-szng solutons, t s benefcal to smultaneously sze both transstors/gates and wres [2,7,8,7,9]. However, the smultaneous problem s harder to solve. In ths paper, we consder performance optmzaton of VLSI crcuts by szng components. In order to smplfy the presentaton, we llustrate the dea by smultaneous gate and wre szng. All technques ntroduced n ths paper can be easly appled to smultaneous transstor and wre szng. The wdely used Elmore delay model [] s used here for delay calculaton. Varous formulatons of the szng problem consderng delay, chp area and power dsspaton have been proposed. When delay alone s consdered, two commonly used formulatons are mnmzng a weghted sum of the delay of components, and mnmzng the maxmum delay among all crcut outputs. Besdes delay, t s desrable to mnmze the chp area occuped by the crcut and the power dsspaton of the crcut as well. All these objectves can be optmzed effectvely by crcut component szng. However, these objectves are usually conflctng. As a result, to consder the tradeoff of these desgn objectves, formulatons lke mnmzng the maxmum delay among all crcut outputs subject to bounds on area/power, and mnmzng area/power subject to delay bounds on all crcut outputs have been proposed. Fshburn and Dunlop [2] have already ponted out that for the transstor szng problem, several formulatons can be wrtten as geometrc programs [0]. In fact, by generalzng the dea of [2], t s not dffcult to see that all formulatons lsted above can be wrtten as geometrc programs. However, t would be very slow to solve them by some general-purpose geometrc programmng solver. So nstead of solvng t exactly, many heurstcs were proposed [6,2,5,6]. Sapatnekar et al. [2] transformed the geometrc programs for transstor szng nto convex programs and solved them by a sophstcated general-purpose convex programmng solver based on nteror pont method. Ths s the best known prevous algorthm that can guarantee exact transstor szng solutons. However, to optmze a crcut of only 832 transstors, the reported runtme s already 9 hours on a Sun SPARCstaton. In ths paper, we defne a specal type of posynomal [0] and geometrc program: Defnton. A unary posynomal s a posynomal of the followng form: u(x,...,x n ) = n α + x n β x +,jn where α, β and γ j for all and j are non-negatve constants. γ j x x j, Defnton 2. A unary geometrc program s a geometrc program whch mnmzes a

3 VLSI CIRCUIT PERFORMANCE 39 unary posynomal subject to upper and lower bounds on all varables. In other words, t s a geometrc program of the followng form: Mnmze u(x,...,x n ) = α + β x + x γ j x x j n n,jn subject to L x U for all n, where α, β, γ j, L and U for all and j are non-negatve constants. As we show n secton 2, the formulaton of mnmzng weghted component delay s a unary geometrc program. For all other formulatons, Chen, Chu and Wong [3] showed that they can be reduced by the Lagrangan relaxaton technque to problems very smlar to weghted component delay problems. We observe that these problems are also unary geometrc programs. In other words, by solvng unary geometrc programs, all formulatons of crcut component szng above can be solved. To solve unary geometrc programs, we present a greedy algorthm whch s both optmal and effcent. In partcular, for unary geometrc programs correspondng to VLSI crcut component szng, we prove that the runtme of the greedy algorthm s lnear to the number of components n the crcut. The rest of ths paper s organzed as follows. In secton 2, we explan why dfferent formulatons of the crcut szng problem can be reduced to unary geometrc programs. In secton 3, we present the greedy algorthm to solve unary geometrc programs, prove ts optmalty and analyze ts convergence rate. In secton 4, we analyze the runtme of the greedy algorthm when appled to VLSI crcuts. In secton 5, expermental results to show the runtme and storage requrements of our approach to crcut szng are presented. 2. Reducton to unary geometrc programs In ths secton, we show that any formulaton of crcut component szng wth one of delay, area and power consttutng the objectve functon and wth constrants on the other two can be reduced to unary geometrc programs. For a general VLSI crcut, we can gnore all latches and optmze ts combnatonal subcrcuts. Therefore, we focus on combnatonal crcuts below. Fgure llustrates a combnatonal crcut. We call a gate or a wre segment a crcut component. Let n be the number of component n the crcut. The crcut component szng problem s to optmze some objectve functon subject to some constrants nvolvng delay, area and power. For n, letx be the gate sze f component s a gate, or the segment wdth f component s a wre segment. Let L and U be, respectvely, the lower bound and upper bound on the component sze x,.e., L x U. In secton 2., we frst ntroduce the model that we use for delay calculaton. In secton 2.2, we show that the formulaton of mnmzng a weghted sum of component delays can be wrtten drectly as a unary geometrc program. In secton 2.3, we show that all other formulatons can be reduced to unary geometrc programs.

4 40 CHU AND WONG Fgure. A combnatonal crcut. Fgure 2. The model of a gate by a swtch-level RC crcut. Note that r = r /x and c = ĉ x + f,where r, ĉ and f are the unt sze output resstance, the unt sze gate area capactance and the gate permeter capactance of the gate respectvely. Although the gate shown here s a 2-nput AND gate, the model can be easly generalzed for any gate wth any number of nput pns. 2.. Delay model For the purpose of delay calculaton, we model crcut components as RC crcuts. A gate s modeled as a swtch-level RC crcut as shown n fgure 2. See [22] for a reference of ths model. For ths model, the output resstance r = r /x, and the nput capactance of a pn c = ĉ x + f,where r, ĉ and f are the unt sze output resstance, the unt sze gate area capactance and the gate permeter capactance of gate respectvely. (To smplfy the notatons, we assume the nput capactances of all nput pns of a gate are the same. We also gnore the ntrnsc gate delay. It s clear that all our results wll stll hold wthout these assumptons.) A wre segment s modeled as a π-type RC crcut as shown n fgure 3. For ths model, the segment resstance r = r /x, and the segment capactance c = ĉ x + f, where r, ĉ and f are the unt wdth wre resstance, the unt wdth wre area capactance and the wre frngng capactance of segment respectvely. The classcal Elmore delay model [] s used for delay calculaton. The delay of each component s equal to the delay assocated wth ts resstor. The delay assocated wth a resstor s equal to ts resstance tmes ts downstream capactance,.e., the total capactance drven by the resstor. The delay along a sgnal path s the sum of the delays assocated wth the resstors n the path.

5 VLSI CIRCUIT PERFORMANCE 4 Fgure 3. The model of a wre segment by a π-type RC crcut. Note that r = r /x and c = ĉ x + f, where r, ĉ and f are the unt wdth wre resstance, the unt wdth wre area capactance and the wre frngng capactance of the segment respectvely Weghted component delay formulaton In ths subsecton, we show that the problem of mnmzng a weghted sum of the delays of components can be wrtten drectly as a unary geometrc program. Accordng to secton 2., the capactance of component s a lnear functon n x and the capactances of output loads are constants. So the downstream capactance of each component s a lnear functon n x,...,x n. For example, the downstream capactance of component 6 s (ĉ 6 x 6 + f 6 )/2 + (ĉ 9 x 9 + f 9 ) + C L. Snce the resstance of component s nversely proportonal to x and the resstance of drvers are constants, the delay assocated wth each component n the crcut can be wrtten as a unary posynomal n x,...,x n plus a constant. For example, Delay of component 6 = r ) 6 (ĉ6 x 6 + f 6 + (ĉ 9 x 9 + f 9 ) + C L x 6 2 = r 6(f 6 /2 + f 9 + C L) x 9 + r 6 ĉ 9 + r 6ĉ 6 x 6 x 6 2. It s clear that a weghted sum of the component delays s also a unary posynomal plus a constant. Together wth upper and lower bounds on component szes, the weghted component delay formulaton can be wrtten as a unary geometrc program Other formulatons Chen, Chu and Wong [3] showed that the Lagrangan relaxaton technque can be used to handle dfferent formulatons of crcut component szng. Lagrangan relaxaton s a general technque for solvng constraned optmzaton problems. In Lagrangan relaxaton, troublesome constrants are relaxed and ncorporated nto the objectve functon after multplyng them by constants called Lagrange multplers, one multpler for each constrant. For any fxed vector λ of the Lagrange multplers ntroduced, we have a new optmzaton problem (whch should be easer to solve because t s free of troublesome constrants) called the Lagrangan relaxaton subproblem. Chen, Chu and Wong [3] showed that there exsts a vector λ such that the optmal soluton of the Lagrangan relaxaton subproblem s also the optmal soluton of the orgnal crcut component szng problem. The problem of fndng such a vector λ s called the Lagrangan dual problem. The Lagrangan dual problem can be solved by the

6 42 CHU AND WONG classcal method of subgradent optmzaton []. Therefore, f the Lagrangan relaxaton subproblem can be solved optmally, the orgnal crcut szng problem can also be solved optmally. For all formulatons stated n secton, the correspondng Lagrangan relaxaton subproblems are ndeed very smlar to a weghted component delay problem. No matter whch of delay, area or power s n the objectve functon and whch are n the constrants, after ncorporatng the constrants nto the objectve functon, the resultng objectve functon s always a weghted sum of total component area, total power dsspaton, component delays and nput drver delays. The total component area, the total power dsspaton and the nput drver delays are all lnear functons n x,...,x n. It s obvous for the case of area. For power dsspaton, power s dsspated manly when chargng and dschargng capactances n the crcut. Power dsspaton s a lnear functon n the capactances of components. Snce the capactance of component s lnear to ts sze x, the total power dsspaton s a lnear functon n x,...,x n. For nput drver delays, note that the resstance of each nput drver s a constant and the total capactance drven by each nput drver s a lnear functon n x,...,x n. So the delay assocated wth each nput drver s a lnear functon n x,...,x n. As a result, for any formulaton consdered, the objectve functon of the Lagrangan relaxaton subproblem s a unary geometrc functon. Together wth the upper and lower bounds on component szes, the Lagrangan relaxaton subproblem s a unary geometrc program. 3. Greedy algorthm for solvng unary geometrc program In ths secton, we present a greedy algorthm whch can solve unary geometrc programs very effcently and optmally. In secton 3., we present the greedy algorthm. In secton 3.2, we prove that f we use (x,...,x n ) = (L,...,L n ) as the startng soluton, the algorthm always converges to the optmal soluton. In secton 3.3, we prove that f (α 0orβ 0) for all, then the greedy algorthm wll converge lnearly to the optmal soluton from any startng soluton. 3.. The greedy algorthm The basc dea of the greedy algorthm s to teratvely adjustng the varables. In each teraton, the varables are examned one by one. When x k s examned, t s adjusted optmally whle keepng the values of all other varables fxed. We call ths operaton an optmal local adjustment of x k. The followng lemma gves a formula for optmal local adjustment.

7 VLSI CIRCUIT PERFORMANCE 43 Lemma. For a soluton x = (x,x 2,...,x n ) of a unary geometrc program, the optmal local adjustment of x k s gven by { { n, k x k = mn U k, max L k, γ }} kx + α k jn, j k γ. kj /x j + β k Proof. u(x,...,x n ) = α + β x + x n = x k ( n, k n,jn γ k x + α k ) + x k ( + terms ndependent of x k. γ j x x j jn, j k ) γ kj + β k x j So by the Kuhn Tucker condtons [3], the optmal value of x k between L k and U k whch mnmze u(x,...,x n ) s { { n, k x k = mn U k, max L k, γ }} kx + α k jn, j k γ. kj /x j + β k The greedy algorthm s gven below. Greedy algorthm for unary geometrc program. S. Let (x,...,x n ) be some startng soluton. S2. for k := ton do { { n, k x k = mn U k, max L k, γ }} kx + α k jn, j k γ. kj /x j + β k S3. Repeat step S2 untl no mprovement Optmalty of the greedy algorthm In ths subsecton, we prove that f we use (x,...,x n ) = (L,...,L n ) as the startng soluton, the algorthm always converges to the optmal soluton. Let x = (x,...,x n ), A k (x) = γ k x, B k (x) = γ kj. x j n, k jn, j k Note that u(x) s a posynomal n x. It s well known that under a varable transformaton, a posynomal s equvalent to a convex functon. So u(x) has a unque global mnmum

8 44 CHU AND WONG and no other local mnmum. We show n the followng two lemmas that wth the startng soluton (x,...,x n ) = (L,...,L n ), the greedy algorthm always converges to the global mnmum. Lemma 2. If the greedy algorthm converges, then the soluton s optmal. Proof. Suppose the algorthm converges to x = (x,...,x n ). Then for k n, by lemma, { xk {U = mn k, max L k, A k (x ) + α k B k (x ) + β k }}. Note that u(x) s a posynomal n x, and that under the transformaton x k = e z k for k n, the functon h(z) = u(e z,...,e z n ) s convex over z ={z: L k e z k U k, k n}. Letz = (z,...,z n ) where x k = ez k for k n. We now consder 3 cases: Case : xk = (A k (x ) + α k )/(B k (x ) + β k ). In ths case, we have u x k (x ) = 0. Thus h (z ) = u (x ) x k (z ) = u (x )e z k = 0. z k x k z k x k Case 2: xk = L k. In ths case, L k (A k (x ) + α k )/(B k (x ) + β k ). We have u x k (x ) 0and z k zk 0, z z. Hence h (z )(z k zk z ) = u (x )e z k (zk zk k x ) 0, z z. k Case 3: xk = U k. In ths case, U k (A k (x ) + α k )/(B k (x ) + β k ). We have u x k (x ) 0and z k zk 0, z z. Hence h (z )(z k zk z ) = u (x )e z k (zk zk k x ) 0, z z. k So h z k (z )(z k zk ) 0forallk and for all z z. Thus for any feasble soluton x, u(x) u(x ) = h(z) h(z ) h(z )(z z ) as h s convex = n k= 0. h z k (z )(z k z k ) Therefore x s the global mnmum pont.

9 VLSI CIRCUIT PERFORMANCE 45 Lemma 3. If (x,...,x n ) = (L,...,L n ) s used as the startng soluton, the greedy algorthm always converges. Proof. For any two vectors x and y, weusex y to denote that x y for all. Consder any two feasble solutons x and y. Letx and y be the solutons after locally adjustng some varable x k of x and y, respectvely. If x y, thena k (x) A k (y) and B k (x) B k (y). So { }} x k {U = mn A k (x) + α k k, max L k, B k (x) + β k { { mn U k, max L k, A k (y) + α k B k (y) + β k }} = y k. Also, x j = x j y j = y j for j k. Hence x y mples x y. If we consder x and y be solutons before two consecutve optmal local adjustment operatons, then x = y. Therefore, x x = y y. Snce the startng soluton s (L,...,L n ), we can prove by mathematcal nducton that all varables are monotoncally ncreasng after each optmal local adjustment operaton. If we consder y to be the optmal soluton, then y = y. Hence x y mples x y. Snce the startng soluton s (L,...,L n ), we can prove by mathematcal nducton that every x after each optmal local adjustment operaton s upper bounded by the optmal value y. As x s monotoncally ncreasng and s upper bounded for all, the greedy algorthm always converges. By lemmas 2 and 3, we have the followng theorem. Theorem. For any unary geometrc program, f (x,...,x n ) = (L,...,L n ) s used as the startng soluton, the greedy algorthm always converges to the optmal soluton Convergence rate of the greedy algorthm In secton 2, we show that many formulatons of the crcut szng problem can be reduced to a sequence of unary geometrc programs by Lagrangan relaxaton. We prove n secton 3.2 the convergence of the greedy algorthm only for the specal startng soluton x = (L,...,L n ). So n order to guarantee convergence, before solvng each unary geometrc program nstance, all varables have to be reset to ther lower bounds to form the startng soluton for the greedy algorthm. However, snce two consecutve unary geometrc program nstances by Lagrangan relaxaton are almost the same (except that the Lagrange multplers are changed by a lttle bt), the optmal soluton of the frst unary geometrc program s close to the optmal soluton of the second one, and hence a good startng soluton to the second one. So f we can guarantee convergence to the optmal soluton, t s better not to reset the soluton before solvng each unary

10 46 CHU AND WONG geometrc program nstance. We observe that not resetng can speed up the greedy algorthm by more than 50% n practce. In addton, even for the specal startng soluton, the convergence rate of the greedy algorthm s not known. In ths subsecton, we consder unary geometry programs satsfyng the condton that α 0orβ 0forall. We pont out n secton 4 that for VLSI crcut component szng problems, ths condton s essentally always true. Under ths condton, we prove that the greedy algorthm always converges to the optmal soluton for any startng soluton. Moreover, we prove that the convergence rate for any startng soluton s always lnear wth convergence rato upper bounded by the parameter σ defned as follows: σ = max kn { φk + θ k 2 }, where φ k = / ( + ) α k A k (U,...,U n ) and θ k = / ( + ) β k. B k (L,...,L n ) Note that for all k, at least one of α k and β k s postve. So at least one of φ k and θ k s less than. Therefore, t s clear that σ s a constant such that 0 < σ <. Lemma 4 gves bounds on the changes of the varables after each teraton of the 2,...,x(0) n ) be the startng soluton, and for t, let x (t) = (x (t),x(t) 2,...,x(t) n ) be the soluton just after the tth teraton of the greedy algorthm. Let = max n {(U L )/L }. greedy algorthm. Let x (0) = (x (0),x(0) Lemma 4. For any t 0, x(t+) + σ t x (t) + σ t for all. The proof of lemma 4 s gven n the appendx. Theorem 2. If α 0orβ 0forall, then the greedy algorthm always converges to the optmal soluton for any startng soluton. Proof. Snce 0 <σ<, + σ t ast. So by lemma 4, t s obvous that the greedy algorthm always converges for any startng soluton. Lemma 2 proves that f the greedy converges, then the soluton s optmal. So the theorem follows. Let x = (x,x 2,...,x n ) be the optmal soluton. The followng lemma proves that the convergence rate of the greedy algorthm s lnear wth convergence rato upper bounded by σ.

11 VLSI CIRCUIT PERFORMANCE 47 Lemma 5. For any t 0, for all. x x (t) x ( + )σ t σ Proof. For any t 0andforany, Case : ( + )σ t /( σ). Then x (t) x Smlarly, we can prove U t ( + )σ + + L σ x (t) x Case 2: ( + )σ t /( σ) <. Then + ( + )σ t /( σ). x (t) x = k=t x (k) x (k+) So by lemma 4, /P x (t) /x P where P = k=t ( + σ k ). ln P = ln ( + σ k) = = = k=t k=t k=t ( σ k 2 2 σ 2k σ 3k ) 4 4 σ 4k + ( ) j j σ jk j= j= j= = ln j j j j j j j= ( ) σ j k k=t σ jt σ j. σ jt ( σ) j (2) σ t /( σ), (3). ()

12 48 CHU AND WONG where () s because ln( + x) = x 2 x2 + 3 x3 4 x4 +, (2) s because 0 <σ<, whch mples 0 <( σ) j < σ < σ j for j, and (3) s because 0 < σ t /( σ) <( + )σ t /( σ) < andln x = x + 2 x2 + 3 x3 + f 0 <x<. So P σ t /( σ) = + σ t /( σ t ) σ σ + σ t /( ) σ + t ( + )σ = +. σ Hence Therefore for both cases, + ( + )σ t /( σ) + ( + )σ t /( σ) It s easy to see that t ( + )σ σ So for any t 0 and for all, x x (t) x x(t) x x(t) x t ( + )σ +. σ t ( + )σ +. σ + ( + )σ t /( σ). t ( + )σ. σ 4. Analyss of the greedy algorthm when appled to VLSI crcuts In ths secton, we analyze the runtme of the greedy algorthm when appled to VLSI crcuts. In secton 4., we show that for VLSI crcuts, each teraton of the greedy algorthm only takes tme lnear to the number of crcut components. In secton 4.2, we show that for VLSI crcuts, the condton α 0orβ 0forall n secton 3.3 s always true. So we conclude that for any crcut component szng formulaton, the Lagrangan relaxaton subproblem can be solved optmally by the greedy algorthm n tme lnear to the sze of the crcut. Notce that Chu and Wong [5] also showed that the runtme of a smlar greedy algorthm for wrng szng of a sngle nterconnect tree s lnear.

13 VLSI CIRCUIT PERFORMANCE Lnear tme for each teraton We frst show that when appled to VLSI crcuts, each teraton of the greedy algorthm only takes lnear tme. For each optmal local adjustment operaton of x k, we need to calculated A k (x) = n, k γ k x and B k (x) = jn, j k γ kj x j. Hence each optmal local adjustment operaton takes O(n) tme and each teraton takes O(n 2 ) tme n general. However, for VLSI crcuts, A k (x) s and B k (x) s can be computed ncrementally. The reason s for any component k, A k (x) s a weghted downstream capactance and B k (x) s a weghted upstream resstance of the component. So A k (x) can be computed easly by fndng a weghted sum of A j (x) over all component j at the output of component k. Smlarly, B k (x) can be computed easly by fndng a weghted sum of B j (x) over all component j at the nput of component k. Note that the number of nputs and number of outputs for VLSI crcuts are always bounded by a smaller constant n practce. If we perform the optmal local adjustment operatons n a topologcal order, for each k, both A k (x) and B k (x) can be computed n constant tme. Therefore, the optmal local adjustment of x k can be done n constant tme. As a result, each teraton of the greedy algorthm only takes lnear tme Convergence rato of the greedy algorthm In secton 3.3, we prove that the greedy algorthm converges lnearly wth convergence rato σ to the optmal soluton from any startng soluton. The convergence rato σ s upper bounded by the maxmum of (φ k +θ k )/2 among all k. So f both φ k = andθ k = for some k, then the proof cannot guarantee the convergence of the greedy algorthm. Ths stuaton occurs when α k = 0andβ k = 0forsomek. On the other hand, f α k 0 or β k 0forallk, thenσ s less than. The convergence of the greedy algorthm s guaranteed. Moreover, the larger the values of α k s and β k s, the faster the convergence of the greedy algorthm. For all k, α k and β k are, respectvely, the coeffcents of the terms /x k and x k n the objectve functon of the unary geometrc program. For VLSI crcut component szng, α k s and β k s are essentally always non-zero. Factors causng α k s and β k s to be greater than zero are lsted below. Wre frngng capactance and gate permeter capactance. The Elmore delay for a component s equal to ts resstance tmes ts downstream capactance. Notce that wre frngng capactance and gate permeter capactance are ndependent of the component szes, whereas the resstance of any component s nversely proportonal to ts sze. So the wre frngng capactance of all wre segments and the gate permeter capactance of all gates/loads at the downstream of component k contrbute to the value of α k.

14 50 CHU AND WONG Drver resstance and load capactance. The Elmore delay for a drver equals to the drver resstance tmes the total capactance of wre segments and gates drven by t. Snce the drver resstance s ndependent of x,...,x n, and the total capactance of wre segments and gates drven s a lnear functon of x,...,x n, the drver resstance contrbutes to the value of β k for all component k drven by the drver. Smlarly, f any component k s n the upstream of a load wth capactance C L, then the term C L r k /x k wll occur n the Elmore delay expresson. Therefore, the load capactance contrbutes to the value of α k. Component area. For any VLSI crcut szng formulaton nvolvng the total component area, β k 0forallk. Let the total component area be n = ω x for some postve constants ω,...,ω n. If the total component area s the objectve to mnmze, then the objectve functon of the unary geometrc program wll contan the term n = ω x.if the total component area s constraned, then after Lagrangan relaxaton, the objectve functon of the unary geometrc program wll contan the term λ( n = ω x ) where λ s the Lagrange multpler. In both cases, β k 0forallk. Power dsspaton. As stated n secton 2.3, the power dsspaton of a crcut s a lnear functon n = ω x for some postve constants ω,...,ω n. So f power dsspaton s consdered ether n the objectve or as a constrant, β k 0forallk. In fact, the number of teratons of the greedy algorthm s a functon of the convergence rato σ.thevalueofσ depends on a lot of factors lke the electrcal parameters of the fabrcaton technology, the resstance of drvers and the capactance of loads, and the upper and lower bounds on the component szes. However, we observe that the actual convergence rato s not very senstve to those factors, and s usually much less than 0. n practce. In addton, the change n σ does not affect the number of teratons very much. For example, f σ changes from 0.05 to an unrealstcally large value 0.5, the number of teratons s ncreased only by a factor of log 0.05/ log 0.5 = 4.3. Snce the convergence rate of the greedy algorthm s lnear and the runtme of each teraton s O(n), we have the followng theorem. Theorem 3. When appled to VLSI crcut component szng, the total runtme of the greedy algorthm for any startng soluton s O(n log(/ε)), whereε specfes the precson of the fnal soluton (.e., for the optmal soluton x, the fnal soluton x satsfes (x x )/x ε for all ). Proof. By lemma 5, for any t 0 and for all, x x (t) x t ( + )σ. σ

15 VLSI CIRCUIT PERFORMANCE 5 In order to guarantee that (x x (t) )/x ε for all, the number of teratons t must satsfy ( + )σ t ε, σ or equvalently, ( + ) t log /σ ( σ)ε. In other words, at most ( + ) log /σ ( σ)ε teratons are enough. Snce each teraton of the greedy algorthm takes O(n) tme, the total runtme s O(n log(/ε)). Therefore, to obtan a soluton wth any fxed precson, only a constant number of teratons of the greedy algorthm are needed. Ths mples that for Lagrangan relaxaton subproblems of VLSI crcut component szng, the runtme of the greedy algorthm s O(n). 5. Expermental results In ths secton, the runtme and storage requrements of our unary-geometrc-program based approach to crcut component szng are presented. We mplemented a crcut component szng program for mnmzng area subject to maxmum delay bound on a PC wth a 333 MHz Pentum II processor. In the program, the Lagrangan relaxaton technque s used to reduce the problem to unary geometrc programs, whch are then solved optmally by our greedy algorthm. The Lagrangan dual problem s solved by the classcal subgradent optmzaton method. We test our crcut component szng program on adders [4] of dfferent szes rangng from 8 bts to 024 bts. Number of gates range from 20 to Number of wres range from 96 to 2288 (note that the number of wres here means the number of szable wre segments). The total number of szable components range from 26 to The lower bound and upper bound of the sze of each gate are and 00, respectvely. The lower bound and upper bound of the wdth of each wre are and 3 µm, respectvely. The stoppng crtera of our program s the soluton s wthn % of the optmal soluton. In table, the runtme and storage requrements of our program are shown. Even for a crcut wth szable components, the runtme and storage requrements of our program are.53 mnutes and about 23 MB only. As mentoned n secton, the nteror-pont-method based approach n [2] s the best prevous algorthm that can guarantee exact crcut szng solutons. The largest test crcut n [2] has 832 transstors and the reported runtme and memory are 9 hours (on a Sun SPARCstaton ) and

16 52 CHU AND WONG Table The runtme and storage requrements of our crcut component szng program on test crcuts of dfferent szes. Crcut name Crcut sze Runtme Memory # Gates # Wres Total (mnutes) (MB) adder (8 bts) adder (6 bts) adder (32 bts) adder (64 bts) adder (28 bts) adder (256 bts) adder (52 bts) adder (024 bts) MB, respectvely. Note that for a problem of smlar sze (864), our approach only needs.3 seconds of runtme (on a PC wth a 333 MHz Pentum II processor) and.5 MB of memory. Accordng to the SPEC benchmark results [23], our machne s roughly 40 tmes faster than the slowest model of Sun SPARCstaton. Takng the speed dfference of the machnes nto account, our program s about 600 tmes faster than the nteror-pont-method based approach for a small crcut. For larger crcuts, we expect the speedup to be even more sgnfcant. Fgures 4 and 5 plot the runtme and storage requrements of our program. By performng a lnear regresson on the logarthm of the data n fgure 4, we fnd that the emprcal runtme of our program s about O(n.7 ). Fgure 5 shows that the rato of the storage versus the crcut sze of our program s close to lnear. The storage requrement for each szable component s about 0.8 KB. The basc dea of the subgradent optmzaton method s to repeatedly modfy the vector of Lagrange multplers accordng to the subgradent drecton and then solve the correspondng Lagrangan relaxaton subproblem untl the soluton converges. Fgure 6 shows the convergence sequence of the subgradent optmzaton method for the Lagrangan dual problem on a 28-bt adder. It shows that our program converges smoothly to the optmal soluton. The sold lne represents the upper bound of the optmal soluton and the dotted lne represents the lower bound of t. The lower bound values come from the optmal value of the unary geometrc program at current teraton. Note that the optmal soluton s always nbetween the upper bound and the lower bound. So these curves provde useful nformaton about the dstance between the optmal soluton and the current soluton, and help users to decde when to stop the programs. Fgure 7 shows the area versus delay tradeoff curve of a 6-bt adder. In our experment, we observe that to generate a new pont n the area and delay tradeoff curve, the subgradent optmzaton method converges n only about 5 teratons. It s because the vector of Lagrange multplers of the prevous pont s a good approxmaton for that of the new pont and hence the convergence of the subgradent optmzaton method s fast. As a result, generatng these tradeoff curves requres only a lttle bt more runtme but provdes precous nformaton.

17 VLSI CIRCUIT PERFORMANCE 53 Fgure 4. The runtme requrement of our program versus crcut sze. Fgure 5. The storage requrement of our program versus crcut sze. Fgure 6. The convergence sequence for a 28-bt adder.

18 54 CHU AND WONG 6. Concluson Fgure 7. The area versus delay tradeoff curve for a 6-bt adder. We have ntroduced a specal type of geometrc program called unary geometrc program, whch s of the followng form: Mnmze u(x,...,x n ) = α + β x + x γ j x x j n n subject to L x U for all n,,jn where α, β, γ j, L and U for all and j are non-negatve constants. We have shown that unary geometrc programs are very useful n VLSI crcut component szng. Many formulatons nvolvng delay, area and power can be reduced by the Lagrangan relaxaton technque to unary geometrc programs. We have presented a greedy algorthm to solve unary geometrc programs optmally and very effcently. We have proved that the algorthm converges to the optmal soluton f x s set to L for all n the startng soluton. We have also proved that when appled to VLSI crcut component szng, the algorthm always converges to the optmal soluton from any startng soluton n tme lnear to the number of gates or wre segments n the crcut. Appendx: Proof of lemma 4 In order to prove lemma 4, we need to prove lemmas 6, 7, and 8 frst. For lemmas 6 and 7, we focus on varable x k for some fxed k. Note that durng the n optmal local adjustment operatons just before the local adjustment of x k at a partcular teraton (except the frst teraton), each varable s adjusted exactly once.

19 VLSI CIRCUIT PERFORMANCE 55 Intutvely, the followng two lemmas show that durng these n adjustment operatons, f the changes n all varables are small, then the change n x k durng the local adjustment of x k at that teraton wll be even smaller. For some t, let x = (x,...,x n ), x = (x,...,x n ) and x = (x,...,x n ) be, respectvely, the solutons just before the local adjustment of x k at teraton t, t + and t + 2 of the greedy algorthm. Let q k = A k (x) + α k and q k B k (x) + β = A k (x ) + α k. k B k (x ) + β k So by lemma, x k = mn{u k, max{l k,q k }} and x k = mn{u k, max{l k,q k }}. Lemma 6. For any ρ>0, f then + ρ x x + ρ for all, + ρσ q k q k + ρσ. Proof. If x /( + ρ) x ( + ρ)x for all, wehave + ρ A k(x) A k (x ) ( + ρ)a k (x) and + ρ B k(x) B k (x ) ( + ρ)b k (x). Snce γ k 0andx U for all and k, wehave A k (x) = γ k x γ k U = A k (U,...,U n ). n, k n, k So by the defnton of φ k, φ k / ( + α k /A k (x)), or equvalently, Hence A k (x) φ k ( Ak (x) + α k ). A k (x ) + α k ( + ρ)a k (x) + α k = ρa k (x) + ( ) A k (x) + α k ( ) ( ) ρφ k Ak (x) + α k + Ak (x) + α k = ( + ρφ k ) ( ) A k (x) + α k (4)

20 56 CHU AND WONG and A k (x ) + α k + ρ A k(x) + α k = A k (x) + α k ρ + ρ A k(x) A k (x) + α k ρφ k ( ) Ak (x) + α k + ρ ( = ρφ ) k (Ak ) (x) + α k + ρ ( ) > Ak (x) + α k + ρφ k as ρ>0and0<φ k <. (5) Smlarly, snce γ kj 0andx j L j for all j and k, wehave B k (x) = jn, j k γ kj x j jn, j k γ kj L j = B k (L,...,L n ). So by the defnton of θ k, θ k /( + β k /B k (x)), or equvalently, B k (x) θ k ( Bk (x) + β k ). Hence we can prove smlarly that B k (x ) + β k ( + ρθ k ) ( ) B k (x) + β k and By defntons of q k q k = B k (x ) + β k > and q k, and by (4) and (7), we have A k (x ) + α k B k (x ) + β k (6) + ρθ k ( Bk (x) + β k ). (7) ( + ρφ k )( + ρθ k ) A k(x) + α k B k (x) + β k ( + ρ φ ) k + θ k q k (as geometrc mean arthmetc mean) 2 ( + ρσ)q k. Smlarly, by (5) and (6), we can prove that q k + ρ(φ k + θ k )/2 q k + ρσ q k.

21 VLSI CIRCUIT PERFORMANCE 57 Asaresult,/( + ρσ) q k /q k + ρσ. Lemma 7. For any ρ>0, f + ρ x + ρ for all, x then + ρσ x k x k + ρσ. Proof. By lemma 6, f x /( + ρ) x ( + ρ)x for all,thenq k /( + ρσ) q k ( + ρσ)q k. By lemma, x k = mn{u k, max{l k,q k }} and x k = mn{u k, max{l k,q k }}. In order to prove x k /( + ρσ) x k, we consder three cases: Case : q k <L k. Then x k = L k.so + ρσ x k = + ρσ L k <L k x k. Case 2: q k >U k. Then x k = U k.so + ρσ x k + ρσ U k <U k = x k. Case 3: q k L k and q k U k. Then q k L k x k q k and q k U k q k x k.so + ρσ x k + ρσ q k q k x k. In order to prove x k ( + ρσ)x k, we consder another three cases: Case : q k >U k. Then x k = U k.sox k U k <( + ρσ)u k = ( + ρσ)x k. Case 2: q k <L k. Then x k = L k.sox Case 3: q k U k and q k = L k <( + ρσ)l k ( + ρσ)x k. k L k. Then q k U k q k x k and q k L k x k q k.so x k Asaresult,/( + ρσ) x k /x k + ρσ. q k ( + ρσ)q k ( + ρσ)x k. Lemma 8 gves bounds on the changes of the varables after each teraton of the greedy algorthm. Be remnded that x (t) = (x (t),x(t) 2,...,x(t) n ) s the soluton just after the tth teraton of the greedy algorthm.

22 58 CHU AND WONG Lemma 8. For any t 0andρ>0, f then + ρ + ρσ x(t+) x (t) x(t+2) x (t+) + ρ for all, + ρσ for all. Proof. The lemma can be proved by nducton on. Base case: Consder the varable x. Before the local adjustment of x, the solutons at teraton t + andt + 2are(x (t),x(t) 2,...,x(t) n ) and (x(t+),x (t+) 2,...,x n (t+) ), respectvely. Snce /( + ρ) x (t+) /x (t) + ρ for all, by lemma 7, we have /( + ρσ) x (t+2) /x (t+) + ρσ. Inducton step: Assume that the nducton hypothess s true for =,...,k. Before the local adjustment of x k, the solutons at teraton t + andt + 2are(x (t+)...,x (t+) k,x(t) k,...,x (t+) ), respectvely. By nducton hypothess, Hence,...,x(t) n + ρσ + ρ ) and (x(t+2) as σ<. Also, t s gven that,...,x (t+2) k,x(t+) k x(t+2) x (t+) x(t+2) x (t+) + ρσ for =,...,k. + ρ for =,...,k,, n So by lemma 7, + ρ x(t+) x (t) + ρ for = k,...,n. Hence the lemma s proved. + ρσ x(t+2) k x (t+) k + ρσ. Proof of lemma 4. Ths can be proved by nducton on t. Base case: Consder t = 0. Note that for any soluton x = (x,...,x n ), L x U for all. Forall, x () x (0) U L + U L L +.

23 VLSI CIRCUIT PERFORMANCE 59 Smlarly, we can prove that for all, x () /x (0) /( + ). Inducton step: Assume that the nducton hypothess s true for t. Therefore, By lemma 8, x(t+) + σ t x (t) + σ t for all. x(t+2) + σ t+ x (t+) Hence the lemma s proved. + σ t+ for all. References [] M.S. Bazaraa, H.D. Sheral and C.M. Shetty, Nonlnear Programmng: Theory and Algorthms, 2nd ed. (Wley, 993). [2] C.-P. Chen, Y.-W. Chang and D.F. Wong, Fast performance-drven optmzaton for buffered clock trees based on Lagrangan relaxaton, n: Proc. ACM/IEEE Desgn Automaton Conf. (996) pp [3] C.-P. Chen, C.C.N. Chu and D.F. Wong, Fast and exact smultaneous gate and wre szng by Lagrangan relaxaton, IEEE Trans. Computer-Aded Desgn 8(7) (999) [4] C.-P. Chen, H. Zhou and D.F. Wong, Optmal non-unform wre-szng under the Elmore delay model, n: Proc. IEEE Intl. Conf. on Computer-Aded Desgn (996) pp [5] C.C.N. Chu and D.F. Wong, Greedy wre-szng s lnear tme, IEEE Trans. Computer-Aded Desgn 8(4) (999) [6] M.A. Crt, Transstor szng n CMOS crcuts, n: Proc. ACM/IEEE Desgn Automaton Conf. (987) pp [7] J. Cong and L. He, An effcent approach to smultaneous transstor and nterconnect szng, n: Proc. IEEE Intl. Conf. on Computer-Aded Desgn (996) pp [8] J. Cong and C.-K. Koh, Smultaneous drver and wre szng for performance and power optmzaton, n: Proc. IEEE Intl. Conf. on Computer-Aded Desgn (994) pp [9] J. Cong and K.-S. Leung, Optmal wreszng under the dstrbuted Elmore delay model, IEEE Trans. Computer-Aded Desgn 4(3) (995) [0] R.J. Duffn, E.L. Peterson and C. Zener, Geometrc Programmng Theory and Applcaton (Wley, NY, 967). [] W.C. Elmore, The transent response of damped lnear network wth partcular regard to wdeband amplfers, J. Appled Physcs 9 (948) [2] J.P. Fshburn and A.E. Dunlop, TILOS: A posynomnal programmng approach to transstor szng, n: Proc. IEEE Intl. Conf. on Computer-Aded Desgn (985) pp [3] D.G. Luenberger, Lnear and Nonlnear Programmng, 2nd ed. (Addson-Wesley, 984). [4] M.M. Mano, Dgtal Logc and Computer Desgn (Prentce-Hall, 979). [5] D.P. Marple, Performance optmzaton of dgtal VLSI crcuts, Techncal Report CSL-TR , Stanford Unversty (October 986). [6] D.P. Marple, Transstor sze optmzaton n the Talor layout system, n: Proc. ACM/IEEE Desgn Automaton Conf. (989) pp [7] N. Menezes, R. Baldck and L.T. Plegg, A sequental quadratc programmng approach to concurrent gate and wre szng, n: Proc. IEEE Intl. Conf. on Computer-Aded Desgn (995) pp

24 60 CHU AND WONG [8] N. Menezes, S. Pullela, F. Dartu and L.T. Plegg, RC nterconnect syntheses-a moment fttng approach, n: Proc. IEEE Intl. Conf. on Computer-Aded Desgn (994) pp [9] N. Menezes, S. Pullela and L.T. Plegg, Smultaneous gate and nterconnect szng for crcut level delay optmzaton, n: Proc. ACM/IEEE Desgn Automaton Conf. (995) pp [20] S.S. Sapatnekar, RC nterconnect optmzaton under the Elmore delay model, n: Proc. ACM/IEEE Desgn Automaton Conf. (994) pp [2] S.S. Sapatnekar, V.B. Rao, P.M. Vadya and S.M. Kang, An exact soluton to the transstor szng problem for CMOS crcuts usng convex optmzaton, IEEE Trans. Computer-Aded Desgn 2() (993) [22] J. Shyu, J.P. Fshburn, A.E. Dunlop and A.L. Sangovann-Vncentell, Optmzaton-based transstor szng, IEEE J. Sold-State Crcuts 23 (988) [23] SPEC table, ftp://ftp.cdf.toronto.edu/pub/spectable.