Representative Critical-Path Selection for Aging-Induced Delay Monitoring

Transcription

1 Representative Critical-Path Selection for Aging-Induced Delay Monitoring Farshad Firouzi, Fangming Ye, Krishnendu Chakrabarty, and Mehdi B. Tahoori Karlsruhe Institute of Technology, Germany Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA Abstract Transistor aging degrades path delay over time and may eventually induce circuit failure due to timing variations. Therefore, in-field tracking of path delays is essential and to respond to this need, several delay sensor designs have been proposed in the literature. However, due to the significant overhead of these designs and the large number of critical paths in today s IC, it is infeasible to monitor the delay of every critical path in silicon. We present an aging-aware representative path-selection method that allows us to measure the delay of a small set of paths and infer the delay of a larger pool of paths that are likely to fail due to transistor aging. Moreover, since aging is affected by process variations and runtime variations in temperature and voltage, we use machine learning and linear algebra to incorporate these variations during representative path selection. Simulation results for benchmark circuits highlight the accuracy of the proposed approach for predicting critical path delay based on the selected representative paths. I. INTRODUCTION As CMOS feature sizes scale further in the nano-meter regime, reliability is emerging as a major design criterion. Transistor aging, which is affected by workload-dependent voltage and temperature variations, as well as process variations, is recognized today as a key reliability bottleneck [1], []. Aging introduces significant delay in a circuit over time. Eventually, a circuit might exhibit failure if the delay in the critical paths exceeds the timing constraints for which it was designed. One of the main cause of transistor aging is Bias Temperature Instability (BTI), which gradually increases the threshold voltage of the transistor, and thereby circuit delay, over time. The BTI-induced delay degradation rate of the transistor depends on several factors, which can be classified into two categories: 1) effects of process variations on device parameters, e.g., threshold voltage and the effective gate length at manufacturing time, ) workload and operating conditions that affect the temperature and voltage droop profile for the chip. Temperature and voltage vary both spatially and temporally. Therefore, to accurately predict aging-induced path delays, the effect of all these phenomena on circuit timing must be considered [3], [4]. The traditional method used to mitigate gradual delay shifts due to transistor aging is to add timing margins to the circuit at design-time. However, the use of static and conservative timing margins, and neglecting silicon data and runtime variations lead to considerable performance loss. To avoid the overhead of design-time solutions, several online techniques have been proposed to respond to time-varying, aging-induced characteristics of the circuit [5], [6]. Online path delay monitoring can respond to dynamical aging-induced delay changes. Periodic delay testing at different operating frequencies has been proposed in recent years to estimate path delays in the presence of transistor aging, and to predict the system runtime failure [7], [8]. Since this approach interrupts the normal execution of the system in order to apply test vectors, it can result in substantial performance penalty. Moreover, it needs on-board memory to store test patterns. The use of aging sensors is another method for monitoring the aging-induced delay in a circuit [9], [1], [11], [1], [13]. However, monitoring techniques require that a large number of sensors be inserted in the circuit to precisely track path delays. Replica circuits (paths) are deployed to estimate the circuit delays in the presence of transistor aging [14], [15], [16]. In this approach, a small set of critical paths is synthesized as a stand-alone circuit to represent the aging-induced delay in the circuit. However, replica paths only cover a small portion of the large pool of critical paths inside the circuit. To identify appropriate replica paths, the approach proposed in [17] selects a small set of critical paths, referred to as representative critical reliability paths, to capture and track the aging-induced delay of the circuit. The key idea behind this approach is to exploit the topological similarity among critical paths to find a minimum set of paths whose delays have high correlation with the circuit delay. However, since this approach does not take runtime and process variations into account, it might lead to an incorrect selection of representative critical reliability paths. Moreover, this approach only estimates the aging-induced delay of the entire circuit and does not localize the source (gates/paths) of aging. Note that the localization information can be used by fine-grained aging mitigation techniques such as Input Vector Control (IVC) [18], to focus on targeted gates/paths rather than treating the circuit (all critical paths) uniformly. In this paper, we propose a new method that utilizes linear algebra and machine learning to dynamically select a small subset of critical paths to be monitored in order to accurately predict the delay of a large pool of critical paths inside the circuit. The proposed method can be regarded as being complementary to prior work on failure prediction [7], [13] in that we provide a selection method to identify the most relevant critical paths to be targeted. Our technique also extends postsilicon path selection techniques [19], [], [1] in that our objective is to predict delay increase of each individual critical path during time rather than identifying speed-paths or delay of critical paths at zero time. In addition, we consider the effects Paper 13. INTERNATIONAL TEST CONFERENCE /13/$31. c 13 IEEE

2 of the workload-dependent temperature and voltage variations, as well as process variations on aging-induced delay increase, during the path-selection process. Neglecting these factors results in incuring significant errors in aging-induced delay estimates and the resulting path-selection results are adversely affected. The delay of the selected paths can be measured by reusing the already available on-chip sensors [], [3], or by using delay-testing techniques [7], [8]. The aging-induced delay shift of the other critical paths is calculated based on the measured delay of the selected representative paths. Simulation results for various benchmark circuits highlight the accuracy of the proposed approach for predicting critical path delay based on the selected representative paths. The rest of the paper is organized as follows. Section II presents the problem statement and an overview of the proposed method. Section III discusses path characteristics and how we use them in our method. Section IV and Section V describe the proposed learning algorithms used to generate a set of representative critical paths. Experimental results for benchmark are shown in Section VI. Finally, Section VII concludes the paper. II. PROBLEM STATEMENT AND OVERVIEW OF PROPOSED METHOD One approach to monitor circuit delay is to target a large pool of target (long) paths that are more likely to have timing failures; such paths are referred to as Critical Paths (CPs). However, monitoring such a large number of CPs is not feasible due to the cost associated with the placement of too many sensors. A solution to this problem lies in the selection of only a small set of Representative Critical Paths (RCPs) from the large pool of target paths. The delays of the RCPs are accurately measured either by on-chip sensors or via delay testing, and the measured values are mapped to the delays of the other critical paths by exploiting the similarities in timing characteristics between CPs and RCPs. In other words, a small set of RCPs is used to predict delays of a large pool of CPs. Our goal is to select an optimal number of paths as RCPs to ensure that the prediction error is minimized. Fig. 1 illustrates the proposed method of RCP selection. The proposed flow consists of two different phases: 1) Variation Aware Timing Analysis (VATA) ) Path Selection and Verification. We utilize a logic simulator, the circuit netlist, and a set of representative input vector (which can be obtained by systemlevel profiling) to obtain signal probabilities and activity factors for all the internal nodes in the circuit. A key contribution of the proposed method is that it incorporates workloaddependent variations in temperature and voltage droop as well as process variations into the BTI-aware RCP-selection algorithm. Since BTI varies exponentially with process variations as well as with temperature and the operating voltage [3], neglecting one or some of these factors results in a significant error in the estimated BTI-induced delay degradation. To account for these factors during our analysis, a profiling process is conducted to obtain the temperature and voltage of each individual gate within the circuit. Next, the extracted profiles are projected into the gate-level BTI models to accurately estimate the path delays of the circuit. Since determining path delays by aging-aware SPICE simulation is computationally infeasible for large circuits, we characterize all the standard cells under various operating conditions (e.g., temperature, voltage, capacitance, input slope, voltage threshold) through accurate HSPICE simulations. This information is stored in a set of look-up tables (LUTs) and subsequently used by a gate-level static timing analysis (STA) tool to estimate the circuit delay. This approach enables us to achieve an accuracy comparable to transistor-level SPICE timing simulation, but the runtime is linear in the number of gates. In the RCP selection phase, all possible CPs within the circuit are enumerated using the above timing analysis flow. Next, we use the proposed method to select the RCPs. Finally, to verify the accuracy and efficiency of the proposed RCP selection method, we compare the actual measured path delays (extracted by the aging and variation-aware timing analysis framework) with the predicted delay values. Note that our proposed approach is a design-time technique. In other words, RCPs are selected during the design phase. However, due to process variation, some non-critical paths might become critical after fabrication. To cope with this problem, the initial set of CPs should be designed to consist of a substantial number of critical and near-critical paths. This approach ensures that the initial set of CPs not only consists of those CPs that are critical at normal operation, but also considers additional paths might become critical under different operation conditions. As shown in Section VI, even for a large set of CPs, our approach can find a small set of RCPs. III. FEATURE GENERATION AND PATH ENCODING To correlate the aging-induced delay of CPs with various design and run-time characteristics that impact BTI-induced delay degradation, we propose to use a machine-learning approach. The identification of these correlations between paths and the sources of timing variation allows us to build a model to monitor the delay of CPs over the lifetime of the system. To effectively explore the aging-aware uncertainty space, a set of features is utilized to encode the delay of a given path into a feature vector. Each of these features is a source of uncertainty that affects the aging-induced delay of a path. Suppose each CP p i can be encoded by a vector p i =[x i1,x i...x im ] with M chip features, which include information regarding 1) netlist and layout (e.g., logic gates in the path), ) process variation, 3) BTI, 4) temperature, and 5) voltage droop. A. Topological features These features model netlist and layout characteristics that are related to the gate types and location of the gates. As an example, these features can include information such as which gates are located in each critical path and the coordinate of each gate in the corresponding layout of the circuit. Paper 13. INTERNATIONAL TEST CONFERENCE

3 SPICE Gate Netlist Representative Workload Circuit HDL Description Path Feature Encoding SPICE Cell Characterization Aging-Aware Timing LUTs System-logic Profiling Transistor-Level BTI Estimation Temperature Profiling Synthesis (Gate-level Netlist) Place&Route Process Variation Model Path Selection Procedure Candidate Representative Paths (RPs) Predicting Paths Delays Using Representative Paths Transistor-Level Aging & Variations Aware Timing Model Voltage Drop Analysis Pre-Processing Timing Accuracy is met? No Timing Analysis Module1: Aging and Variations Aware Timing Analysis Aging-Variation aware Critical Paths & feature Fig. 1: Overall flow of the proposed path selection methodology. Yes Display Module: RP Selection B. Process-variation features Due to process variation, the Physical Parameters (PPs) of fabricated devices and interconnects are different from their nominal values. These uncertainties affect circuit delay, temperature-voltage profiles, as well as the BTI-induced delay degradation [4], [5]. To model the variation of PPs, the following pair of equations is used [6]: ΔPP total =ΔPP dd +ΔPP wd, ΔPP wd =ΔPP cor +ΔPP rand, (1) where ΔPP dd represents die-to-die variation, ΔPP wd is within-die (intra-die) variation, ΔPP cor represents the spatially-correlated variation, and ΔPP rand denotes the independent random variations. To model spatial correlations, the layout of the chip is partitioned into several rectangular grids where the number of grids depends on the die area. The correlation between two grids, follows a diminishing function of e bd, where d is the distance between the grids and b is a constant. In our experiments, process variation is modeled as 3σ/μ =. [5]. Finally, a CP is encoded in a way that the corresponding vector reflects the grids to which the path is sensitive. C. BTI feature BTI can be understood in terms of two different phenomena: 1) Stress: Two physical mechanisms have been identified as being contributors to the BTI-induced threshold voltage increase: 1) Reaction-Diffusion ) Trapping- Detrapping. In the first mechanism, traps are generated at the interface of the Si/dielectric through a process consisting of an electrochemical reaction together with the diffusion of H + into the poly-gate. In the second mechanism, some of the holes are trapped due to tunneling in the pre-existing defects within the oxide. Both mechanisms cause the threshold voltage of the transistors to increase over time. ) Recovery: This phenomena occurs when V gs =1for PMOS and V gs =for PMOS transistor. In this phase, some of the generated/activated traps are removed from the interface and oxide. Therefore, the threshold voltage decreases towards its initial value. It should be noted that the recovery mode cannot completely compensate for the effect of the stress mode and hence the overall effect of BTI is a positive shift in the threshold voltage of the transistor. To model the overall BTI-induced threshold voltage shift, we use the widely adopted model from [3] as follows: ( ) n Kv αt clk ΔV th (t) = () 1 β 1/n K v = f(v dd V th ), (3) β = f(t,t clk,tox,t), where t denotes time, t clk is the clock cycle, α is the duty cycle, T is the temperature, and n is a fabrication process constant. The parameters V th and V dd represent threshold voltage and supply voltage, respectively. D. Temperature feature One of the major sources of workload-dependent runtime variations, which strongly influences BTI, is temperature. The temperature and power consumption of a chip are tightly coupled. To convert the power consumption profile to a, Paper 13. INTERNATIONAL TEST CONFERENCE 3

4 A All gates (power) in this area load Point A Vdd Fig. : Equivalent circuit model of a power grid. temperature profile, the layout of the chip is divided into several rectangular grids. Next, the power consumption for each grid is calculated by adding the leakage and dynamic power for the gates located in each grid. The switching activity of each node together with parasitic capacitance information obtained from the floorplan, are used to estimate the leakage and dynamic power of each cell inside the circuit netlist, respectively. Finally, the floorplan and power profile are given to the publicly available tool HotSpot [7] to extract the temperature profile of the chip. In order to encode a path with respect to temperature, the chip area is divided into several grids. The representative temperature feature of the path reflects the grids in which the path passes through. E. Voltage droop feature Due to switching currents and the resistance of the power delivery network, the actual supply voltage level seen by individual gates during circuit operation fluctuates from its nominal value. Voltage droop, which has been shown to vary significantly over time and from gate-to-gate [8], [9], significantly affects BTI-induced delay degradation [3], [3]. According to [31], the power network can be modeled as a resistive network distributed over the die (see Fig. ). Therefore, voltage droop as a function of the drawn current is calculated using the following equation [3]: V grid = G 1 I, (4) where G is the conductance matrix, V grid is a vector of supply voltages of the grids, and I is a vector of current drawn off the power grids. Note that the current drawn from each grid can be calculated by adding the dynamic and leakage currents of all the gates inside the grid. Similar to the temperature feature, the voltage droop feature captures the transformation of voltage grids to the delays of the target paths. i.e., it encodes the membership of each path to the power grids and the corresponding voltage sensitivity to the grid. IV. AGING-AWARE REPRESENTATIVE PATH SELECTION AND PATH DELAY PREDICTION Recall that our goal is to select RCPs for monitoring in order to estimate the chip performance. Based on the measured delays in RCPs, we could accurately estimate the delay of other CPs. Given N CPs, we use an M N matrix P = {p 1,p,...,p N } T to denote these paths. Each path p i = {x i1,x i,...,x im } is encoded with M features as described in Section III. The total delay d i in each path p i is determined by sum of contributions from each feature, namely delay contributions, such that d i = p i T and T = {t i,t,...,t M } T. The delay of N paths can be expressed as D =[d 1,d,...,d N ] T. The selected RCP set can be denoted as P R = {p 1,p,...,p r} T, where P R P and R<<N. Similarly, the delay measurements of the RCPs are of the form of D R =[d 1,d,...,d R ]T. In order to identify the RCP set, we rely on unsupervised machine learning techniques, such as method and clustering, which are discussed below. The choice of unsupervised learning is motivated by the fact that we have no data on the behavior of the chip available for supervised learning. A. method Singular-value decomposition and QR decomposition with column pivoting () is an orthogonal transformation technique that has been widely used for feature selection in many areas, such as signal processing, control theory, and network optimization [33], [34]. Using the method, an RCP set P R can be selected from the complete CP set P. The delay for each CP can be estimated using a linear combination of measured delays in RCPs. The estimated delay D can be expressed as follow: D = PP T R (P R P T R ) 1 D R, (5) where () 1 denotes the inverse matrix. The corresponding estimation error can be measured using relative root meansquared error (), defined as: (D D)) = 1, (6) N range(d) where range(d) is the range of D = max(d) min(d). To accurately predict delays in critical paths using delays in representative paths, the selection of representative paths represents a tradeoff between number of RCP R and prediction error Err. To select RCPs, we rely on SVD factorization, which transforms the matrix P into a product of three matrices. The decomposition can be written as: P = UΣV T, (7) where matrix U R N N and V R M M are orthogonal matrices, and Σ=diag(σ 1 σ... σ M ). The diagonal elements of Σ are called the singular values of P. An important property of SVD is that it reveals the rank of P. In Equation (7), rank(p ) = rank(σ). Consequently, the number of non-zero singular values indicates the rank of the matrix P. However in our application, we can get an even smaller number R<rank(Σ), since the existence of smaller singular values σ i implies the presence of redundancy or less important rules among the rules that forms the complete set [35]. Paper 13. INTERNATIONAL TEST CONFERENCE 4

5 Algorithm 1: method Input: P, p ex th Output: P R,R 1: N number of critical paths in P : Singular-value decomposition: [U, Σ,V] = SVD(P ); 3: R, p ex, array S diag (Σ); 4: while p ex <p ex th do 5: R R +1; 6: p ex = ΣR 1 si Σ, s N 1 si i S; 7: end while 8: Select first R columns in U, U R = U(:, 1:R); 9: QR-decomposition with column pivoting: [Q, R, Π] =QR(UR T ); 1: P n =Π T P ; 11: P R = P n (:, 1:R); 1: return P R and R Fig. 3: Procedure for the method. In order to determine appropriate R, we adopt the criterion p ex, i.e., the percentage of energy explained by singular values [36]. It is defined as: p ex = R i=1 σ i N i=1 σ i 1, (8) where R is the number of RCPs for which the energy explained by the corresponding R number of singular values is p ex percentage of the total energy. In this work, we determine minimum R RCPs to meet P ex >P ex th = 99%, thereby these R RCPs can represent nearly the entire set of CPs. Once we determine the optimal number of critical paths R, we then select the positions of these RCPs based on QR decomposition using column pivoting (QRcp), using following equation: U T R = QRΠ T, (9) where the input to this procedure is U R, a sub-matrix formed by the first R columns of U [], [17]. Q is a unitary matrix, and R is an upper triangular matrix. The permutation matrix Π can transform P, reflected in UR T, so that the critical paths in P n =Π T P appears in a decreasing order of corresponding importance. Then we take the sub-matrix P R formed by the first R rows of P n to be the RCP set. The complete algorithm is presented in Fig. 3, Next, we present a small example to illustrate the selection of RCPs based on. Suppose we have a CP set P and delay contribution vector T as follow: P = T =, , (1) where P consists of 8 CPs as row vectors, each of which has 9 features. An entry of 1 indicates that the CP corresponding to that row exhibits the feature for that column. Delay of CP set is D = P T = {d 1 =11,d =8,d 3 =9,d 4 =4,d 5 =8,d 6 = 9,d 7 =5,d 8 =13}. According to the algorithm shown in Fig. 3, if we set number of RCPs R to be 5, the selected RCP set is P R = {p,p 3,p 5,p 6,p 8 }, and P e x =.95 according to Equation (8). By measuring the delay of RCPs in P R and using Equation (5), we can predict the delay of remaining CPs d 1 = 1.8, d 4 = 3.6, and d 7 = 4.9. The is calculated to be 1.. If we consider fewer RCPs, e.g. R =3, the selected P R = {p,p 5,p 8 }. Then predicted delay of the remaining CPs are d 1 =1.9,d 3 =7.,d 4 = 3.,d 6 =7.6, and d 7 =4.3, and is 7., which is still quite low. B. Clustering method Clustering is an unsupervised learning technique that can be used to cluster critical paths so that critical paths in the same cluster are more similar to each other than those in other clusters. We select one critical path from each cluster to form the RCP set, based on which we predict the delays in the other CPs. Here, we use a widely used clustering methods, namely clustering. clustering incorporates fuzzy logic, whereby each critical path has a probability of belonging to each cluster [19], thus each critical path can probabilistically belong to two or more clusters rather than only one cluster. This fuzzy set membership can be interpreted as that any two paths may share partial features, thus any path is a combination of multiple features that can be regarded as clusters. The objective of C- means clustering is to maximize the inter-cluster variance and minimize the intra-cluster variance. The training of clustering is based on minimization of the objective function J m as shown below: N C J m = u m ij p i c j, (11) i j where m 1 is a weighting factor, and is the Euclidean norm. The parameter N is the number of CPs. Set C consists of k clusters, in which c j is the centroid of each cluster, and u ij is the probability that a path p i belongs to c j.the optimization problem follows two iterative steps of calculating between centroid c j and probability u ij, such that: c j = ΣN i um ij p i Σ N i um ij k j C, (1) C u ij =( ( p i c j p i c k )) 1 i N,j C. (13) Note that computation of the updated probability u ij is necessary for the minimization of the objective function J m [37]. The complete algorithm is shown in Fig. 4. The algorithm will eventually converge to a minimum objective function, under the condition that the change in J m is below some threshold ξ. Paper 13. INTERNATIONAL TEST CONFERENCE 5

6 Algorithm : clustering method Input: P, N, k, ξ Output: U, C 1: Initialize U = {u ij } matrix; : Initialize J m very large value; 3: repeat 4: J old J m ; 5: for each 1 <j<kdo 6: update C = {c j c j = N i um ij pi N i um ij 7: update U = {u ij u ij =( k ( pi cj 8: end for 9: J m = N i C j um ij p i c j ; 1: until J m J old <ξ 11: return U and C }; p i c k )) 1 }; Fig. 4: Procedure for the clustering method. The effectiveness of the clustering method depends on the choice of the number of clusters. If we select too few clusters, we may not cover all the segments in the design. If we select too many clusters, we may exceed the upper limit on the number of CP monitors. We determine the number of clusters by the monitoring resources, e.g. number of sensors. To illustrate the clustering method, we again use the CP set P shown in Equation (1). If we use 5 clusters, reflected as 5 selected representative paths, the membership Matrix U as obtained using the algorithm of Fig. 4 is shown below: U = where each column corresponds to the membership of a CP to each cluster. Here, RCP set P R = {p 1,p 3,p 4,p 5,p 7 } is selected, as these paths have the highest scores in each cluster. The delays of the remaining CPs are calculated using Equation (5) as d =6.9,d 6 =7.8, and d 8 =11.8. Thus the is, which is low, but comparatively higher than the obtained using with the same number of RCPs. V. AGING-AWARE ADAPTIVE PREDICTION As discussed in Section II, aging effects lead to increased delay in functional paths. However, the delay increase in one path differs from another path due to different workloadinduced stress on each segment in these paths. To account for path delay change over time, we propose an update mechanism to reduce the mismatch in aging-induced delay. At design time, we leverage the method (Algorithm 3) to generate a base representative path set P R. We place delay sensors on all paths in P R. At run-time, in addition to P R, we dynamically monitor a set of additional paths P A using path delay testing. The selection of P A depends on the resource budget available for monitoring, which also determines the number of clusters that can be utilized. The set P A is determined using the C- means clustering algorithm, as shown in Fig. 4. The complete set of monitoring paths P = P R P A can thus be generated, as shown in Fig. 5, When we determine the RCP set for monitoring chip performance, we use the delay prediction mechanism shown in Fig. 6. First, we measure the delays D R in the RCP set P R to get the base predicted delay set D. Based on the predicted delay set D and chip topological features, we cluster P in order to select the extra path set P A. The measured delays in the extra paths D A are then compared to the predicted delay D A. We can thus obtain the offset Δ(D A )=D A D A to estimate Δ(D) for all CPs in P. The eventual prediction model in each interval can thus be updated to account for the prediction errors. To illustrate the effectiveness of the adaptive method, we revisit the example from Section IV, as described in Equation (1). Assume that T (see Equation (1)) is the delay contribution vector at t =. If we consider aging, the delay contribution vector changes at t>. Assume that T 1 is the delay contribution vector at some point t = t i during system runtime, as below: T 1 = [ ] T (14)., When we use a set of 5 RCPs out of 8 CPs and the algorithm method alone, the is 1. at t =. When t = t i, the delay set D 1 = P T 1 is {d 1 = 33,d = 8,d 3 = 9,d 4 = 15,d 5 = 9,d 6 = 6,d 7 =1, and d 8 =38}. Based on the measured delays of RCP set P R = {p,p 3,p 5,p 6,p 8 }, the predicted delays of the remaining 3 CPs are d 1 =9.1,d 4 =1.9, and d 7 =19.. Therefore, the increases to 5.8%, which is much larger than the prediction accuracy obtained at t =. The prediction errors can be mitigated using the adaptive method proposed in Fig. 6. We form a set of 5 RCPs, which consists of 3 fixed RCPs (using method) and dynamic RCPs (using clustering method). The RCP set P R selected by is P R = {p,p 5,p 8 }.Att =, the other dynamic RCPs are selected based on The complete set P of CPs method The representative set P R of RCPs Pre determined at design time Predicted delay info D of CPs using RCPs clustering An extra set P A of monitored paths A new set of monitored paths P = P R U P A Determined at each measurement interval Fig. 5: Algorithm for selecting RCPs using a combination of and clustering for runtime monitoring. Paper 13. INTERNATIONAL TEST CONFERENCE 6

7 Measured delays D R in RCP set P R based prediction model Predicted delay info D of CP set P using P R TABLE I: Information about ITC 99 and IWLS 5 benchmark chips. Predicted delays D A in monitored set P A Measured delays D A in monitored set P A Prediction error (D A ) = D A - D A Updated prediction model Adjusted delay prediction D of CP set P using P =P R U P A Fig. 6: Adaptive delay prediction mechanism. method using a matrix P, as follow: P =[P D] = , (15) where D consists of the measured and the -based predicted delays. The additional RCP set P A is selected to be {p 1,p 6 } and the entire RCP set is P = P R P A = {p 1,p,p 5,p 6,p 8 } for t =. Comparing the measured delays of P A and corresponding predicted delays obtained above, we can obtain the prediction errors Δd 1 =.1 and Δd 6 = 1.4. The delay compensation can thus be calculated for the remaining 3 CPs using Equation (5), such that Δd 3 = 1.3, Δd 4 =.9, and Δ d 7 =.5. Therefore the complete prediction delay set D = {d 1 = 11,d = 8,d 3 =8.5,d 4 =4.1,d 5 =8,d 6 =9,d 7 =4.8,d 8 =13}, and is compensated to be.9%, which is less than using either or clustering alone. At t = t i, similar compensation also applies to the delay prediction. We select the RCP set to be P = {p,p 5,p 8 } {U 6,U 7 }. Note that we select a different P A because the predicted delay using is different at t = t i. The predicted delays based on the adaptive method is then D 1 = {d 1 =3.1,d = 8,d 3 =3.4,d 4 =13.9,d 5 = 9,d 6 =6,d 7 =1, and d 8 =38}. The is 4.9%, which is better than the method only. VI. EXPERIMENTAL SETUP AND RESULTS Experiments are performed on several IWLS 5 and ITC 99 benchmark circuits [38], [39] to evaluate the efficiency and accuracy of the proposed methodology. Circuits are synthesized using Synopsys Design Compiler and mapped to the Nangate 45 nm library [4]. The extracted netlists are placed and routed using Cadence SOC Encounter. The power profile is calculated by running different randomly generated input vectors with a switching activity factor of.. Extracted layouts and power profile are given to HotSpot [7] to obtain the thermal profile of the circuit. BTI-induced threshold voltage change is estimated by assuming a delay degradation b17 b18 b19 b RISC vga # of gates 7k 88k 165k 4k 61k 114k # of gate-type features # of temperature features # of voltage features # of process variation features # of critical paths #. of RCPs The number of RCPs is obtained when timing accuracy is higher than 9. of 1 in 3 years. Moreover, each cell in the library is characterized by accurate HSPICE simulation by sweeping: 1) operating voltage, ) temperature, 3) threshold voltage of each transistor, 4) capacitance, 6) input slope, and 7) gate length. This information is then stored in LUTs. Next, extracted thermal and voltage profiles, and estimated V th of each transistor as well as the generated variations-aware LUTs are given to an interpolation procedure to generate a new library file according to the collected information. Moreover, the netlist is modified accordingly to the remapping of each cell to the newly generated library file. Finally, the generated library and netlist are fed to Primetime to extract critical and near-critical paths of the circuit in the presence of aging and variations. Learning algorithms are implemented using the Matlab 11b statistics toolbox. Experiments are run on a 64 bit Linux systems with 1 GB of RAM and qual-core Intel i7 processors running at.67 GHz. We first evaluate the effectiveness of delay prediction when aging-aware features are considered. For a system with a large number of paths (millions or more), we select only the top of critical paths to form a targeted CP set based on corresponding timing slacks. We use the method (Fig. 3) to select the RCP set from the entire CP set. Prediction accuracy is evaluated based on the metric, defined in Equation (6). Table I lists the total number of CPs, the optimal number of RCPs for different benchmark circuits when the required timing accuracy is set to be higher than 9. Note that, for different circuits, the number of selected RCPs are different based on the calculation of P ex and the total number of CPs. According to this table, we observe that the number of RCPs is significanlty smaller than number of CPs. For example, we select 35 RCPs out of a total of 31 CPs for b17, and 46 RCPs out of a total of 366 CPs for RISC processor. These results show that with only a small number of RCPs, we can predict the delays of a large set of CPs with high accuracy. The prediction accuracy for six benchmarks at measurement point t 3y (the third year in system runtime) is plotted in Fig. 7. First, we observe that drops fast when the number of RCP increases. For example in b, if we take all features into account for delay prediction, the obtained by using only 5 RCPs is 1., while the obtained Paper 13. INTERNATIONAL TEST CONFERENCE 7

8 1 % % (a) b17 1 % % (b) b18 1 % % (c) b19 1 % % (d) b 1 % % (e) RISC 1 % (f) vga Fig. 7: Prediction accuracy obtained 1) using all features and ) using only topological feature at t 3y for ITC 99 and ISWL 5 benchmark circuits. for 18 RCPs is only 1.. Second, the is found to remain constant when the number of RCPs is larger than 5 for b. The results show that there is a clear knee in the graphs for all circuits, which indicates that increasing the number of RCPs beyond a certain point does not have a significant impact on accuracy. Therefore, we are able to achieve high prediction accuracy for a large pool of target CP set by monitoring only a few paths and using Equation (5). Note that we can exploit P ex, using Equation (8), to determine the knee point effectively. Third, we observe that drops faster when we use a more detailed model that considers all features than when we use a simple model that includes only topological features. These results highlight the effectiveness of aging-aware features for delay prediction when we build our prediction model using RCPs, as described in Section III. Note that our method is a superset of [17] in which we can predict delay of every critical path in the circuit, in contrast to the overall delay of the entire circuit. Moreover, we consider more complete features such as process variations, voltage droop, and temperature to achieve more accurate results. As depicted in Fig. 7, by considering all the features, the accuracy is improved by 17. on average if we use the same number of RCPs. Next, we illustrate the effectiveness of using adaptive prediction method for six benchmark circuits. The average prediction accuracies are shown in Fig. 8. The adaptive prediction method is a combination of and clustering, described in Fig. 5 and Fig. 6, respectively. We compare the prediction accuracy obtained using same number of RCPs selected by our proposed method to two static path selection methods, namely (Fig. 3) and clustering (Fig. 4). The number of RCPs selected by the C- means clustering method equals the number of clusters. In addition, we have implemented an iterative clustering method based on [41], thereby selecting the clustering setting with near-optimal prediction accuracy. The prediction accuracy is the average of multiple measurement points during the runtime. We observe a higher prediction accuracy when we use the adaptive prediction method, compared to the other two static methods. For example in b19 as shown in Fig. 8, is. if we use the proposed adaptive prediction, while the is.7% if we use and if we use clustering. Finally, in Fig. 9, we present the prediction accuracy trends during runtime. In almost all cases, where each case corresponds to a circuit and a prediction point, the dynamic method (SVD+) offers higher accuracy in comparison to the two static methods. VII. CONCLUSIONS The complexity associated with advanced technology nodes requires the monitoring of a large pool of critical paths to ensure desired performance of a chip over its lifetime. A Paper 13. INTERNATIONAL TEST CONFERENCE 8

9 with with with (a) b17 (b) b18 (c) b19 with (d) b with (e) RISC with (f) vga Fig. 8: Comparison of average prediction accuracy between different RCP selection methods for ITC 99 and IWLS 5 benchmark circuits. with with with (a) b17 (b) b18 (c) b19 with (d) b with (e) RISC with Fig. 9: Comparison of runtime prediction accuracy between different RCP selection methods for ITC 99 and IWLS 5 benchmark circuits. (f) vga Paper 13. INTERNATIONAL TEST CONFERENCE 9

10 small set of representative critical paths are usually adopted as a surrogate to estimate delays for the complete set of critical paths. However, uncertainties introduced by process variations and aging reduce prediction accuracy when a small of representative critical paths is used. As a result, system adaptation effectiveness and resilience are adversely affected. We have shown how reasoning methods based on linear algebra and dynamic compensation based on clustering dynamic machine-learning can be used to account for uncertainties in chip parameters. Simulation results for a range of benchmark circuits highlight the efficiency of the proposed techniques for predicting critical path delays in the presence of process variations and circuit aging. REFERENCES [1] W. Wang et al., The impact of NBTI effect on combinational circuit: modeling, simulation, and analysis, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 18, no., pp , 1. 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