Dynamic Adaptation for Resilient Integrated Circuits and Systems

Size: px
Start display at page:

Download "Dynamic Adaptation for Resilient Integrated Circuits and Systems"

Transcription

1 Dynamic Adaptation for Resilient Integrated Circuits and Systems Krishnendu Chakrabarty Department of Electrical and Computer Engineering Duke University Durham, NC 27708, USA Department of Computer and Information Science and Engineering National Cheng Kung University Tainan, Taiwan 1

2 Acknowledgments Fangming Ye, PhD student at Duke University Farshad Firouzi, PhD student at Karlsruhe Institute of Technology, Germany Prof. Mehdi Tahoori, Karlsruhe Institute of Technology, Germany Sponsor: Semiconductor Research Corporation (SRC) 2

3 Motivation Design-time solutions and guard-bands for resilience no longer sufficient for nanoscale ICs Process variations: each chip born with a unique personality ( nature ) Operating conditions, environment, and workload: each chip grows uniquely ( nurture ) Need: Guarantee that each system, despite different nature and nurture, has an acceptable behavior ( resilience ) Resilience: Persistence of performance level that can justifiably be trusted in the presence of change 3

4 Motivation (Contd.) Dynamic health monitoring of ICs and systems Reuse additional on-chip sensors Voltage sensors, temperature sensors, etc. Reduce number of sensors needed for monitoring Learn, predict, and adapt 4

5 Outline Background Selection of representative critical paths Path encoding and feature identification Dynamic RCP monitoring Results Conclusions 5

6 Circuit Degradation Transistor aging NBTI (PBTI) Degrades path delay Failure rate Burn- in Increased soft errors Aging Time Timing failures Early- life failure Normal lifetime Wearout Degradation rate Varies due to voltage, temperature, workload, process variations 6

7 Prior Work Periodic delay testing [Baba VTS 09] interrupts normal execution of system In-situ sensors [Agarwal VTS 07] Prohibitively large number of sensors Replica circuits [Tschanz VTS 09] Fail to cover the entire circuit Representative critical paths [Xie DAC 10, Wang ICCAD 12] Static, coarse-grained 7

8 Proposed Approach Leverage additional sources (e.g., power, temperature, process variation) for path-delay estimation Chip monitoring o C V o C Core Logic V V Infer delays of larger pool of paths based on small set of paths (RCPs) All Paths Passed gates Passed voltage grid Passed temperature grid Path delay RCP Selection RCP Path delay Infer Dynamic delay-estimation model based on features Early stage Later stage RCP model Updated RCP model Adaptation action A Updated adaptation action A 8

9 Topological feature Chip Features Gate types and locations of gates of path in layout Process-variation feature Captures die-to-die, intra-die, and random variations Temperature feature Reflects temperature grids in which path passes through Voltage feature Reflects voltage grids in which path passes through BTI feature Reflect BTI grid in which path passes through 9

10 Topological Features Describe a path using locations and types of gates in the path 0 AND OR 0 AND AND 0 0 OR 0 0 OR 0 OR 0 OR OR 0 OR 0 OR OR OR OR 10

11 Process Variation Feature 11

12 Temperate/Voltage/BTI Feature Workload on each device is translated to: Voltage Temperature BTI model 12

13 Voltage Feature All gates within this grid load same power 13

14 Temperature Feature Power Chip Solder Polymer Substrate Gel Heat sink R solder R polymer R sub R gel R sink T ambient 14

15 Path Encoding Voltage feature BTI feature about path Processvariation features Temperature feature Topological features Determine Path delay 15

16 RCP Selection Measured delay of representa(ve paths matrix Delays of all paths 16

17 SVD-QRcp Singular value decomposition (SVD) Purpose: Estimate number of RCPs SVD QRcp QR factorization with column pivoting (QRcp) Purpose: Rank CPs, and provide first few RCPs to be selected paths 17

18 Singular Value Decomposition (SVD) Given: mxn matrix A Voltage feature BTI feature Processvariation features Temperature feature Topological features Path delay A D 18

19 Singular Value Decomposition (SVD) Given: mxn matrix A = ULV T U : mxr column orthogonal matrix L : rxr diagonal matrix (non-negative, descending order) V : nxr column orthogonal matrix Singular value 19

20 QR-Factorization with Column Pivoting (QRcp) Given: mxr matrix U = QRP T Q : orthogonal matrix R : singular upper right matrix P : permutation matrix Swap 1 and 3 Max Norm Calcula@on (Col 1 to n) permutation matrix P =[ ] Iteration 20

21 Transformation Matrix Use delays of RCP set and transformation matrix to infer delays of all paths matrix Ts CP set A Measured Delays D of RCP set Es@mated Delays D of CP set 21

22 Example Given a set of critical paths (matrix A) and the corresponding path delays (vector D) A = p 1 d D = p 8 d

23 Example (Contd.) SVD-QRcp method (Step 1: SVD) A=U S V S determines the number of RCPs S = S 2 = RCPs contain most of information of A 23

24 Example (Contd.) SVD-QRcp method (Step 2: QRcp) QR = UE E is the permutation matrix that we need E = Selected RCP set P 5 P 4 A = P 1 P 8 P

25 C-means Clustering Cluster 1 Cluster 2 Cluster 3 CP set A Es@mated Delays D for CP set A 25

26 Example of C-means Clustering Set 5 clusters Membership matrix is W = Selected RCP set P 1 P 3 A = P 4 P 5 P 7 26

27 Dynamic Monitoring (Design Time) Determine RCP set A R CP set A with topological features only SVD-QRcp method C-means clustering method Transformation matrix T S Transformation matrix T C 27

28 Dynamic Monitoring (Design Time) p p 1 2 p p3 p 3 4 p p 5 p 5 p 8 p 6 p 7 9 Transforma@on matrix T S SVD- QRcp method C- mean clustering method Transforma@on matrix T C p 1 p 3 p 5 p 7 28

29 Dynamic Monitoring (Design Time) d d 1 2 d d3 d 3 4 d d 5 d 5 d 8 6 d 7 d 9 Transforma@on matrix T S Tranforma@on matrix T C d 1 d 3 d 5 d 7 29

30 Dynamic Monitoring (Run Time) CP set A with only topological features C-means clustering New transformation matrix T C Additional features of CPs (e.g., T, V, BTI) Estimation error mitigation for P R_C ΔD R_C = D R_C -D R_C RCP subset A R_C Measured delays D R_C Estimated delays D R_C RCP subset A R_S Transformation matrix T S Estimated delays D of A Estimation error mitigation ΔD for A Adjusted delay estimation D =D + ΔD 30

31 Dynamic Monitoring (Run Time) 1. Update transformation matrix T C of C-mean clustering method by using extra features [p 1 +f 1 ] [p 3 +f 3 ] [p 2 +f 2 ] [p 7 +f 7 ] [p 5 +f 5 ][p 4 +f 4 ] [p 8 +f 8 ] [p [p 9 +f 9 ] 6 +f 6 ] C- mean clustering method [p 5 +f 5 ] [p 7 +f 7 ] New Transforma@o n matrix T C 31

32 Dynamic Monitoring (Run Time) matrix T S d d 1 2 d d 3 d 3 4 d 5 d d 8 6 d 7 d 9 d 1 d 3 32

33 Dynamic Monitoring (Run Time) d d 1 2 d d 3 d 3 4 d 5 d d 8 6 d 7 d 9 D R_C d 5 d 7 D R_C Δ d 5 Δ d 7 Δ D R_C 33

34 Dynamic Monitoring (Run Time) Δd Δd 1 Δd 2 4 Δd Δd 3 Δd 3 5 Δd Δd 8 6 Δd 7 Δd9 Δd 5 Δd 7 Δ D R_C New Transforma@on matrix T C 34

35 Dynamic Monitoring (Run Time) 5. Obtain mitigated delays D initial estimated delays D by adding error mitigation ΔD to d d 1 2 d d 3 d 3 4 d 5 d d 8 6 d 7 d 9 Δd Δd 1 Δd 2 4 Δd Δd 3 Δd 3 5 Δd Δd 8 6 Δd 7 Δd9 d" d 1 d 2 4 d d 3 d 3 5 d d 8 6 d 7 d 9 35

36 Example Given a set of critical paths (matrix A) and the corresponding path delays (vector D) A = p 1 d D = p 8 d

37 Demonstration of Dynamic Monitoring Base RCP set (using SVD-QRcp) A R_S = {P 2, P 5, P 8 } Mitigation RCP set (using C-means) A R_c = {P 1, P 6 } D = Use A R_S to predict (sta@c) D = Use A R_C to mi@gate (dynamic) 4.3 Error is 5.8% 13 Error is 0.9% D =

38 Experiments: Benchmarks ITC 99 and IWLS 05 benchmarks b17 b18 b19 b22 RISC vga # gates 27k 88k 165k 40k 61k 114k # gate- type features # temperature features # voltage features # process- varia@on features # cri@cal paths

39 Evaluation Metric 39

40 Estimation Accuracy with Extra Features Using C-means Method Number of RCP estimation accuracy More features estimation accuracy Elbow curve (a) b18 (b) RISC 40

41 Estimation Accuracy with Extra Features Using SVD-QRcp Method Number of RCP estimation accuracy More features estimation accuracy (a) b18 (b) RISC 41

42 Average Estimation Accuracy Proposed method outperforms static SVD-QRcp method and static C-means method 4% 4% 3% 3% rrmse 2% 1% rrsme 2% 1% 0% 0% (b) b18 (e) RISC Proposed method Static SVD-QRcp method Static C-means method 42

43 Runtime Estimation Accuracy 4% 4% 3% 3% rrsme 2% 1% rrsme 2% 1% 0% System runtime (years) (a)b18 Proposed method 0% Static SVD-QRcp method System runtime (years) (b)risc Static C-mean method 43

44 Conclusions Small set of RCPs to infer large pool of CPs Multiple features of path considered: process variation, voltage, temperature, BTI Dynamic monitoring on RCPs offset aging-induced estimation errors Decrease in number of RCPs Increased delay-estimation accuracy 44

Representative Critical-Path Selection for Aging-Induced Delay Monitoring

Representative Critical-Path Selection for Aging-Induced Delay Monitoring Representative Critical-Path Selection for Aging-Induced Delay Monitoring Farshad Firouzi, Fangming Ye, Krishnendu Chakrabarty, and Mehdi B. Tahoori Karlsruhe Institute of Technology, Germany Department

More information

Statistical Analysis of BTI in the Presence of Processinduced Voltage and Temperature Variations

Statistical Analysis of BTI in the Presence of Processinduced Voltage and Temperature Variations Statistical Analysis of BTI in the Presence of Processinduced Voltage and Temperature Variations Farshad Firouzi, Saman Kiamehr, Mehdi. B. Tahoori INSTITUTE OF COMPUTER ENGINEERING (ITEC) CHAIR FOR DEPENDABLE

More information

PARADE: PARAmetric Delay Evaluation Under Process Variation * (Revised Version)

PARADE: PARAmetric Delay Evaluation Under Process Variation * (Revised Version) PARADE: PARAmetric Delay Evaluation Under Process Variation * (Revised Version) Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi Dept. of Electrical Engineering Dept. of Computer Science Texas

More information

Representative Path Selection for Post-Silicon Timing Prediction Under Variability

Representative Path Selection for Post-Silicon Timing Prediction Under Variability Representative Path Selection for Post-Silicon Timing Prediction Under Variability Lin Xie and Azadeh Davoodi Department of Electrical & Computer Engineering University of Wisconsin - Madison Email: {lxie2,

More information

PARADE: PARAmetric Delay Evaluation Under Process Variation *

PARADE: PARAmetric Delay Evaluation Under Process Variation * PARADE: PARAmetric Delay Evaluation Under Process Variation * Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi Dept. of Electrical Engineering Dept. of Computer Science Texas A&M University

More information

EECS150 - Digital Design Lecture 26 Faults and Error Correction. Recap

EECS150 - Digital Design Lecture 26 Faults and Error Correction. Recap EECS150 - Digital Design Lecture 26 Faults and Error Correction Nov. 26, 2013 Prof. Ronald Fearing Electrical Engineering and Computer Sciences University of California, Berkeley (slides courtesy of Prof.

More information

A Novel Cell Placement Algorithm for Flexible TFT Circuit with Mechanical Strain and Temperature Consideration

A Novel Cell Placement Algorithm for Flexible TFT Circuit with Mechanical Strain and Temperature Consideration A Novel Cell Placement Algorithm for Flexible TFT Circuit with Mechanical Strain and Temperature Consideration Jiun-Li Lin, Po-Hsun Wu, and Tsung-Yi Ho Department of Computer Science and Information Engineering,

More information

Low-Rank Approximations, Random Sampling and Subspace Iteration

Low-Rank Approximations, Random Sampling and Subspace Iteration Modified from Talk in 2012 For RNLA study group, March 2015 Ming Gu, UC Berkeley mgu@math.berkeley.edu Low-Rank Approximations, Random Sampling and Subspace Iteration Content! Approaches for low-rank matrix

More information

Predicting Circuit Aging Using Ring Oscillators

Predicting Circuit Aging Using Ring Oscillators Predicting Circuit Aging Using Ring Oscillators Deepashree Sengupta and Sachin S. Sapatnekar Department of Electrical and Computer Engineering University of Minnesota, Minneapolis, MN 55455, USA. Abstract

More information

EECS150 - Digital Design Lecture 26 - Faults and Error Correction. Types of Faults in Digital Designs

EECS150 - Digital Design Lecture 26 - Faults and Error Correction. Types of Faults in Digital Designs EECS150 - Digital Design Lecture 26 - Faults and Error Correction April 25, 2013 John Wawrzynek 1 Types of Faults in Digital Designs Design Bugs (function, timing, power draw) detected and corrected at

More information

TrenchStop Series. Low Loss DuoPack : IGBT in TrenchStop and Fieldstop technology with soft, fast recovery anti-parallel Emitter Controlled HE diode

TrenchStop Series. Low Loss DuoPack : IGBT in TrenchStop and Fieldstop technology with soft, fast recovery anti-parallel Emitter Controlled HE diode Low Loss DuoPack : IGBT in TrenchStop and Fieldstop technology with soft, fast recovery antiparallel Emitter Controlled HE diode C G E Automotive AEC Q101 qualified Designed for DC/AC converters for Automotive

More information

On Critical Path Selection Based Upon Statistical Timing Models -- Theory and Practice

On Critical Path Selection Based Upon Statistical Timing Models -- Theory and Practice On Critical Path Selection Based Upon Statistical Timing Models -- Theory and Practice Jing-Jia Liou, Angela Krstic, Li-C. Wang, and Kwang-Ting Cheng University of California - Santa Barbara Problem Find

More information

Modeling and Analyzing NBTI in the Presence of Process Variation

Modeling and Analyzing NBTI in the Presence of Process Variation Modeling and Analyzing NBTI in the Presence of Process Variation Taniya Siddiqua, Sudhanva Gurumurthi, Mircea R. Stan Dept. of Computer Science, Dept. of Electrical and Computer Engg., University of Virginia

More information

Capturing Post-Silicon Variations using a Representative Critical Path

Capturing Post-Silicon Variations using a Representative Critical Path 1 Capturing Post-Silicon Variations using a Representative Critical Path Qunzeng Liu and Sachin S. Sapatnekar Abstract In nanoscale technologies that experience large levels of process variation, post-silicon

More information

Fast Buffer Insertion Considering Process Variation

Fast Buffer Insertion Considering Process Variation Fast Buffer Insertion Considering Process Variation Jinjun Xiong, Lei He EE Department University of California, Los Angeles Sponsors: NSF, UC MICRO, Actel, Mindspeed Agenda Introduction and motivation

More information

Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks

Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks Sanjay Pant, David Blaauw Electrical Engineering and Computer Science University of Michigan 1/22 Power supply integrity issues

More information

CSE241 VLSI Digital Circuits Winter Lecture 07: Timing II

CSE241 VLSI Digital Circuits Winter Lecture 07: Timing II CSE241 VLSI Digital Circuits Winter 2003 Lecture 07: Timing II CSE241 L3 ASICs.1 Delay Calculation Cell Fall Cap\Tr 0.05 0.2 0.5 0.01 0.02 0.16 0.30 0.5 2.0 0.04 0.32 0.178 0.08 0.64 0.60 1.20 0.1ns 0.147ns

More information

MM74C906 Hex Open Drain N-Channel Buffers

MM74C906 Hex Open Drain N-Channel Buffers Hex Open Drain N-Channel Buffers General Description The MM74C906 buffer employs monolithic CMOS technology in achieving open drain outputs. The MM74C906 consists of six inverters driving six N-channel

More information

MM74C14 Hex Schmitt Trigger

MM74C14 Hex Schmitt Trigger MM74C14 Hex Schmitt Trigger General Description The MM74C14 Hex Schmitt Trigger is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement transistors. The

More information

MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter

MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter General Description The MM74C00, MM74C02, and MM74C04 logic gates employ complementary MOS (CMOS) to achieve wide power

More information

Resilient Design for Process and Runtime Variations

Resilient Design for Process and Runtime Variations Resilient Design for Process and Runtime Variations zur Erlangung des akademischen Grades eines Doktors der Ingenieurwissenschaften der Fakultät für Informatik des Karlsruher Instituts für Technologie

More information

MM74C14 Hex Schmitt Trigger

MM74C14 Hex Schmitt Trigger MM74C14 Hex Schmitt Trigger General Description The MM74C14 Hex Schmitt Trigger is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement transistors. The

More information

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B) 1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed

More information

SGP30N60HS SGW30N60HS

SGP30N60HS SGW30N60HS High Speed IGBT in NPT-technology 30% lower E off compared to previous generation Short circuit withstand time 10 µs Designed for operation above 30 khz G C E NPT-Technology for 600V applications offers:

More information

PERFORMANCE METRICS. Mahdi Nazm Bojnordi. CS/ECE 6810: Computer Architecture. Assistant Professor School of Computing University of Utah

PERFORMANCE METRICS. Mahdi Nazm Bojnordi. CS/ECE 6810: Computer Architecture. Assistant Professor School of Computing University of Utah PERFORMANCE METRICS Mahdi Nazm Bojnordi Assistant Professor School of Computing University of Utah CS/ECE 6810: Computer Architecture Overview Announcement Jan. 17 th : Homework 1 release (due on Jan.

More information

DATASHEET CD4093BMS. Features. Pinout. Functional Diagram. Applications. Description. CMOS Quad 2-Input NAND Schmitt Triggers

DATASHEET CD4093BMS. Features. Pinout. Functional Diagram. Applications. Description. CMOS Quad 2-Input NAND Schmitt Triggers DATASHEET CD9BMS CMOS Quad -Input NAND Schmitt Triggers FN Rev. December 199 Features High Voltage Types (V Rating) Schmitt Trigger Action on Each Input With No External Components Hysteresis Voltage Typically.9V

More information

Fast IGBT in NPT-technology with soft, fast recovery anti-parallel Emitter Controlled Diode

Fast IGBT in NPT-technology with soft, fast recovery anti-parallel Emitter Controlled Diode Fast IGBT in NPTtechnology with soft, fast recovery antiparallel Emitter Controlled Diode 75% lower E off compared to previous generation combined with low conduction losses Short circuit withstand time

More information

Fast IGBT in NPT-technology with soft, fast recovery anti-parallel Emitter Controlled Diode

Fast IGBT in NPT-technology with soft, fast recovery anti-parallel Emitter Controlled Diode Fast IGBT in NPTtechnology with soft, fast recovery antiparallel Emitter Controlled Diode 75% lower E off compared to previous generation combined with low conduction losses Short circuit withstand time

More information

DKDT: A Performance Aware Dual Dielectric Assignment for Tunneling Current Reduction

DKDT: A Performance Aware Dual Dielectric Assignment for Tunneling Current Reduction DKDT: A Performance Aware Dual Dielectric Assignment for Tunneling Current Reduction Saraju P. Mohanty Dept of Computer Science and Engineering University of North Texas smohanty@cs.unt.edu http://www.cs.unt.edu/~smohanty/

More information

SKP15N60 SKW15N60. Fast IGBT in NPT-technology with soft, fast recovery anti-parallel Emitter Controlled Diode

SKP15N60 SKW15N60. Fast IGBT in NPT-technology with soft, fast recovery anti-parallel Emitter Controlled Diode Fast IGBT in NPTtechnology with soft, fast recovery antiparallel Emitter Controlled Diode 75% lower E off compared to previous generation combined with low conduction losses Short circuit withstand time

More information

MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter

MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter General Description The MM74C00, MM74C02, and MM74C04 logic gates employ complementary MOS (CMOS) to achieve wide power

More information

Adding a New Dimension to Physical Design. Sachin Sapatnekar University of Minnesota

Adding a New Dimension to Physical Design. Sachin Sapatnekar University of Minnesota Adding a New Dimension to Physical Design Sachin Sapatnekar University of Minnesota 1 Outline What is 3D about? Why 3D? 3D-specific challenges 3D analysis and optimization 2 Planning a city: Land usage

More information

TAU 2014 Contest Pessimism Removal of Timing Analysis v1.6 December 11 th,

TAU 2014 Contest Pessimism Removal of Timing Analysis v1.6 December 11 th, TU 2014 Contest Pessimism Removal of Timing nalysis v1.6 ecember 11 th, 2013 https://sites.google.com/site/taucontest2014 1 Introduction This document outlines the concepts and implementation details necessary

More information

DATASHEET CD40109BMS. Features. Description. Applications. Functional Diagram. Pinout. CMOS Quad Low-to-High Voltage Level Shifter

DATASHEET CD40109BMS. Features. Description. Applications. Functional Diagram. Pinout. CMOS Quad Low-to-High Voltage Level Shifter DATASHEET CD19BMS CMOS Quad Low-to-High Voltage Level Shifter Features High Voltage Type (V Rating) Independence of Power Supply Sequence Considerations - can Exceed - Input Signals can Exceed Both and

More information

Non-Invasive Pre-Bond TSV Test Using Ring Oscillators and Multiple Voltage Levels

Non-Invasive Pre-Bond TSV Test Using Ring Oscillators and Multiple Voltage Levels Non-Invasive Pre-Bond TSV Test Using Ring Oscillators and Multiple Voltage Levels Sergej Deutsch and Krishnendu Chakrabarty Duke University Durham, NC 27708, USA Abstract Defects in TSVs due to fabrication

More information

TrenchStop Series. P t o t 270 W

TrenchStop Series. P t o t 270 W Low Loss IGBT in TrenchStop and Fieldstop technology C Short circuit withstand time 10 s Designed for : Frequency Converters Uninterrupted Power Supply TrenchStop and Fieldstop technology for 1200 V applications

More information

IGP03N120H2 IGW03N120H2

IGP03N120H2 IGW03N120H2 HighSpeed 2Technology Designed for: SMPS Lamp Ballast ZVSConverter optimised for softswitching / resonant topologies G C E 2 nd generation HighSpeedTechnology for 1200V applications offers: loss reduction

More information

416 Distributed Systems

416 Distributed Systems 416 Distributed Systems RAID, Feb 26 2018 Thanks to Greg Ganger and Remzi Arapaci-Dusseau for slides Outline Using multiple disks Why have multiple disks? problem and approaches RAID levels and performance

More information

Problems in VLSI design

Problems in VLSI design Problems in VLSI design wire and transistor sizing signal delay in RC circuits transistor and wire sizing Elmore delay minimization via GP dominant time constant minimization via SDP placement problems

More information

Soft Switching Series

Soft Switching Series Reverse Conducting IGBT with monolithic body diode Features: 1.5V Forward voltage of monolithic body Diode Full Current Rating of monolithic body Diode Specified for T Jmax = 175 C Trench and Fieldstop

More information

SKP06N60 SKA06N60. Fast IGBT in NPT-technology with soft, fast recovery anti-parallel Emitter Controlled Diode

SKP06N60 SKA06N60. Fast IGBT in NPT-technology with soft, fast recovery anti-parallel Emitter Controlled Diode Fast IGBT in NPTtechnology with soft, fast recovery antiparallel Emitter Controlled Diode 75% lower E off compared to previous generation combined with low conduction losses Short circuit withstand time

More information

High-Performance SRAM Design

High-Performance SRAM Design High-Performance SRAM Design Rahul Rao IBM Systems and Technology Group Exercise RWL WWL READ Path RWL WBL WBLb RBL WWL READ Path WBL WBLb RBL Worst case read condition : Worst case Bitline Leakage when

More information

60 30 Pulsed collector current, t p limited by T jmax I Cpuls 90 Turn off safe operating area V CE 900V, T j 175 C - 90 Diode forward current

60 30 Pulsed collector current, t p limited by T jmax I Cpuls 90 Turn off safe operating area V CE 900V, T j 175 C - 90 Diode forward current Reverse Conducting IGBT with monolithic body diode Features: 1.5V typical saturation voltage of IGBT Trench and Fieldstop technology for 900 V applications offers : very tight parameter distribution high

More information

Physical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006

Physical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006 Physical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006 1 Lecture 04: Timing Analysis Static timing analysis STA for sequential circuits

More information

Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits

Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits Afshin Abdollahi University of Southern California Farzan Fallah Fuitsu Laboratories of America Massoud Pedram University of Southern

More information

MM54C14 MM74C14 Hex Schmitt Trigger

MM54C14 MM74C14 Hex Schmitt Trigger MM54C14 MM74C14 Hex Schmitt Trigger General Description The MM54C14 MM74C14 Hex Schmitt Trigger is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement

More information

Dimension Reduction and Iterative Consensus Clustering

Dimension Reduction and Iterative Consensus Clustering Dimension Reduction and Iterative Consensus Clustering Southeastern Clustering and Ranking Workshop August 24, 2009 Dimension Reduction and Iterative 1 Document Clustering Geometry of the SVD Centered

More information

Understanding Integrated Circuit Package Power Capabilities

Understanding Integrated Circuit Package Power Capabilities Understanding Integrated Circuit Package Power Capabilities INTRODUCTION The short and long term reliability of s interface circuits, like any integrated circuit, is very dependent on its environmental

More information

TrenchStop Series I C

TrenchStop Series I C Low Loss IGBT in TrenchStop and Fieldstop technology Very low V CE(sat) 1.5 V (typ.) Maximum Junction Temperature 175 C Short circuit withstand time 5µs Designed for : Freuency Converters Uninterrupted

More information

SGB02N120. Fast IGBT in NPT-technology. Power Semiconductors 1 Rev. 2_3 Jan 07

SGB02N120. Fast IGBT in NPT-technology. Power Semiconductors 1 Rev. 2_3 Jan 07 Fast IGBT in NPT-technology Lower E off compared to previous generation Short circuit withstand time 10 µs Designed for: - Motor controls - Inverter - SMPS NPT-Technology offers: - very tight parameter

More information

Low Loss DuoPack : IGBT in TrenchStop and Fieldstop technology with soft, fast recovery anti-parallel Emitter Controlled HE diode

Low Loss DuoPack : IGBT in TrenchStop and Fieldstop technology with soft, fast recovery anti-parallel Emitter Controlled HE diode Low Loss DuoPack : IGBT in TrenchStop and Fieldstop technology with soft, fast recovery antiparallel Emitter Controlled HE diode Best in class TO247 Short circuit withstand time 10 s Designed for : Frequency

More information

IKW50N60TA q. Low Loss DuoPack : IGBT in TRENCHSTOP TM and Fieldstop technology with soft, fast recovery anti-parallel Emitter Controlled HE diode

IKW50N60TA q. Low Loss DuoPack : IGBT in TRENCHSTOP TM and Fieldstop technology with soft, fast recovery anti-parallel Emitter Controlled HE diode Low Loss DuoPack : IGBT in TRENCHSTOP TM and Fieldstop technology with soft, fast recovery antiparallel Emitter Controlled HE diode C G E Features: Automotive AEC Q101 ualified Designed for DC/AC converters

More information

EVERLIGHT ELECTRONICS CO.,LTD. Technical Data Sheet High Power LED 1W (Preliminary)

EVERLIGHT ELECTRONICS CO.,LTD. Technical Data Sheet High Power LED 1W (Preliminary) Features Feature of the device: small package with high efficiency Typical color temperature: 3500 K. Typical view angle: 120. Typical light flux output: 33 lm @ 350mA ESD protection. Soldering methods:

More information

Understanding Integrated Circuit Package Power Capabilities

Understanding Integrated Circuit Package Power Capabilities Understanding Integrated Circuit Package Power Capabilities INTRODUCTION The short and long term reliability of National Semiconductor s interface circuits like any integrated circuit is very dependent

More information

EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration under Process Variations

EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration under Process Variations IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1 EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration under Process Variations Grace Li

More information

An Algorithmic Framework of Large-Scale Circuit Simulation Using Exponential Integrators

An Algorithmic Framework of Large-Scale Circuit Simulation Using Exponential Integrators An Algorithmic Framework of Large-Scale Circuit Simulation Using Exponential Integrators Hao Zhuang 1, Wenjian Yu 2, Ilgweon Kang 1, Xinan Wang 1, and Chung-Kuan Cheng 1 1. University of California, San

More information

Stochastic Dynamic Thermal Management: A Markovian Decision-based Approach. Hwisung Jung, Massoud Pedram

Stochastic Dynamic Thermal Management: A Markovian Decision-based Approach. Hwisung Jung, Massoud Pedram Stochastic Dynamic Thermal Management: A Markovian Decision-based Approach Hwisung Jung, Massoud Pedram Outline Introduction Background Thermal Management Framework Accuracy of Modeling Policy Representation

More information

5-V Low Drop Fixed Voltage Regulator TLE

5-V Low Drop Fixed Voltage Regulator TLE 5-V Low Drop Fixed Voltage Regulator TLE 427-2 Features Output voltage tolerance ±2% 65 ma output current capability Low-drop voltage Reset functionality Adjustable reset time Suitable for use in automotive

More information

Skew Management of NBTI Impacted Gated Clock Trees

Skew Management of NBTI Impacted Gated Clock Trees International Symposium on Physical Design 2010 Skew Management of NBTI Impacted Gated Clock Trees Ashutosh Chakraborty and David Z. Pan ECE Department, University of Texas at Austin ashutosh@cerc.utexas.edu

More information

TRENCHSTOP Series. Low Loss DuoPack : IGBT in TRENCHSTOP and Fieldstop technology with soft, fast recovery anti-parallel Emitter Controlled HE diode

TRENCHSTOP Series. Low Loss DuoPack : IGBT in TRENCHSTOP and Fieldstop technology with soft, fast recovery anti-parallel Emitter Controlled HE diode Low Loss DuoPack : IGBT in TRENCHSTOP and Fieldstop technology with soft, fast recovery antiparallel Emitter Controlled HE diode Features: Very low V CE(sat) 1.5V (typ.) Maximum Junction Temperature 175

More information

ic-wg BLCC WGC PACKAGE SPECIFICATION

ic-wg BLCC WGC PACKAGE SPECIFICATION Rev B1, Page 1/5 ORDERING INFORMATION Type Package Options Order Designation ic-wg BLCC WGC none ic-wg BLCC WGC ic-wg BLCC WGC reticle ic-wg BLCC WGC-WG1R WG1R Code Disc 13bit-Gray +2048 PPR A/B, d 44mm

More information

UTPlaceF 3.0: A Parallelization Framework for Modern FPGA Global Placement

UTPlaceF 3.0: A Parallelization Framework for Modern FPGA Global Placement UTPlaceF 3.0: A Parallelization Framework for Modern FPGA Global Placement Wuxi Li, Meng Li, Jiajun Wang, and David Z. Pan University of Texas at Austin wuxili@utexas.edu November 14, 2017 UT DA Wuxi Li

More information

Hyperspherical Clustering and Sampling for Rare Event Analysis with Multiple Failure Region Coverage

Hyperspherical Clustering and Sampling for Rare Event Analysis with Multiple Failure Region Coverage Hyperspherical Clustering and Sampling for Rare Event Analysis with Multiple Failure Region Coverage Wei Wu 1, Srinivas Bodapati 2, Lei He 1,3 1 Electrical Engineering Department, UCLA 2 Intel Corporation

More information

I C. A Pulsed collector current, t p limited by T jmax I Cpuls 3.5 Turn off safe operating area V CE 1200V, T j 150 C - 3.

I C. A Pulsed collector current, t p limited by T jmax I Cpuls 3.5 Turn off safe operating area V CE 1200V, T j 150 C - 3. HighSpeed 2-Technology Designed for frequency inverters for washing machines, fans, pumps and vacuum cleaners 2 nd generation HighSpeed-Technology for 1200V applications offers: - loss reduction in resonant

More information

OFF-state TDDB in High-Voltage GaN MIS-HEMTs

OFF-state TDDB in High-Voltage GaN MIS-HEMTs OFF-state TDDB in High-Voltage GaN MIS-HEMTs Shireen Warnock and Jesús A. del Alamo Microsystems Technology Laboratories (MTL) Massachusetts Institute of Technology (MIT) Purpose Further understanding

More information

Pre and post-silicon techniques to deal with large-scale process variations

Pre and post-silicon techniques to deal with large-scale process variations Pre and post-silicon techniques to deal with large-scale process variations Jaeyong Chung, Ph.D. Department of Electronic Engineering Incheon National University Outline Introduction to Variability Pre-silicon

More information

Transient thermal measurements and thermal equivalent circuit models

Transient thermal measurements and thermal equivalent circuit models AN 2015-10 Transient thermal measurements and thermal equivalent circuit Replaces AN2008-03 About this document Scope and purpose The basis of a power electronic design is the interaction of power losses

More information

Aging Benefits in Nanometer CMOS Designs

Aging Benefits in Nanometer CMOS Designs Aging Benefits in Nanometer CMOS Designs Daniele Rossi, Member, IEEE, Vasileios Tenentes, Member, IEEE, Sheng Yang, Saqib Khursheed, Bashir M. Al-Hashimi Fellow, IEEE Abstract In this paper, we show that

More information

TRENCHSTOP Series. Low Loss DuoPack : IGBT in TRENCHSTOP and Fieldstop technology with soft, fast recovery anti-parallel Emitter Controlled HE diode

TRENCHSTOP Series. Low Loss DuoPack : IGBT in TRENCHSTOP and Fieldstop technology with soft, fast recovery anti-parallel Emitter Controlled HE diode Low Loss DuoPack : IGBT in TRENCHSTOP and Fieldstop technology with soft, fast recovery antiparallel Emitter Controlled HE diode Very low V CE(sat) 1.5V (typ.) Maximum Junction Temperature 175 C Short

More information

Amdahl's Law. Execution time new = ((1 f) + f/s) Execution time. S. Then:

Amdahl's Law. Execution time new = ((1 f) + f/s) Execution time. S. Then: Amdahl's Law Useful for evaluating the impact of a change. (A general observation.) Insight: Improving a feature cannot improve performance beyond the use of the feature Suppose we introduce a particular

More information

Saving Energy in Sparse and Dense Linear Algebra Computations

Saving Energy in Sparse and Dense Linear Algebra Computations Saving Energy in Sparse and Dense Linear Algebra Computations P. Alonso, M. F. Dolz, F. Igual, R. Mayo, E. S. Quintana-Ortí, V. Roca Univ. Politécnica Univ. Jaume I The Univ. of Texas de Valencia, Spain

More information

STA141C: Big Data & High Performance Statistical Computing

STA141C: Big Data & High Performance Statistical Computing STA141C: Big Data & High Performance Statistical Computing Lecture 5: Numerical Linear Algebra Cho-Jui Hsieh UC Davis April 20, 2017 Linear Algebra Background Vectors A vector has a direction and a magnitude

More information

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002 CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18-322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed

More information

IGW25T120. TrenchStop Series

IGW25T120. TrenchStop Series Low Loss IGBT in TrenchStop and Fieldstop technology Short circuit withstand time 10µs Designed for : Frequency Converters Uninterrupted Power Supply TrenchStop and Fieldstop technology for 1200 V applications

More information

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK SUBJECT CODE: EC 1354 SUB.NAME : VLSI DESIGN YEAR / SEMESTER: III / VI UNIT I MOS TRANSISTOR THEORY AND

More information

UNIVERSITY OF MASSACHUSETTS Dept. of Electrical & Computer Engineering. Fault Tolerant Computing ECE 655

UNIVERSITY OF MASSACHUSETTS Dept. of Electrical & Computer Engineering. Fault Tolerant Computing ECE 655 UNIVERSITY OF MASSACHUSETTS Dept. of Electrical & Computer Engineering Fault Tolerant Computing ECE 655 Part 1 Introduction C. M. Krishna Fall 2006 ECE655/Krishna Part.1.1 Prerequisites Basic courses in

More information

A Cross-Associative Neural Network for SVD of Nonsquared Data Matrix in Signal Processing

A Cross-Associative Neural Network for SVD of Nonsquared Data Matrix in Signal Processing IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 12, NO. 5, SEPTEMBER 2001 1215 A Cross-Associative Neural Network for SVD of Nonsquared Data Matrix in Signal Processing Da-Zheng Feng, Zheng Bao, Xian-Da Zhang

More information

SGP20N60 SGW20N60. Fast IGBT in NPT-technology

SGP20N60 SGW20N60. Fast IGBT in NPT-technology Fast IGBT in NPTtechnology 75% lower E off compared to previous generation combined with low conduction losses Short circuit withstand time 10 µs Designed for: Motor controls Inverter NPTTechnology for

More information

Chapter 2 Process Variability. Overview. 2.1 Sources and Types of Variations

Chapter 2 Process Variability. Overview. 2.1 Sources and Types of Variations Chapter 2 Process Variability Overview Parameter variability has always been an issue in integrated circuits. However, comparing with the size of devices, it is relatively increasing with technology evolution,

More information

ECE-470 Digital Design II Memory Test. Memory Cells Per Chip. Failure Mechanisms. Motivation. Test Time in Seconds (Memory Size: n Bits) Fault Types

ECE-470 Digital Design II Memory Test. Memory Cells Per Chip. Failure Mechanisms. Motivation. Test Time in Seconds (Memory Size: n Bits) Fault Types ECE-470 Digital Design II Memory Test Motivation Semiconductor memories are about 35% of the entire semiconductor market Memories are the most numerous IPs used in SOC designs Number of bits per chip continues

More information

Statistical Analysis of Random Telegraph Noise in Digital Circuits

Statistical Analysis of Random Telegraph Noise in Digital Circuits Nano-scale Integrated Circuit and System (NICS) Laboratory Statistical Analysis of Random Telegraph Noise in Digital Circuits Xiaoming Chen 1, Yu Wang 1, Yu Cao 2, Huazhong Yang 1 1 EE, Tsinghua University,

More information

There are six more problems on the next two pages

There are six more problems on the next two pages Math 435 bg & bu: Topics in linear algebra Summer 25 Final exam Wed., 8/3/5. Justify all your work to receive full credit. Name:. Let A 3 2 5 Find a permutation matrix P, a lower triangular matrix L with

More information

Chapter 2. Design and Fabrication of VLSI Devices

Chapter 2. Design and Fabrication of VLSI Devices Chapter 2 Design and Fabrication of VLSI Devices Jason Cong 1 Design and Fabrication of VLSI Devices Objectives: To study the materials used in fabrication of VLSI devices. To study the structure of devices

More information

Thermal Interface Materials (TIMs) for IC Cooling. Percy Chinoy

Thermal Interface Materials (TIMs) for IC Cooling. Percy Chinoy Thermal Interface Materials (TIMs) for IC Cooling Percy Chinoy March 19, 2008 Outline Thermal Impedance Interfacial Contact Resistance Polymer TIM Product Platforms TIM Design TIM Trends Summary 2 PARKER

More information

Stochastic Computing: A Design Sciences Approach to Moore s Law

Stochastic Computing: A Design Sciences Approach to Moore s Law Stochastic Computing: A Design Sciences Approach to Moore s Law Naresh Shanbhag Department of Electrical and Computer Engineering Coordinated Science Laboratory University of Illinois at Urbana Champaign

More information

Soft Switching Series I C I F I FSM

Soft Switching Series I C I F I FSM Reverse Conducting IGBT with monolithic body diode Features: Powerful monolithic Body Diode with very low forward voltage Body diode clamps negative voltages TrenchStop and Fieldstop technology for 1200

More information

SIPMOS Small-Signal-Transistor

SIPMOS Small-Signal-Transistor Type BSS225 SIPMOS Small-Signal-Transistor Feature n-channel enhancement mode Logic level Product Summary 1) V DS 6 V R DS(on),max 45 Ω I D.9 A dv /dt rated Qualified according to AEC Q11 Halogen free

More information

IGW15T120. TrenchStop Series

IGW15T120. TrenchStop Series Low Loss IGBT in TrenchStop and Fieldstop technology Approx. 1.0V reduced V CE(sat) compared to BUP313 Short circuit withstand time 10µs Designed for : Frequency Converters Uninterrupted Power Supply TrenchStop

More information

ReSCALE: Recalibrating Sensor Circuits for Aging and Lifetime Estimation under BTI

ReSCALE: Recalibrating Sensor Circuits for Aging and Lifetime Estimation under BTI ReSCALE: Recalibrating Sensor Circuits for Aging and Lifetime Estimation under BTI Deepashree Sengupta and Sachin S. Sapatnekar Department of Electrical and Computer Engineering University of Minnesota,

More information

Skew Management of NBTI Impacted Gated Clock Trees

Skew Management of NBTI Impacted Gated Clock Trees Skew Management of NBTI Impacted Gated Clock Trees Ashutosh Chakraborty ECE Department The University of Texas at Austin Austin, TX 78703, USA ashutosh@cerc.utexas.edu David Z. Pan ECE Department The University

More information

CD4071BC CD4081BC Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate

CD4071BC CD4081BC Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate General Description The CD4071BC and CD4081BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed

More information

BTI and Leakage Aware Dynamic Voltage Scaling for Reliable Low Power Cache Memories

BTI and Leakage Aware Dynamic Voltage Scaling for Reliable Low Power Cache Memories BTI and Leakage Aware Dynamic Voltage Scaling for Reliable Low Power Cache Memories Daniele Rossi, Vasileios Tenentes, Saqib Khursheed, Bashir M. Al-Hashimi ECS, University of Southampton, UK. Email: {D.Rossi,

More information

TRENCHSTOP TM IGBT3 Chip SIGC100T65R3E

TRENCHSTOP TM IGBT3 Chip SIGC100T65R3E IGBT TRNCHSTOP TM IGBT3 Chip SIGC100T65R3 Data Sheet Industrial Power Control SIGC100T65R3 Table of Contents Features and Applications... 3 Mechanical Parameters... 3 Maximum Ratings... 4 Static and lectrical

More information

PROBABILISTIC LATENT SEMANTIC ANALYSIS

PROBABILISTIC LATENT SEMANTIC ANALYSIS PROBABILISTIC LATENT SEMANTIC ANALYSIS Lingjia Deng Revised from slides of Shuguang Wang Outline Review of previous notes PCA/SVD HITS Latent Semantic Analysis Probabilistic Latent Semantic Analysis Applications

More information

Efficient Selection and Analysis of Critical-Reliability Paths and Gates

Efficient Selection and Analysis of Critical-Reliability Paths and Gates Efficient Selection and Analysis of Critical-Reliability Paths and Gates Jifeng Chen, Shuo Wang, and Mohammad Tehranipoor University of Connecticut, Storrs, CT 0669, USA {jic0900,shuo.wang,tehrani}@engr.uconn.edu

More information

IKW40N120T2 TrenchStop 2 nd Generation Series

IKW40N120T2 TrenchStop 2 nd Generation Series Low Loss DuoPack : IGBT in 2 nd generation TrenchStop with soft, fast recovery antiparallel Emitter Controlled Diode Best in class TO247 Short circuit withstand time 10 s Designed for : Frequency Converters

More information

Laplace-Beltrami Eigenfunctions for Deformation Invariant Shape Representation

Laplace-Beltrami Eigenfunctions for Deformation Invariant Shape Representation Laplace-Beltrami Eigenfunctions for Deformation Invariant Shape Representation Author: Raif M. Rustamov Presenter: Dan Abretske Johns Hopkins 2007 Outline Motivation and Background Laplace-Beltrami Operator

More information

This chip is used for: power module BSM 75GD120DN2. Emitter pad size 8 x ( 2.99 x 1.97 ) Thickness 200 µm. Wafer size 150 mm

This chip is used for: power module BSM 75GD120DN2. Emitter pad size 8 x ( 2.99 x 1.97 ) Thickness 200 µm. Wafer size 150 mm IGBT Chip in NPT-technology Features: 1200V NPT technology low turn-off losses short tail current positive temperature coefficient easy paralleling integrated gate resistor This chip is used for: power

More information

Efficient Incremental Analysis of On-Chip Power Grid via Sparse Approximation

Efficient Incremental Analysis of On-Chip Power Grid via Sparse Approximation Efficient Incremental Analysis of On-Chip Power Grid via Sparse Approximation Pei Sun and Xin Li ECE Department, Carnegie Mellon University 5000 Forbes Avenue, Pittsburgh, PA 1513 {peis, xinli}@ece.cmu.edu

More information

MM74C90 MM74C93 4-Bit Decade Counter 4-Bit Binary Counter

MM74C90 MM74C93 4-Bit Decade Counter 4-Bit Binary Counter 4-Bit Decade Counter 4-Bit Binary Counter General Description The MM74C90 decade counter and the MM74C93 binary counter and complementary MOS (CMOS) integrated circuits constructed with N- and P-channel

More information