PHYSICAL MODELING AND SIMULATION OF THERMAL HEATING IN VERTICAL INTEGRATED CIRCUITS

Transcription

1 PHYSICA MODEING AND SIMUATION OF THERMA HEATING IN VERTICA INTEGRATED CIRCUITS Abderrazzak El Boukili School of Sciece ad Egieerig, Al Akhaway Uiversity, Ifrae, Morocco ABSTRACT Itercoect is oe of the mai erformace determiat of moder itegrated circuits (ICs). The ew techology of vertical ICs laces circuit blocks i the vertical dimesio i additio to the covetioal horizotal lae. Comared to the laar ICs, vertical ICs have shorter latecies as well as lower ower cosumtio due to shorter wires. This also icreases seed, imroves erformaces ad adds to ICs desity. The beefits of vertical ICs icrease as we stack more dies, due to successive reductios i wire legths. However, as we stack more dies, the lattice self-heatig becomes a challegig ad critical issue due to the difficulty i coolig dow the layers away from the heat sik. I this aer, we rovide a quatitative electro-thermal aalysis of the temerature rise due to stackig. Mathematical models based o steady state o-isothermal drift-diffusio trasort equatios couled to heat flow equatio are used. These hysically based models ad the differet heat sources i semicoductor devices will be reseted ad discussed. Three dimesioal umerical results did show that, comared to the laar ICs, the vertical ICs with 2-die techology icrease the maximum temerature by 17 Kelvi i the die away from the heat sik. These umerical results will also be reseted ad aalyzed for a tyical 2-die structure of comlemetary metal oxide semicoductor (CMOS) trasistors. KEY WORDS Modelig ad simulatio, thermal effects, 3D itegrated circuits, CMOS. 1. INTRODUCTION Moder techology of vertical ICs stacks active layers of trasistors oe above the other searated by isulatig oxide, ad coected to each other by metal wires. Vertical ICs are also called three dimesioal itegrated circuits (3D ICs). This techology has the advatage of reducig sigificatly wire legths, icreasig seed, ad rovidig lower ower cosumtio. However, as we stack more trasistors, the ower desity icreases causig the temeratures to icrease maily i the trasistors away from the heat sik [1]. Ad it is well kow that self-heatig limits the erformace of semicoductor electroic ad otoelectroic devices as high ower laser diodes, high ower trasistors, high electro mobility trasistors (HEMTs), or CMOS trasistors [2]. Cosequetly, the self-heatig will also limit the erformaces of the 3D ICs techology. Heat is geerated i semicoductor devices whe carriers (electros ad holes) trasfer art of their eergy to the crystal lattice. The, the thermal (vibratioal) eergy of the lattice rises, which is measured as a icrease i its temerature, T. Withi the semicoductor lattice, the eergy is dissiated by travelig lattice vibratios. The smallest eergy ortios of lattice waves are called hoos, which ca be treated as articles. Microscoic theories of lattice heat geeratio ad dissiatio are based o hoos. The eergy trasfer from carriers to lattice ca occur by diffusio, covectio, or radiatio. This will deed o the semicoductor device uder had. For hysical ad mathematical modelig issues, we

2 assume that the heat trasfer from carriers to lattice, i CMOS devices, is due to diffusio oly. For these CMOS devices, we also assume a local thermal equilibrium betwee lattice ad carriers. The, the lattice temerature T is cosidered to be the same as the electros ad holes temeratures T, ad T, resectively. For these reasos, the steady state o-isothermal drift-diffusio model which ivolves oly diffusio terms is eough for our simulatios. For other devices, as HEMTs or laser diodes, the eergy trasfer from carriers to lattice may occur by diffusio, covectio or eve radiatio. The, a trasiet or steady state o-isothermal Eergy Balace or Hydrodyamic models should be used. The mai focus of this aer is the 3D modelig ad simulatio of electro-thermal self-heatig of 3D ICs with two active CMOS layers as show i Figure 1. The materials used i this 3D ICs are: Alumium (Al), Polysilico (Poly), Silico Dioxide (SiO2), ad Silico (Si). The mathematical model used is based o steady state o-isothermal drift-diffusio model which ivolves Poisso s equatio ad electros ad holes trasort equatios couled to heat flow equatio for lattice temerature. These models imlemet the Wachutka s thermodyamically rigorous model of lattice heatig [3]. Almost all of the mathematical models used for thermal aalysis, by may researchers ad foud i the literature, are oly solvig the heat equatio as i [4]-[17]. Ad the heat source i this heat equatio is assumed to be give. I would say that this is a too simlified model. I our case, we are usig a accurate ad comrehesive mathematical model that coules the heat equatio to the electrical o-isothermal drift-diffusio equatios. I our model, the heat sources are modeled accurately ad roerly ad are deedig strog o electrical currets ad lattice temerature. Heat is geerated i semicoductor lattice wheever hysical rocesses trasfer eergy to the crystal lattice. Deedig o differet eergy trasfer mechaisms, heat sources ca be searated ito: Joule heat, electro-hole (radiative ad oradiative) recombiatio heat, electro-hole geeratio coolig, Thomso heat, Peltier heat, ad otical absortio heat. The mathematical models of these differet heat sources will be reviewed ad discussed. The models of lattice heat sources that we have used will be reseted. This aer is orgaized as follows. Sectio 2 outlies the hysically based steady state o-isothermal drift-diffusio ad lattice heat flow equatios. This sectio resets ad discusses differet models for lattice heat ad coolig sources i semicoductor devices. It does also outlie the umerical methods used to fid the lattice temerature distributio i a tyical 3D ICs structure. Sectio 3 resets the comutatioal methods ad algorithms used to solve ad decoule the equatios. Sectio 4 resets the 3D umerical results ad aalysis for the 3D ICS structure give i Figure 1. Sectio 5 discusses the qualitative ad quatitative validatio of the simulatio results. This sectio also gives a comariso betwee our results ad other results foud i the literature [5],[6],[7],[8],[9]. Sectio 6 holds the cocludig thoughts.

3 Figure 1. 3D ICs with 2 stacked active CMOS layers. 2. PHYSICAY BASED MATHEMATICA MODES Mathematical models of the oeratio ad fabricatio of ay semicoductor device result from may years of academic ad idustrial research ito rocess ad device hysics. The accuracy of the umerical simulatio results deed strogly o the accuracy of the hysically based mathematical models. I this aer, we are doig our best to use accurate hysically based models. 2.1 No-Isothermal Drift-Diffusio Model The o-isothermal drift-diffusio model which takes ito accout the lattice self-heatig effects cosists of a set of fudametal equatios which lik together the lattice local temerature T, electrostatic otetial φ, ad the quasi-fermi levels φ, φ for electros ad holes, resectively. These equatios, which are solved iside ay geeral urose device simulator, have bee derived from Maxwell s laws or from semicoductor Boltzma equatios [10]. They cosist of Poisso s equatio ad the trasort equatios for electros ad holes. Poisso s equatio relates variatios i electrostatic otetial to local charge desities. The trasort equatios describe the way that the electro ad hole desities evolve as a

4 result of trasort rocesses, geeratio rocesses, ad recombiatio rocesses. I the steady state case, these 3 equatios are defied as follows [10]. div ( ε φ ) q( N( φφ,, T ) P( φφ,, T ) D) = 0 (1) div( J ) qgr( φ, φ, φ, T ) = 0 (2) div( J ) + qgr( φ, φ, φ, T ) = 0 (3) The equatio (1) reresets the Poisso s equatio. The equatios (2) ad (3) rereset the trasort equatios for electros ad holes, resectively. The term ε reresets the local ermittivity, q is the magitude of the charge of a electro. The electro ad hole desities N( φ, φ, T ) ad P( φ, φ, T ), resectively, rereset the mobile charges. I Boltzma statistics, they are give by: q( φ φ) N( φ, φ, T ) = Nc( T )ex( ) (4) k T B q( φ φ ) P( φ, φ, T ) = Nv( T ) ex( ) (5) k T B where Nc( T ), Nv( T ), k B rereset the effective desity of states for electros ad holes ad the Boltzma costat, resectively. I Poisso s equatio, D(x) reresets the fixed ad ioized charges [11]. The o-isothermal carrier curret desities J ad J that accout for satially varyig lattice temerature are give by: J = qµ N( φ, φ, T )( φ + P T ) (6) J = qµ N( φ, φ, T )( φ + P T ) (7) where µ ad µ rereset electro ad hole mobilities which may deed o lattice temerature T ad o electric field. These carrier mobilities are the key material arameter i trasort simulatios. They are limited by collisios of electros ad holes with other carriers, with crystal defects, ad with hoos (lattice vibratios). Those scatterig evets slow dow the carriers ad costitute the electrical resistace of the material. Various ad advaced models for carrier mobilities could be foud i [2]. attice temerature variatios is a additioal drivig force for thermal curret. The geeratio of curret by temerature gradiet T is called the Seebeck effect with the thermoelectric owers P ad P ( V / K ), resectively, as material arameter. The thermoelectric owers accout for the extra eergy of carriers above the Fermi level. This eergy icreases with higher temerature due the wider sreadig of the Fermi fuctio. Whe a temerature gradiet occurs, carriers move from hot regios to cold

5 regios i order to reduce that extra eergy. For the o degeerate semicoductors, by: P ad P are give P P kb N( φ, φ, T ) 5 = l( ) ( ks) q + Nc 2 k P( φ, φ, T ) B 5 = l( ) ( + ks) q Nv 2 (8) (9) where the values of ks = ks deed o the domiat carrier scatter mechaisms [12] , 2,3,4, ks = for amorhous semicoductors, for acoustic hoo scatterig, for otical hoo scatterig, for ioized imurity scatterig, ad for eutral imurity scatterig, resectively. For 5 our simulatios, we are takig: ks =. The models for the electro-hole geeratio ad recombiatio GR( φ, φ, φ, T ) ad GR( φ, φ, φ, T ) are detailed i the followig sectio. 2.2 Electro-Hole Geeratio ad Recombiatio Models The et geeratio ad recombiatio rates for electro-hole airs are rereseted by GR( φ, φ, φ, T ) ad GR( φ, φ, φ, T ), resectively. I steady state case, they are give by: GR( φ, φ, φ, T ) = GR( φ, φ, φ, T ) = R( φ, φ, φ, T ) G( φ, φ, φ, T ) (10) I the above equatio (10), R( φ, φ, φ, T ) reresets the total electro-hole recombiatio rate, ad G( φ, φ, φ, T ) reresets the total electro-hole geeratio rate. Accurate models for R( φ, φ, φ, T ) ad G( φ, φ, φ, T ) are essetial for lattice self-heatig simulatios as they do rereset a source of lattice heatig or coolig as we will see later o. The model of R( φ, φ, φ, T ) ad G( φ, φ, φ, T ) deed o the device uder had. For a laser device simulatios, all ossible electro-hole recombiatio or geeratio mechaisms should be icluded. Ad, i this case, R( φ, φ, φ, T ) is give by: R( φ, φ, φ, T ) = R + R + R + R (11) SRH Auger Sot Stim where R SRH reresets the electro-hole recombiatio due to Shockley-Read-Hall [11]. R SRH ivolves eergy levels dee iside the semicoductor bad ga that are geerated by crystal defects. Such dee level defects are able to cature electros from the coductio bad as well as holes from the valace bad ad thereby serve as recombiatio ceters. They are characterized by cature coefficiets c ad c, tra desity N t, ad tra eergy E t. I the steady state case, RSRH is give by:

6 = c c ( N P N P ) 0 0 R S R H N t c N + N 1 + c P + P 1 ( ) ( ) (12) where N ad P rereset the electro ad hole cocetratios defied i the equatios (4) ad (5). N P = N P where N0 ad P0 rereset the electro ad hole equilibrium cocetratios. Ad, reresets the Auger recombiatio [11]. We should ote that recombiatio (o emissio of hotos). SRH RAuger R ad RAuger rereset oradiative I Auger recombiatio the excess eergy is trasferred to aother electro withi the valece or coductio bad. Auger recombiatio may ivolve differet valece bads ad the iteractio with hoos. The Auger electro-hole recombiatio rate is give by: R = ( c ( T ) N + c ( T ) P)( NP N P ) (13) Auger 0 0 where c( T ) ad c ( T ) are the Auger coefficiets ad ca be foud i [11]. RSot ad RStim rereset electro-hole recombiatio rates due sotaeous ad stimulated emissios ad their models ca be foud i [11]. We should also ote that R Sot ad RStim rereset radiative recombiatio (emissio of hotos or light). For the simulatio of CMOS trasistors as i our case, the radiative recombiatio rates R Sot ad R Stim are icluded i the total recombiatio rate R( φ, φ, φ, T ). The geeratio of electro-hole airs is looked at as a source of lattice coolig. Sice it does absorb some of the lattice eergy to geerate electro-hole airs. The geeratio of electro-hole airs requires the iteractio with other articles. Ad it is may due to hoos (thermal geeratio), to hotos (otical geeratio), or to other electros (geeratio due to imact ioizatio) [2]. The et recombiatio rates give above i equatios (12) ad (13) already iclude thermal geeratio as they vaish uder thermal equilibrium, N1P1 = N0P0. I laser diode simulatios, the total electro-hole airs geeratio G( φ, φ, φ, T ) ca be defied by: G( φ, φ, φ, T ) = G + G + G (14) where Otical Im act Bad to Bad GOtical reresets the otical electro-hole airs geeratio due to hotos absortio. This tye of geeratio is the key hysical mechaism i hoto detectors ad other electro absortio devices. Due to absortio, the light itesity decreases as the light eetrates deeer ito the device. If we assume that the otical absortio coefficiet α0 is uiform, the the model of the otical absortio is give by: G O tica l = α I (0 ) ex ( α z ) ħω O t 0 0 (15)

7 where ħ ω reresets hoto eergy, ħ reresets the reduced Plak costat, ω reresets the agular frequecy of the icidet radiatio, ad IOt (0) reresets the otical itesity at the surface ad z reresets the eetratio distace [11]. GIm act reresets the electro-hole airs geeratio due to imact ioizatio. Imact ioizatio is of great imortace i devices like avalache hoto detectors. Sice these devices use high electric field F ad high carrier drift velocities to geerate electro-hole airs. Imact ioizatio is oosite to the Auger recombiatio as it absorbs the eergy of motio of aother electro or hole to geerate a electro-hole air [11]. A tyical model of imact ioizatio is give by [11]: G Im a ct ( F ) α ( F ) J + α ( F ) J P = (16) q where α ( F ) ad α ( F) rereset the ioizatio coefficiets for electros ad holes, resectively. The term F reresets the electrical field. GBad to Bad reresets the electro-hole geeratio airs due to bad-to-bad tuelig. I fact, carriers ca be geerated without additioal eergy by bad-to-bad tuelig with strog electric fields 6 F 10 V / cm >. The model used is give by [11]: γ bbt Bbbt G Bad to Bad ( F ) = Abbt F ex( ) (17) q where the values of A, γ bbt, B bbt bbt deed o the material ad ca be foud i [11]. We should ote that the electro-hole geeratio due to bad-to-bad tuelig is ot cosidered a source of lattice coolig as it does ot eed additioal eergy. 2.3 attice Heat Flow Equatio The hysical ad mathematical modelig of heat geeratio ad dissiatio i semicoductor devices or 3D ICs is extremely challegig. All the material arameters such as carrier mobilities, bad gas, coductivities deed o lattice temerature, T. attice heat is geerated or absorbed wheever hysical rocesses trasfer eergy to the crystal lattice or absorb eergy from the crystal lattice. To accout for lattice self-heatig effects the o-isothermal driftdiffusio equatios (1), (2), ad (3) should be solved self-cosistetly with the lattice heat equatio defied as follows:

8 div( k ( T ) T ) + H ( φ, φ, φ, T ) = 0 (18) where k( T ) reresets the thermal coductivity. For steady state simulatios, the thermal coductivity k( T ) is the oly arameter of equatio (18) that must be secified for each material regio i the structure. Thermal coductivity varies as fuctio of lattice temerature. Its model is give by: k ( T ) = 1 a + b T + c T 2 (19) where a, b, c are costats for each material [e.g., Sze 1981]. H ( φ, φ, φ, T ) reresets the lattice heat geeratio or absortio. Its model should take ito accout all ossible sources of lattice heatig or coolig. For accurate modelig ad simulatio of lattice heatig or coolig, the model of H ( φ, φ, φ, T ) should be develoed roerly ad accurately. This will be doe i the followig sectio. 2.4 attice Heat Geeratio ad Absortio Modelig Accordig to differeces i eergy trasfer mechaisms, heat geeratio sources ca be searated ito: Joule heat, electro-hole recombiatio heat, Thomso ad Peltier heat, ad otical absortio heat. Ad i the same way, the sources of heat absortio which may hel i lattice coolig are may be due to electro-hole geeratio mechaisms. Joule heat. The flow of carriers through a semicoductor is accomaied by frequet carrier scatterig by hoos. This leads to a cotiuig eergy loss to the lattice. Carriers move from a higher electrostatic otetial to a lower otetial, ad the corresodig eergy differece is tyically absorbed by lattice as Joule heat, H J give by: H J 2 2 J J = + qµ N ( φ, φ, T ) qµ P( φ, φ, T ) (20) H J is roortioal to the electric resistace of the material. Recombiatio heat. Whe electro-hole air recombies, the eergy lost is either trasferred to a hoto (light) ad this is kow as radiative recombiatio, or to a hoo (heat) ad this is kow as oradiative recombiatio. The average heat released by electro-hole recombiatio (or absorbed by electro-hole geeratio) is roortioal to the differece betwee the quasi-fermi levels. The amout of heat released ad absorbed H RG which models lattice heatig (due to recombiatio) ad lattice coolig (due to geeratio) is give by: HRG = q( R( φφ,, φ, T ) G( φφ,, φ, T )) φ φ (21)

9 where R( φ, φ, φ, T ) ad G( φ, φ, φ, T ) are give above by the equatios (11) ad (14), resectively. For CMOS trasistor simulatios, as i our case, the recombiatio model of R( φ, φ, φ, T ) give by the equatio (11) is reduced to: R ( φ, φ, φ, T ) = R + R (22) SR H Auger Besides tra recombiatio R, this model also icludes the Auger recombiatio R Auger. Sice the SRH hot carriers geerated durig Auger recombiatio evetually lose their eergy to hoos. For laser diodes, or hoto detectors, the sotaeous recombiatio recombiatio Stim RSot ad the stimulated R may be icluded i R( φ, φ, φ, T ). O the oe had, most of the hotos emitted by sotaeous recombiatio are absorbed by the semicoductor lattice ad evetually coverted ito heat. Stimulated emissio of hotos, due to stimulated recombiatio, also leads to some heat geeratio as those hotos are artially absorbed iside the device. Electro-hole recombiatio also causes a coolig of carriers above the Fermi level. This cotributio is related to the chage i thermoelectric ower P ad P of holes ad electros, resectively ad it is give by [11]: H = q ( R G ) T ( P P ) (23) P Thomso ad Peltier heat. The thermoelectric ower ( V / K ) is a measure for the icrease i average carrier excess eergy with icreasig temerature. It varies with the desity of states, carrier cocetratio, ad temerature. Thomso heat H TP is trasferred betwee carriers ad lattice as curret flows alog a gradiet of the thermoelectric ower. It is give by: H = q T ( J P + J P ) (24) T P Otical absortio heat. Whe otical waves eetrate a material, their eergy ca be artially or fully absorbed. The magitude ad the mechaism of absortio deeds o the hoto eergy hγ. At low hoto eergies, the light is directly absorbed by the crystal lattice. At tyical eergies of hotos, absortio by free carriers domiates. This will quickly dissiates the eergy to the lattice due to very short itra bad scatterig times. The otical absortio related heat H could be modeled by: Otical H O tic a l = α Φ hω (25) 0 O tic a l Where h reresets the Plak costat, α 0 is a costat, ad desity ad it is give by: I Ot Φ Otical = ħω ΦOtical reresets the hoto flux (26)

10 where IOt reresets the magitude of the otical curret. The a comlete model for heat geeratio ad dissiatio H ( φ, φ, φ, T ) may be give as: H( φφ,, φ, T ) = H + H + H + H + H J RG P TP Otical (27) I our case, H Otical is omitted. 2. COMPUTATIONA METHODS AND SOUTION We use fiite volume method to aroximate the strogly couled ad oliear equatios. We use Newto-Rahso s algorithm to liearize (ad decoule) the equatios. Differet imlemetatios of Newto-Rahso s algorithm have bee used. I oe imlemetatio, the equatios are liearized ad ket couled. I aother imlemetatio, the equatios are liearized ad decouled. More details about Newto-Rahso s algorithm ad its differet imlemetatios to solve semicoductor equatios ca be foud i [10]. We use direct methods based o U factorizatio [10] or Multi-frotal U factorizatio with or without ivotig [13] to solve the arisig liear systems. 3D meshig algorithms are based o advaced ad robust domai decomositio methods, Delauay meshig algorithms, ad surface re-meshig techiques. Advaced algorithms ad techiques have also bee develoed to merge the mesh of two differet dies i 3D ICs to a sigle mesh. To mesh a chi of 3D ICs, we decomose the whole chi ito a certai umber of blocks. We mesh searately each block usig the aroriate mesh geeratio tools. The, we merge the mesh of the differet blocks ito a sigle global mesh. The equatios are the solved o this global mesh. The mesh is refied locally eough to get accurate solutios. No automatic refiemet or mesh adatatio rocedure has bee used. That is a other comlicated issue i 3D ICs. Parallelizatio of all these techiques ad algorithms o multi-core rocessors could also be used. The 3D umerical results showig substatial thermal icrease i CMOS trasistors away from the heat sik will be reseted for a tyical structure give by Figure NUMERICA RESUTS AND ANAYSIS The stadard rocess flow of 1 micros techology is used to fabricate each CMOS layer i such a multile layer structure. I this study, we did cosider several kids of thermal eviromets: multile layers (from 1 to 3), layer thickesses (from 10 to 100 micros er layer) ad differet kids of thermal boudary coditios (Dirichlet ad Neuma). These iclude heat sik o to ad bottom, heat sik o either to or bottom, ad a rage of thermal coductace for the cotact wires which rovide additioal coolig for the devices. Drichlet boudary coditios are used o the to ad bottom of the 3D ICs reseted here. Homogeeous Neuma boudaries coditios are used o the remaiig boudaries that are assumed to be adiabatic. For electrical boudaries, we are usig Dirichlet boudary coditios o the source, gate, ad drai ad homogeeous Neuma boudary coditios o the remaiig boudaries. Tyical results will be reseted to demostrate the 3D curret flow ad the resultig heatig effects. Each active layer is 10 micros thick with heat sik o the to ad bottom. So, the bottom device is the oe away from the heat sik. Ad the to device is the closest to the heat sik. We are, the, exectig the temerature to be higher i the bottom device. The alied voltages at the gate ad drai of the bottom active trasistor are 4 volts, resectively to tur o the CMOS trasistor. The thermal coductace of the

11 coectig Alumium wires have bee reduced accordig to the wire legths. It is sigificat that 17 Kelvi icrease i the temerature of the bottom active layer have bee obtaied from the simulatio. For ivestigatio ad comariso uroses, we have set u a similar structure with icreased layer thickess. The wirig thermal coductace s have bee icreased roortioally. We foud a imortat icrease of temerature i a thicker structure. Some tyical results are reseted here to demostrate the 3D curret flow ad the resultig heatig effects. Figure 1 shows a 2 active CMOS layers cofiguratio i 3D. This is a tyical structure i 3D ICs. Each active layer is 10um thick with heat sik o the to ad bottom. The alied voltages at the gate ad drai of the bottom active trasistor are resectively 4 volts to tur o the CMOS device. The thermal coductace of the coectig Alumium wires have bee reduced accordig to the wire legths. Figure 2 shows the electrostatic otetial distributio i the cross sectio of the 3D ICs structure. Figure 3 resets the temerature rofile i the cross sectio of a sigle active layer corresodig to the bottom layer of Figure 1. Figure 4 shows the temerature distributio i the cross sectio of the 2- active CMOS layers give i Figure 1. Figure 4 shows that there is 17 Kelvi icrease i the temerature of the bottom active layer comared to the sigle active layer give i Figure 3. This meas that i 3D ICs the temerature will icrease sigificatly i the layers away from the heat sik. Similar results to those give i Figure 4 have bee reorted i [5],[6], [7],[8],[9].

12 Figure 2. Potetial distributio i the cross sectio of Figure 1. Figure 3. Temerature distributio i the cross sectio of a sigle active CMOS layer.

13 Figure 4. Temerature distributio i the cross sectio of 2-active CMOS layers of Figure Validatio ad comariso of the simulatio results The result i Figure 4 already roves the validity of our simulatio results. Sice the result i the Figure 4 shows that there is 17 Kelvi icrease of temerature i the bottom device which is the oe away from the heat sik. Similar thermal results, for similar 2-die 3D ICs, have bee reorted i [5],[6], [7],[8],[9]. For examle, i [5], the authors aalyzed the thermal imact of 3D ICs techology o higherformace microrocessors by comutig the temeratures of a laar IC based o the Alha rocessor as well as 2-die ad 4-die 3D IC imlemetatios of the same. They have oly solved umerically the heat equatio where the heat source is give. The thermal rofile of the laar IC i Figure 6 i [5] shows that the maximum temerature is 312 Kelvi. Ad the thermal rofile of the 3D IC with 2-die show i Figure 7 of [5] shows that the maximum temerature is 328 Kelvi. This meas that there is 16 Kelvi icrease of temerature i the die

14 away from the heat sik. I our case, we foud a 17 Kelvi icrease of temerature i the die away from the heat sik as show i Figure 4. The our results are quatitatively comarable to those foud i [5]. 6. CONCUSION I coclusio, robust meshig algorithms have bee used to build successfully a 3D stacked CMOS structure. Ad the electro-thermal ivestigatio ad aalysis based o advaced, hysically based, mathematical models ad umerical simulatios did show substatial temerature icrease i CMOS devices away from the heat sik. The exact temerature icrease due to layer stackig is sesitive to layer thickess ad wirig thermal boudary coditios. The ew challeges, i 3D ICs, are agai makig the techology comuter aided desig simulatio tools crucial ad madatory i desigig, otimizig ad aalyzig 3D ICs techology. REFERENCES [1] S. Das, A. Chadrakasa, R. Reif, (2004) Timig, eergy, ad thermal erformace of threedimesioal itegrated circuits. GSVSI 04:14 th ACM Great akes symosium o VSI, [2] J. Pirek, (2003) Semicoductor otoelectroic devices, itroductio to hysics ad simulatio, Elsevier Sciece Publ., Sa Diego, Califoria, USA. [3] G. K. Wachutka, (1990) Rigorous thermodyamic treatmet of heat geeratio ad coductio i semicoductor trasmodelig, IEEE Tras.,CAD-9, [4] W. Huag, K. Sakaraarayaa, K. Skadro, R. Ribado, M. Sta,(2007) Accurate, Pre-RT temerature aware desig usig a arameterized, geometric thermal model. Desig, Automatio, ad Test i Euroe. [5] K. Puttaswamy, G. oh, (2006) Thermal aalysis of a 3D die-stacked high-erformace microrocessor. Great akes Symosium o VSI. [6] P. Michaud, Y. Sazeides,(2007) Aalytical model of temerature i microrocessors. Worksho o Modelig, Bechmarkig ad Simulatio. [7] Y. Zha, S. Saatekar, (2005) A high efficiecy full-chi thermal simulatio algorithm. Iteratioal Coferece o Comuter Aided Desig. [8] D. Oh, C. Che, Y. Hu, (2007) 3DFFT: Thermal aalysis of o-homogeous IC usig 3DFFT Gree fuctio method. Iteratioal Symosium o Quality Electroic Desig. [9] H. Clarke, K. Murakami, (2011) Suerositio ricile alied to thermal aalysis for 3D ICs. Iteratioal Coferece o Circuits, System ad Simulatio. [10] A. El Boukili, (2005) Aalyse mathematique et simulatio umerique bidimetioelle des trasistors biolaires a heterojuctio ar elemets fiies mixtes. P.h.D. Thesis, Paris 6 Uiversity, Paris, Frace.

15 [11] S. M. Sze, (1981) Physics of semicoductor devices. Joh Wiley & Sos Publ., New York, USA. [12] K. W. Boer, (1990) Survey of semicoductor hysics. Vol. I. Va Nostrad Reihold Publ., New York, USA. [13] R. Amestoy, I. S. Duff, (1998) Excellet, multifrotal arallel distributed symmetric ad usymmetric solvers, Comut. Methods. Al. Mech. Eg.,184, [14] S. Selberherr, (1991) Aalysis ad simulatio of semicoductor devices. Sriger-Verlag, Wie- New York. [15] J. Kim, S. Jhag, C. Joh, (2010) Dyamic register-reamig scheme for reducig ower-desity ad temerature. Symosium o Alied Comutig. [16] S. Melamed, T. Thorolofsso, A. Sriisa, A. Cheg, P. Frazo, R. Davis, (2009) Juctio-level thermal extractio ad simulatio of 3D ICs. IEEE Iteratioal 3D Systems Itegratio Coferece. [17] H. Oris, M. Cuak, G. Va Der Plas, P. Marchal, A. Sriivasa, E. Cheg, (2009) Fie-grai thermal modelig of 3D stacked structures. 15 th Iteratioal Worksho o Thermal Ivestigatios of ICs ad Systems, October, euve, Belgium, Authors Abderrazzak El Boukili received both the PhD degree i Alied Mathematics i 1995, ad the MSc degree i Numerical Aalysis, Scietific Comutig ad Noliear Aalysis i 1991 at Pierre et Marie Curie Uiversity i Paris-Frace. He received the BSc degree i Alied Mathematics ad Comuter Sciece at Picardie Uiversity i Amies-Frace. I 1996 he had a idustrial Post-Doctoral ositio at Thomso-CR comay i Orsay-Frace where he worked as software egieer o Drift-Diffusio model to simulate heterojuctio biolar trasistors for radar alicatios. I 1997, he had Euroea Post-

16 Doctoral ositio at Uiversity of Pavia-Italy where he worked as research egieer o software develomet for simulatio ad modelig of quatum effects i heterojuctio biolar trasistors for mobile hoes ad high frequecy alicatios. I 2000, he was Assistat Professor ad Research Egieer at the Uiversity of Ottawa-Caada. Through he was workig at Silvaco Software Ic. i Sata Clara, Califoria-USA as Seior Software Develoer o mathematical modelig ad simulatios of vertical cavity surface emittig lasers. Betwee , he was workig at Crosslight Software Ic. i Vacouver-Caada as Seior Software Develoer o 3D Process simulatio ad Modelig. Sice Fall 2008, he is workig as Assistat Professor of Alied Mathematics at Al Akhaway Uiversity i Ifrae-Morocco. His mai research iterests are i idustrial TCAD software develomet for simulatios ad modelig of oto-electroic devices ad rocesses. htt://