The Impact of BTI Variations on Timing in Digital Logic Circuits

Transcription

1 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY The Impact of BTI Variations on Timing in Digital Logic Circuits Jianxin Fang and Sachin S. Sapatnekar, Fellow, IEEE Abstract A new framework for analyzing e impact of bias temperature instability (BTI) variations on timing in large-scale digital logic circuits is proposed in is paper. This approach incorporates bo e reaction-diffusion model and e charge trapping model for BTI, and embeds ese into a temporal statistical static timing analysis (T-SSTA) framework capturing process variations and pa correlations. Experimental results on 32nm, 22nm and 6nm technology models, verified rough Monte Carlo simulation, confirm at e proposed approach is fast, accurate and scalable, and indicate at BTI variations make a significant contribution to circuit-level timing variations. Index Terms Bias Temperature Instability, Circuit Reliability, Process Variation, Timing Analysis I. INTRODUCTION Reliability issues in very large scale integrated (VLSI) circuits have been a growing concern as technology trends in semiconductor technologies show progressive downscaling of feature sizes. One of e major reliability issues is bias temperature instability (BTI), which causes e reshold voltage, V, of CMOS transistors to increase over time under voltage stress, resulting in a temporally-dependent degradation of digital logic circuit delay. Various optimizations have been proposed to cope wi is degradation, such as slowing e operating frequency wi time, adding delay guardbands, and using adaptive meods to recover from delay degradation. The reaction-diffusion (R-D) model [] [3], based on dissociation of Si H bonds at e Si/SiO 2 interface, has been e prevailing eory of BTI mechanism and has been widely used in research on circuit optimization and design automation. However, over e years, several limitations in e eory have been exposed. For instance, in R-D eory, e rate of recovery is determined by e diffusion of neutral hydrogen atoms, which is not affected by e gate bias. However e measured device recovery begins faster and lasts longer an e prediction of R-D eory, and shows strong dependence on e applied gate bias. An alternative mechanism for explaining BTI effects is e charge trapping and detrapping model [4], in which e defects in gate dielectrics can capture charged carriers, resulting in V degradations. The major difference between e two models is e nature of e diffusing species and e medium at facilitates e diffusion. Based on published works, bo R-D and charge trapping mechanisms exist Manuscript received June 2, 22; revised September 4, 22. This work was supported in part by e SRC under contract 22-TJ-2234 and e NSF under award CCF-7778 and CCF J. Fang and S. S. Sapatnekar are wi e Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455, USA ( fang6@umn.edu, sachin@umn.edu). in current semiconductor technologies, and e superposition of bo models is shown to better match experimental device data [3]. In nanometer-scale technologies, variations in e BTI effect are gaining a great deal of attention under bo R-D and charge trapping frameworks, due to e random nature of defect localization in smaller and smaller transistors; togeer, ese result in increased variations in e number of defects in a transistor. While ere has been a great deal of research on timing variability due to process variations [5] [7], and a few previous works have combined random variation effects from process variations wi deterministic BTI degradations [8] [], e problem of BTI variations has not received much attention. Most of e published circuit-level works incorporating BTI variations are based on e variability model of N IT randomness wiin e R-D framework, introduced by []. This model was applied to analytically determine e effect of BTI variations on SRAM and logic cells, and on circuit and pipeline performance using Monte Carlo simulations in [2], [3]. However, as explored in our paper, for digital logic circuits, e N IT variation in is R-D based model has a relatively small impact on circuit timing variation, as compared wi variations under e charge trapping model and process variations. Anoer model of e BTI-related variations was considered in [9], as caused by process perturbations. Since ese small model perturbations lead to a relatively small change in e BTI-driven delay shift, e impact on circuit timing is a second-order perturbation at is relatively small. On e oer hand, e variations of device-level BTI degradations under e charge trapping model has been discovered to be a significant issue for nanoscale transistors. Charge trapping and detrapping at each defect are random events at are characterized by e capture and emission time constants. This paradigm is intrinsically statistical and it captures not only e variations in e number of defects, but also e variations in V induced by each defect [4] [6]. Under is statistical model, e variation of device lifetime increases significantly, especially for devices wi a smaller number of defects N, as illustrated in Fig.. However, e impact of BTI variations under e charge trapping model on circuit performance has not received much attention, wi only limited works at explore is issue beyond e device level. In [7], models and approaches were proposed for analyzing e impact of BTI variations on circuit performance; however e proposed SPICE-based atomistic approaches are time-consuming and not scalable to Copyright c 22 IEEE. Personal use permitted. For oer purposes, permission must be obtained from e IEEE by ing pubs-permissions@ieee.org

2 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 2 V (a.u.) 2 (a) lifetime criterion V (a.u.) 2 N = 8 N = stress time(a.u.) stress time(a.u.) Fig.. [7]: (a) Narrow distribution of lifetime in large devices where randomness averages out; (b) Large variation of lifetime in small devices where stochasticity predominates. large-scale circuits. As we will show, e charge trapping model is e dominant component of BTI intrinsic variations, and makes significant contributions to circuit delay variation. Furermore its impact grows rapidly as devices scale down, posing increasingly severe reliability issues to digital logic circuits. In is paper, we first introduce e notion of precharacterized mean defect occupancy probability for e charge trapping model to effectively reduce e complexity of circuit-level analysis and to make it possible to handle large-scale circuits. Then we incorporate variations under bo e R-D model and e charge trapping model into a novel temporal statistical static timing analysis (T-SSTA) framework, capturing randomness from bo process variations and temporal BTI degradations. We exercise is approach on large digital logic circuits and show simulation results for e 32nm, 22nm, and 6nm technology nodes. The correlation of process parameters due to pa reconvergence is considered efficiently in modeling and analysis to guarantee bo high accuracy and low complexity. To e best of our knowledge, is is e first circuit-level work at incorporates variations in BTI effects into SSTA under a scalable and computationally efficient procedure. Our experimental results are based on simulations, and show at e proposed analysis approach has an accuracy at lies wiin 2.2% of Monte Carlo simulation while speeding up e calculation by 5. Averaging over all benchmarks considered in our work, e fraction of e variance attributable to process variations, BTI R-D effects, and BTI charge trapping effects is, respectively, 8%, 3%, and 6% at e 32nm node, 7%, 4%, and 26% at e 22nm node, and 66%, 5%, and 29% at e 6nm node. Thus, under ese models, e relative role of BTI charge trapping to circuit variability is projected to increase significantly in e future, but is less an e contribution of process variations. (b) II. MODELING VARIATIONS This section introduces e models used to capture e effects of variations at affect BTI-induced aging. We begin by discussing BTI variations under bo e R-D and charge trapping models. Next, we overview models for process variations, including spatial correlation effects. As in [3], e total reshold degradation V of an MOS device is modeled by superposition as V = V -RD + V -CT + V -RDF, () in which e BTI terms V -RD and V -CT are independent Gaussian random variables at will be given in (5) and (5), and V -RDF is e variation component due to random dopant fluctuation (RDF) [8], [9], which also follows Gaussian, and have no spatial correlations [2]. For each transistor, e sum, V, of Gaussian variables is still a Gaussian, and is sum is an independent random variable for different MOS transistors. A. BTI Variability under e R-D Model Under e R-D framework, e mechanism of BTI in a MOS transistor is explained rough e dissociation of Si H bonds at e Si/SiO 2 interface and e diffusion of hydrogen into dielectric and gate. The number of generated interface traps, Si +, is denoted as N IT, and absolute value of e induced reshold voltage shift, V, is V = q N IT C ox (2) Under e R-D model, e long term reshold voltage shift V under AC BTI stress is modeled in [2], [2] as V (nom) = f AC (SP ) K DC t n (3) in which K DC is a technology dependent constant for DC BTI degradation, and f AC (SP ) is e coefficient at captures e AC degradation wi signal probability SP (e probability of effective BTI stress). The function f AC (SP ) can be precomputed numerically using meod proposed in [2]. For deeply scaled technologies, e device size is small enough at N IT is a random variable, modeled as a Poisson distribution []: N IT Poisson(λ), where λ = N (nom) IT = V (nom) C ox /q (4) Our reliability analysis focuses on late lifetime behavior, when e average numbers of interface traps λ in MOS transistors have relatively large values. For instance, e value of λ corresponding to V =.V for a device wi W L = 2 is about 49 for 32nm PTM [22] model, or 5 for 6nm PTM model, and it increases proportionally wi e device size. It is well-known at for λ >, a Gaussian approximates e Poisson distribution well [23]. Therefore, to simplify our analysis wiout significant loss of accuracy, is Poisson distribution is approximated as a Gaussian distribution wi e same mean and variance µ = σ 2 = λ, hence N IT N(λ, λ). From (2), e reshold voltage degradation under R-D model has e distribution ( ) qλ V -RD N, q2 λ C ox Cox 2 (5) As will be shown in Sec IV, is distribution approximation does not induce significant errors to e circuit level results.

3 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 3 B. BTI Variability under e Charge Trapping Model Recent work [4] on e BTI effect of small-area devices reveals at e degradation and recovery of V proceed in discrete steps, wi variable heights, which could not be explained by e R-D model, but are fully consistent wi charge trapping, which is also observed in random telegraph noise (RTN) and /f 2 noise. Based on ese observations, a newer charge-trapping model was proposed for e BTI effect, in which each defect is characterized by parameters of e capture time τ c and emission time τ e, and each defect s contribution to e device reshold change, V t. These parameters are characterized using e time-dependent defect spectroscopy (TDDS) meod [4], [4], as a distribution shown in e form of a density map as Fig. 2, in which defects wi similar time constants are binned togeer, and e total V t is shown in each grid. Capture time constant c,stress Emission time constant e,relax Fig. 2. The distribution of defects according to eir capture time constant τ c and emission time constant τ e. If is characterization is performed on a large enough device, wi e assumption at V t of all defects are independent and identically distributed (i.i.d.), e density map could be interpreted as e distribution of defects, in which each grid s value represents e probability of defects falling into at grid. The generation of is distribution is part of technology process characterization and independent of circuit structure. Charge trapping (capture) and detrapping (emission) is a stochastic process. Following e models in [6], e capture time, τ c, and e emission time, τ e, are strongly dependent on bias voltage and temperature. In digital circuits ere are only two nontransient voltage stages, logic and logic, hence e bias condition can be simplified to two static modes of stress and relaxation. We capture e temperature dependence effect by e use of a standard corner-based approach where e worst-case temperature corner is assumed. In is way each defect can be described by four time constants, denoted by e vector τ as τ = (τ c,stress, τ c,relax, τ e,stress, τ e,relax ). (6) The defect occupancy probability (i.e., e probability of charge trapping) of a single defect wi time constants τ under AC stress of duty factor DF and time span t is derived in [6] to be: τ e P c (DF, t, τ) = τc + τe ( ( ( exp τc + ) )) τe t, (7) Here e duty factor DF of a device under AC stress is defined as e probability of e transistor in accumulation mode at is effective for BTI stress (in some papers, DF is also referred to as e signal probability SP ). The parameters τ c and τ e are defined as e effective capture and emission time constants under AC stress, which account for e duty factor effect: τ c τ e = DF τ c,stress + DF τ c,relax (8) = DF τ e,stress + DF τ e,relax (9) Fig. 3 shows an example plot of e occupancy probability function, P c (DF, t, τ), of a single defect as defined in (7), wi e values of e time constants shown in e figure. The plot indicates at e occupancy probability P c increases gradually wi DF, but rises rapidly wi time at e range of 5 to 6 a.u P c(df,t) DF.5 2 c, Stress= 3x 3 e, Stress= x 4 c, Relax= x 8 e, Relax= x t (arbitrary unit) Fig. 3. An example plot of defect occupancy probability function P c (DF, t, τ) of a single defect. Since e defect precursors (Si Si bond in e SiO 2 dielectric according to [24]) are created in e fabrication process and uniformly distributed in e dielectric layer, e statistical distribution of capture/emission time constants associated wi each defect is i.i.d. For each defect, e four components of τ are correlated [4], and eir joint distribution can be characterized for a specific technology. In is paper, we follow e assumptions in [7] to generate e distributions of time constants. Fig. 2 shows an example 2-D histogram of e joint distribution of τ c,stress and τ e,relax, which are e dominant components of τ. The proposed approaches in is paper are independent of e distribution of τ. We introduce e concept of e mean defect occupancy probability, Pc (DF, t), which captures e expected value of e probability of a defect charged wi carriers (i.e., captured), based on e single defect model of (7), and f( τ), e joint pdf of τ: P c (DF, t) = P c (DF, t, τ)f( τ)d τ () Fig. 4 shows an example of P c (DF, t) function corresponding to e assumed f( τ) plotted in Fig. 2. This plot indicates at e mean occupancy probability is a monotonically increasing

4 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 4 function of bo DF and time. Due to averaging effects over large number of defects wi different τ, Pc (DF, t) changes more gradually wi time, compared wi P c of a single defect in Fig. 3. Fig. 4. P c (DF,t) DF t (arbitrary unit) The plot of mean defect occupancy probability function P c(df, t). Since P c (DF, t) is only determined by e distribution f( τ) and is independent of e circuit structure, it can be precharacterized numerically using () and stored in a look-up table (LUT) for use in e circuit analysis. For small-geometry devices, e number of defects in a MOS transistor is a relatively small number wi relatively large variation [4]. For a transistor of leng L and wid W, e total number of oxide defects n is empirically modeled as a Poisson distribution []: n Poisson(N), where N = N ot W L. () Here N ot is e density of defects in e dielectric, and N is e total number of defects in e MOS transistor. Note at e Poisson distribution in () has similar form as e R-D model (4), but ey are from different underlying mechanisms: R-D is modeled wi interface traps (Si H bond), while T- D is modeled wi bulk oxide traps (missing oxygen atom in Si O Si bond [24]). Bo kinds of traps are modeled as Poisson distributions due to e random location of e traps in small devices, however ese two distributions are not correlated in nature. Similarly, e number of occupied defects, n c, in a transistor also has a Poisson distribution, wi its mean value N c calculated as follows. n c Poisson(N c ), where N c = N P c (DF, t) (2) Observed in [5], e BTI-induced reshold degradation corresponding to each single defect follows an exponential distribution. Each defect k =,..., n, contributes a reshold degradation of: V (k) Exp(η), where η = η /(W L). (3) The number of occupied defects in a device follows a Poisson distribution by definition because (a) each occupied defect has e same occurrence rate N c /(W L) wiin e device area of W by L, and (b) e occurrence of all occupied defects are independent wi each oer. This is similar to e number of all defects which follows n Poisson(N), and is verified by experimental results in Sec IV. Like N ot, η is a technology-specific constant. The total reshold voltage degradation, V, of a transistor is e sum of contributions V (k) from all occupied defects k in e transistor, i.e., n c V = V (k). (4) k= A closed form of is sum is derived in [5], and e PDF of V turns out be to a complex distribution wi mean µ = N c η and variance σ 2 = 2N c η 2. The mean value corresponds to e nominal case (i.e., each of N c defects results in a reshold degradation of η). In [5], e probit plot of V indicates at for an adequate number of defects (e.g., N c ), e transistor V distribution can be approximated as a Gaussian by matching e mean and variance, resulting in e distribution: V -CT N(N c η, 2N c η 2 ) (5) When e number of occupied defects, N c, is sufficiently large, is Gaussian approximation is justified by central limit eorem (CLT), using e fact at e total reshold degradation is e sum of V from each defect, which are i.i.d. exponential. For smaller devices wi lower values of N c, is Gaussian approximation is not necessarily accurate for individual devices, but e circuit level timing analysis results still have good accuracy compared wi Monte Carlo simulation, which can be justified by e central limit eorem (CLT) because e circuit delay is e sum of e cell delays along e critical pas and approaches a Gaussian distribution. A more detailed discussion about is Gaussian approximation model is available in Sec IV. C. Process Variations and Spatial Correlation Variations in e process parameters also contribute to BTI variability. Process variations are typically classified as lot-tolot, die-to-die (D2D), and wiin-die (WID) variations, according to eir scope; ey can also be categorized, based on eir causes and predictability, as systematic or random variations. Some (but not all) WID variations exhibit spatial dependence knows as spatial correlation, which must be considered for accurate circuit analysis. We employ a widely-used variational paradigm, where a process parameter X is modeled as a random variable about its mean, X, as [25]: X = X + X X = X g + X s + X r σx 2 = σx 2 g + σx 2 s + σx 2 r (6) Here, X g, X s, and X r stand for, respectively, e global component (from lot-to-lot or D2D variations), e spatially correlated component (from WID variation), and e residual random component of process variations. Under is model, all devices on e same die have e same global part X g. The spatially correlated part is modeled using a widely-used gridbased meod [5] for e parameters at exhibit is property, and is zero for ose at are spatially uncorrelated. Under

5 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 5 e spatial correlation model, e entire chip is divided into grids. All devices wiin e same grid have e same spatially correlated part X s ; e X s parameters for devices in different grids are correlated, wi e correlation falling off wi e distance. The random part X r is unique to each device in e system. In is paper we consider e variations in e transistor wid (W ), e channel leng (L), e oxide ickness (T ox ), as well as shifts in e reshold voltage V due to random dopant fluctuations (RDFs). In oer words, for each device, X represents elements of e set {W, L, T ox, V }. As in e large body of work on SSTA, we assume Gaussiandistributed parameters for each of ese process parameters, wi W and L exhibiting spatial correlation, and T ox and V being uncorrelated from one device to e next. The spatial correlation structure is extracted as a correlation matrix [26], and processed using principal components analysis (PCA) to facilitate fast timing analysis [5]. The process parameter value in each grid is expressed as a linear combination of e independent principal components, wi potentially reduced dimension. Notationally, we express each process parameter X as a vector in a random space, wi basis e = [e g, e s, e r, ϵ] T, as X = X + X = X + k T Xe = X + k T Xge g + k T Xse s + k T r e r + k ϵ ϵ (7) σ 2 X = k T Xk X, cov(x i, X j ) = k T Xik Xj k ϵi k ϵj (8) Here, e g = [e W g, e Lg ] T is e basis for e global part (T ox variation and RDF effect are purely random hence do not have a global part), e s = [e,..., e t ] T is e basis of principal components for e spatially correlated part, in which t is e number of dimensions after e PCA processing of correlated part, and e r = [ϵ,..., ϵ m ] T is e basis of random part. The dimension of random part, m, will depend on e implementation of e SSTA algorim, and can vary from constant to linear (of circuit size), as will be shown later in is paper. The random basis e r and its coefficient vector k r are implemented using a sparse data structure. The Gaussian variable ϵ N(, ) is a separate independent random part for use in circuit-level timing analysis. D. Consideration of Process Variations and BTI Interaction Process variations are created at manufacture time, while BTI degradation occurs during e circuit operation. Therefore e effect of process variations is independent from BTI, but e BTI effect will be impacted by process variations, i.e., e BTI degradation is dependent on e actual W, L and T ox of a transistor. This paper assumes e process variations and BTI effects (bo R-D and charge trapping model including variabilities) to be independent and uses a superposition model to calculate e total effect on circuit-level degradations. This is based on e following facts and considerations. The impact of process variations on BTI degradation is a second order effect at is relatively small in nature. For W and L variations, [27] indicates e NBTI effect is more pronounced in narrow and long transistors. However e transistors on e critical pas are normally sized larger (wider) for timing performance, hence less affected by e W and L variations. For T ox variation, a smaller T ox causes elevated BTI degradation speed, but also gives smaller initial V and propagation delay. Therefore e interaction effect actually cancels out wi each oer to some degree, and ignoring it yields pessimistic and safe approximations. The independent assumption simplifies e modeling and analysis and helps achieve linear computational complexity and good scalability (Section III-C). III. TIMING ANALYSIS UNDER VARIATIONS This section introduces e logic cell delay model under BTI variations and process variations. Based on is model, a scalable approach for statistical timing analysis of large digital logic circuits is outlined. A. Cell Timing Model and Characterization We use a cell delay degradation model at is similar to [28]. The delay d i of cell i is modeled using a first-order Taylor approximation, as a linear function of process parameters W j, L j and T ox-j of each transistor j in cell i, and BTI degradation V (j) of each transistor j: d i = d i + d i = d i + d i X X X P i Here P i = {W j, L j, T ox-j, V (j) }, j cell i is e set of variational parameters. The nominal propagation delay d i and its sensitivity d i / X to parameter X P i are computed using standard techniques rough SPICE simulations. This part of e calculation is circuit-independent and performed as part of library characterization. Since all variational parameters X P i are expressed as vectors in e random variable space e in Section II-C, d i, which is a linear combination of ese parameters, is also a vector in space e: ( ) T d i d i = d i + X k X e X P i = d i + k T d g e g + k T d s e s + k T d r e r (9) Here e random part e r = {ϵ X } X Pi is extended to include e random parts from all variational parameters X P i in cell i. B. Circuit Level Timing Analysis At e circuit level, timing analysis is performed using a PERT-like traversal [5] at a fixed time point, where e contributions of e temporal BTI variations can be characterized using e models described in Sections II-A and II-B. The V degradation due to ese two models are uncorrelated, and are found to substantially affect e circuit level delay. In our initial implementation of algorim, as in [7], e random part k T r e r of arrival time is merged into e separate independent term k ϵ ϵ at is e product of scalars to reduce

6 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 6 e computational complexity. The temporal statistical static timing analysis (T-SSTA) result of is meod is denoted as T-SSTA. Table I shows e mean and standard deviation of circuit delay degradation on benchmark c354 under a 6nm technology model at t=2 (a.u.), splitting e contribution of e mean and variance into ose attributable to BTI R- D, BTI charge trapping (CT), process variations (PV), and finally presenting e combined values (ALL). The results of mean and standard deviation calculated by Monte Carlo (MC) simulation are listed as reference, and e results indicate at e mean value of delay degradation is mainly contributed by BTI RD and BTI CT, while e standard deviation is mainly contributed by BTI CT and PV effects. By comparing results for ALL from T-SSTA meod wi MC, we can see T- SSTA overestimates e mean value and underestimates e standard deviation, where e errors are mainly coming from e BTI CT part. TABLE I T-SSTA RESULTS UNDER VARIATIONS (TIME UNIT: PS) c354 6nm MC T-SSTA T-SSTA2 T-SSTA3 D =582.3 µ D σ D µ D σ D µ D σ D µ D σ D BTI RD BTI CT PV ALL independent of each oer, but are correlated. However e conventional SSTA meod, using an separate independent term k ϵ ϵ to replace k r e r, does not capture is pa correlation and introduces errors. The same situation occurs when calculating e total delay using e maximum of AT N and AT N, which are correlated because e pas from node N8 reconverge. One natural way to resolve is problem is to preserve e entire random part k r e r when calculating e arrival times, by which e pa correlation is captured. This meod is denoted as T-SSTA2 in Table I, and e results indicate is meod is much more accurate an T-SSTA. However, e cost paid for is accuracy is in e increased computation time associated wi e growing size of e random part (e.g., AT N in e example contains components from cells B, C, D, and F ). The computational complexity is discussed wi more details in Section III-C and e experimental runtime and storage comparison will be given in Section IV. We employ a ird meod, denoted as T-SSTA3 in Table I, taken from [29], to provide a trade off between e accuracy and complexity. This removes only e smaller elements in e random vector k r using preset reshold and merges em into e separate term k ϵ. Results in Table I show at is meod achieves good accuracy (wiin 2% error compared wi T-SSTA2 and Monte Carlo) wi low computation. We will expand on is in Section IV. Fig. 5. An example circuit showing pa reconvergence. Investigating is furer, we find at e error between conventional meod (T-SSTA) and Monte Carlo (MC) simulation can be attributed to e correlations at arise due to pa reconvergence, which are neglected in T-SSTA. The BTI CT part of V degradation contains a significant amount of independent random component in e form (7), hence generates large errors due to pa reconvergence. We illustrate e pa reconvergence effect rough Fig. 5, which shows an example circuit where e arrival time AT of node N, denoted as AT N, is calculated as follows AT N = max (AT N8 + d F, AT N9 + d F 2 ) (2) where AT N8 and AT N9 stand for e arrival times of node N8 and N9, while d F and d F 2 stand for e delays from e first and second input to e output of cell F. The arrival times and cell delays are modeled as vectors in random variable space e. Note at since cell C and D have a common fanin of cell B, AT N8 and AT N9 are bo dependent on e random component of e parameters of cell B, corresponding to e impact of X r in Equation (6). As a result, e independent components in e expression for AT N8 and AT N9 are not F F2 C. Computational Complexity To calculate e circuit delay, e SSTA algorim does a topological traversal rough e digital circuit. For each node (logic cell), e timing analysis performs k sum-of-two and k max-of-two operations, where k is e number of fan-in of e cell. In random space e wi dimension d, e numbers of total sum and max operations for SSTA are N sum = n k d (2) N max = n (k ) d (22) Here d = d g + d s + d r, in which d g, d s and d r are e dimension of global component e g, spatial component e s and random component e r, respectively. The values of d g and d s are well bounded by PCA algorim erefore can be regarded as constant. The values of d r depends on how e random part is handled as discussed in Section III-B. For meods T-SSTA and T-SSTA3 d r is bounded by a constant, while for T-SSTA2 d r can grow significantly depending on e circuit size and structure. For simplicity it can be roughly approximated as d r n, which corresponds to e dep of e circuit (number of cells on e critical pas). Therefore e computational complexity is O(n) for T-SSTA and T-SSTA3, and O(n.5 ) for T-SSTA2. This result indicates e proposed T-SSTA3 meod has good scalability to handle large scale circuits. IV. RESULTS Our approach for timing analysis under BTI variations and process variations is applied to ISCAS85 and ITC99

7 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 7 benchmarks. The benchmark circuits are mapped to a subset of e Nangate cell library [3] using ABC [3], wi placement carried out using a simulated annealing algorim. The benchmark circuits are scaled down to 32nm, 22nm and 6nm for comparisons under different technology models. The characterization of cell delay and of its sensitivities to variational parameters is performed using HSPICE simulation under PTM models [22]. Bo e proposed analytical meod and e Monte Carlo meod (for verification) are implemented in C++ and run on a Linux PC (3GHz CPU, 2GB RAM). The process variations in W, L, and T ox are set to 3σ = 4% of eir mean values [32]. The V variation due to RDF is dependent on e device size [2]. It has a Gaussian distribution wi mean value µ =, and standard variation W L σ V = σ V (23) W L in which σ V is e RDF-induce reshold standard deviation of a minimum-sized device (W by L ). The value of σ V is dependent on process parameters T ox and N a, as well as e doping profile of e channel [2]. Here we assume 3σ V = 5% of e nominal V. The parameter variations of W and L are split into 2% of global variation, 2% of spatially correlated variation and 6% of random variation, while e variations of T ox and V are fully random. The gridbased spatial correlation matrix is generated using e distance based meod in [26], wi e number of grids growing wi circuit size, as shown in e Table III. The Monte Carlo simulation framework for verification of e proposed approach is set up as follows: e simulation program randomly generates 5 circuit instances (we found it a good trade-off of accuracy and runtime). For each circuit instance, e V of each MOS transistor is calculated as e sum of e following ree components: (a) V -RD, which is set by (5) and is randomly generated based on e distribution of N IT as specified in (4), (b) V -CT, which is set as e sum of V of all defects at are randomly generated using distributions () and (3), and (c) V -RDF, which is due to RDF effects and set by (23). The contributions of V -RD and V -CT vary wi different technologies [3]. In e experiments it is assumed at ese two have comparable mean values, so at eir contributions to circuit-level variations can be easily visualized. The process parameters W, L, and T ox of each MOS transistor are also generated according to eir distributions and correlation models. Then e propagation delay of each cell is calculated using (9) and pre-characterized cell delay and sensitivity data. Based on ese values and a PERT-like traversal, e total delay of e circuit instances is evaluated using statistical static timing analysis (SSTA). For each benchmark circuit, e mean and standard deviation of e circuit delay are calculated at time t=2 (a.u.), using e proposed analytical meod and Monte Carlo (MC) simulation. The ree meods of handling random parts discussed in Section III-B are implemented separately. As before, T-SSTA merges e random part into one variable, T-SSTA2 preserves full random part, and T-SSTA3 partially lumps e random part. Table II shows e nominal delay D of each benchmark circuit, as well as e mean µ and standard deviation (SD), σ, of e circuit delay using ree analytical meods and e MC simulation, at 32nm, 22nm, and 6nm. The last row shows e relative error of µ D and σ D of each analytical meod, compared wi MC. The mean and SD of e V contributions (averaged over all devices in e circuit) from e R-D model and from e charge trapping model are also listed in Table II. Note at e simulation is based on e assumption at e V contributions (mean value) from R-D model and charge trapping model are comparable. This assumption is made to give a general insight at e charge trapping model predicts significantly larger BTI variability an R-D model. The proposed approaches for circuit degradation analysis is actually independent wi is assumption and can handle different cases of e BTI degradation model. In general cases of application, bo R-D and charge trapping model of BTI effects can be characterized for given technology and used for analyzing e circuit timing degradations. It is also wor noting at under certain cases (especially at 6nm, under e charge trapping model), e value of 3σ can be larger an µ, indicating Gaussian distribution may not be an accurate approximation of V since V from BTI effects should always be positive. However is inaccuracy of e Gaussian approximation is averaged out by e sum of delay along e critical pa, and e circuit level delay, calculated by sum and max operations in SSTA, and approaches a Gaussian distribution according to e central limit eorem (CLT), which does not require e transistor V to be Gaussian. Therefore e proposed meod appears to be robust even under is model inaccuracy, as verified by e good accuracy indicated in Table II, and e visuallyverified match between distribution functions plotted in Fig. 6, which shows an example of e circuit delay distribution for c354 at 6nm at t=2 (a.u.). The T-SSTA3 and MC meods match well, verifying e validity of our assumptions; T-SSTA is significantly different, due to e omission of pa correlations. Fig PDF of circuit delay (unit: ps).5 Monte Carlo T SSTA3 T SSTA Monte Carlo T SSTA3 T SSTA CDF of circuit delay (unit: ps) The delay PDF and CDF of c354 wi 6nm model. Table III compares e runtime and storage complexity (in

8 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 8 TABLE II MEAN AND SD OF CIRCUIT DELAY USING DIFFERENT METHODS (TIME UNIT: PS, AVERAGE ERROR SHOWN FOR µ D AND σ D ) Circuit & Initial T-SSTA T-SSTA2 T-SSTA3 MC V -RD (mv) V -CT (mv) Technology D µ D σ D µ D σ D µ D σ D µ D σ D µ σ µ σ c c c c c nm b b b b b Avg Err % c c c c c nm b b b b b Avg Err % c c c c c nm b b b b b Avg Err % Total Avg Err TABLE III COMPARISON OF COMPUTATIONAL COMPLEXITIES, WHERE T exe= RUNTIME, [CELLS] = AVERAGE NUMBER OF CORRELATED CELLS. 4 MC Circuit Size T-SSTA T-SSTA2 T-SSTA3 MC Name #cells #grids T exe T exe [Cells] T exe [Cells] T exe c s 5.8s s 3. 8s c s 3.5s s 2.7 2s c s 4.s s s c s 37.8s s s c s 2.s s s b s 352.4s s 3. 8s b s 53s s s b s 482.s s s b s 439.s s s b s 67.2s s s terms of e average number of correlated cells, denoted as [Cells]) of e analytical meods and MC. Fig. 7 shows e runtime vs. circuit size (number of logic cells) for e different meods. The results indicate at e runtime of partially lumping random part (T-SSTA3) meod grows linearly wi circuit size increasing, indicating good scalability. It has an overall error of about 2% to MC, and is 5 faster on average. Furermore, it reduces runtime by 6% and storage by 98% on average compared wi T-SSTA2, wi similar accuracy. The conventional meod (T-SSTA) has e shortest runtime, but has nearly 9% errors wi respect to MC. The results also verify at e Gaussian approximations for V in BTI R-D and charge trapping models are valid; e meod is accurate, efficient, and scalable. Moreover, e standard deviation of circuit delay σ D Runtime (sec) Fig T SSTA2 T SSTA3 T SSTA Circuit size (# of cells) x 4 Runtime vs. circuit size of different meods. increases wi technology downscaling, indicating at random timing variation attributable to BTI is a growing issue. Fig. 8 shows e variance of circuit delay at originates from process variations, R-D BTI variations, and charge trapping BTI variations separately, for different benchmarks under e 32nm, 22nm, and 6nm technology models. For better presentation of data, e variances are normalized to e total variance of 32nm model for each benchmark. These results indicate at e charge trapping model is e dominant component of BTI variations, and makes a significant contribution to circuit delay variation. In contrast, e BTI variations under e R-D model only introduce a relatively small portion

9 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 9 Variance of Delay (normalized) nm 22nm 6nm Process Variations BTI R-D BTI Charge Trapping c267 c354 c535 c6288 c7552 b5 b7 b2 b2 b22 Fig. 8. Relative contribution of BTI charge trapping, BTI R-D, and process variation to circuit delay variation. of delay variations. Unlike process variations which have nearly constant influence on delay variation, e impact of BTI variations grows wi scaling, becoming increasingly severe in future. Furer, according to e results in Table II and Fig. 8, e circuit level delay variation at can be attributed to BTI variations is not as significant as e single-device V variation due to BTI effect of a small transistor shown in Fig. (b). This is mainly due to e facts at (a) transistors on e critical pas usually have larger an minimum sizes to help wi timing, and (b) e average out of randomness of e transistor V on e critical pas due e sum of delay. Fig. 9. Normalized Delay PV+BTI Var PV+BTI nom BTI nominal Time (a.u.) Delay degradation vs. time of c535 Fig. 9 presents e circuit delay degradation vs. time curves of benchmark c535 at 6nm. Three curves are shown for e normalized delay of () nominal BTI degradation, wiout any variation model; (2) µ + 3σ of process variation (PV) and nominal BTI degradation; and (3) µ + 3σ of PV and BTI wi variabilities (under bo R-D and charge trapping models). The results indicate at BTI degradation and variability, which grow wi time, make up e dominant part of total delay degradation, especially at e later point of circuit lifetime. Furermore, BTI variations has a significant impact on circuit reliability. In is case, e circuit lifetime will be overestimated by over 2 if BTI variations is not considered (lifetime defined as 25% increase of delay from time zero). V. CONCLUSION This paper incorporates bo e R-D and charge trapping models of BTI variations into a T-SSTA framework, capturing process variations and pa correlations. Experimental results show at e proposed analysis meod is fast and accurate. Our results indicate at e charge trapping mechanism, which has been neglected by e EDA field so far, is e dominant source of BTI variations, wi significant and growing contributions to circuit timing variations. REFERENCES [] M. A. Alam, A critical examination of e mechanics of dynamic NBTI for PMOSFETs, in Proceedings of e IEEE International Electronic Devices Meeting, Dec. 23, pp [2] S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, A finite-oxide icknessbased analytical model for negative bias temperature instability, IEEE Transactions on Devices and Materials Reliability, vol. 9, no. 4, pp , Dec. 29. [3] S. Mahapatra, A. E. Islam, S. Deora, V. D. Maheta, K. Joshi, A. Jain, and M. A. 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10 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY [7] B. Kaczer, S. Mahato, V. V. de Almeida Camargo, M. Toledano- Luque, P. J. Roussel, T. Grasser, F. Catoor, P. Dobrovolny, P. Zuber, G. Wir, and G. Groeseneken, Atomistic approach to variability of bias-temperature instability in circuit simulations, in Proceedings of e IEEE International Reliability Physics Symposium, Apr. 2, pp. XT.3. XT.3.5. [8] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, Matching properties of MOS transistors, IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp , Oct [9] A. J. Bhavnagarwala, X. Tang, and J. D. Meindl, The impact of intrinsic device fluctuations on CMOS SRAM cell stability, IEEE Journal of Solid-State Circuits, vol. 36, no. 4, pp , Apr. 2. [2] Y. Taur and T. H. Ning, Fundamentals of modern VLSI devices. Cambridge University Press, 998. [2] W. Wang, V. Reddy, A. T. Krishnan, R. Vattikonda, S. Krishnan, and Y. Cao, Compact modeling and simulation of circuit reliability for 65- nm CMOS technology, IEEE Transactions on Devices and Materials Reliability, vol. 7, no. 4, pp , Dec. 27. [22] Predictive Technology Model, ptm/. [23] J. H. Pollard, A Handbook of Numerical and Statistical Techniques: Wi examples mainly from e Life Sciences. Cambridge University Press, 977. [24] T. Grasser, B. Kaczer, W. Goes, T. Aichinger, P. Hehenberger, and M. Nelhiebel, A two-stage model for negative bias temperature instability, in Proceedings of e IEEE International Reliability Physics Symposium, Apr. 29, pp [25] S. Nassif, Delay variability: Sources, impact and trends, in Proceedings of e IEEE International Solid-State Circuits Conference, Feb. 2, pp [26] J. Xiong, V. Zolotov, and L. He, Robust extraction of spatial correlation, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 4, pp , Apr. 27. [27] G. Ma, C. Benard, J. L. Ogier, and D. Goguenheim, Geometry effects on e NBTI degradation of PMOS transistors, in IEEE Integrated Reliability Workshop (IRW) Final Report, Oct. 28, pp. 5. [28] B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy, Impact of NBTI on e temporal performance degradation of digital circuits, IEEE Electron Device Letters, vol. 26, no. 8, pp , Aug. 25. [29] L. Zhang, W. Chen, Y. Hu, and C. C. Chen, Statistical timing analysis wi extended pseudo-canonical timing model, in Proceedings of e Design, Automation & Test in Europe, Mar. 25, pp [3] Nangate 45nm Open Cell Library, [3] Berkeley Logic Synesis and Verification Group, ABC: A System for Sequential Synesis and Verification, Release berkeley.edu/ alanmi/abc/. [32] C. Zhuo, D. Blaauw, and D. Sylvester, Post-fabrication measurementdriven oxide breakdown reliability prediction and management, in Proceedings of e IEEE/ACM International Conference on Computer- Aided Design, Nov. 29, pp Sachin S. Sapatnekar (S 86, M 93, F 3) received e B. Tech. degree from e Indian Institute of Technology, Bombay, e M.S. degree from Syracuse University, and e Ph.D. degree from e University of Illinois at Urbana-Champaign. From 992 to 997, he was on e faculty of e Department of Electrical and Computer Engineering at Iowa State University. Since 997, he has been at e University of Minnesota, where he currently holds e Distinguished McKnight University Professorship and e Robert and Marjorie Henle Chair in Electrical and Computer Engineering. He is an auor/editor of eight books, and has published widely in e area of computer-aided design of VLSI circuits. He has served as General Chair and Technical Program Chair of e ACM/EDAC/IEEE Design Automation Conference, e ACM International Symposium on Physical Design, and e IEEE/ACM International Workshop on e Specification and Synesis of Digital Systems (Tau). He has served on e editorial boards of several publications, including e IEEE Transactions on Computer-Aided Design (currently as Editor-in-Chief), IEEE Design & Test of Computers, e IEEE Transactions on VLSI Systems, and e IEEE Transactions on Circuit and Systems II. He is a recipient of e NSF CAREER Award, six conference Best Paper awards and a Best Poster Award, and e Semiconductor Research Corporation (SRC) Technical Excellence award. Jianxin Fang received e B.S. and M.S. degree in electronic engineering from Tsinghua University, Beijing, China, in 24 and 27, and e Ph.D. degree in electrical engineering from University of Minnesota in 22. He is currently a senior engineer in e ASIC design automation department wi Qualcomm Technology Inc., San Diego, CA. His research interests are reliability- and variationaware CAD techniques, particularly related to e effects of oxide breakdown, hot carrier effects and bias temperature instability. Jianxin was a recipient of e ISQED 2 Best Paper Award and e IRPS 22 Best Poster Award.