CMOS Active-Cascode Gain Stage

Transcription

1 Hndut CMOS Active-Cscde Gin Stge Yun Chiu ABSTRACT An s-dmin nlysis f the full dynmics f the ple-zer pir (frequency dublet) sscited with the brdly used CMOS ctive-cscde gin-enhncement technique is presented. Quntittive results shw tht three scenris cn rise fr the settling behvir f clsed-lp ctive-cscde pertinl mplifier depending n the reltive lctins f the unity-gin frequencies f the uxiliry nd the min mplifiers. The nlysis ls revels tht lthugh thereticlly pssible it is prcticlly difficult t chieve n exct ple-zer cncelltin. The nlyticl results presented here prvide thereticl guidelines t the design f CMOS pertinl mplifiers using this technique. Keywrds CMOS pertinl mplifier gin enhncement ctive cscde regulted cscde gin bsting ple-zer pir dublet slw settling I. INTRODUCTION Invented in 1979 [1] nd subsequently refined in 1990 [] [4] the CMOS ctive-cscde gin-enhncement technique 1 finds wide pplictins in nlg integrted circuits such s Nyquist-rte nd versmpling dt cnverters smple-nd-hld mplifiers switched-cpcitr filters bnd-gp reference circuits nd vltge regultrs. By bsting the lw-frequency trnscnductnce f the cscde device the technique increses the utput resistnce f CMOS cscde pertinl mplifier (p mp) nd hence the vltge gin withut degrding its high-frequency perfrmnce. As result it is idelly suitble fr n-chip pplictins where lrge ginbndwidth prduct is desirble while driving cpcitive lds. In dditin s the technique derives extr gin lterlly using n uxiliry mplifier (bster) withut stcking multiple cscde trnsistrs it retins the highswing feture f simple cscde stge nd thus becmes widely ppulr in scled CMOS technlgies with lw supply vltges. In smpled-dt pplictins the circuit ccurcy nd speed re usully determined by the settling behvir f p mps when emplyed. In n ttempt t chieve high unity-gin frequency nd high dc gin simultneusly the ctive cscde intrduces ple-zer pir (dublet) ner the unity-gin frequency f the uxiliry mplifier which ptentilly leds t slw-settling behvir f such p mps []. A guideline t vid the deleterius effects f the dublet ws ls discussed in []. Hwever n ccurte clsed-frm slutin f the dublet des nt exist. Lcking thereticl guidnce designers ften resrt t circuit simultrs t verify nd t fine-tune their p mps rendering the design prcess time cnsuming nd heuristic. 1 Alterntive nmes re gin bsting regulted cscde nd ctive-feedbck cscde

2 Hndut This nte exmines the dublet behvir f CMOS ctive cscdes. Quntittive nlysis revels tht three scenris cn rise fr the clsed-lp settling behvir dependent n the rti f the unity-gin bndwidth f the bster t tht f the min mplifier. Sectins II nd III review the principles f the cscde gin stge nd the CMOS ctive-cscde technique respectively. Sectin IV presents smll-signl nlysis f the ctive cscde nd clsed-frm slutin f the dublet fllwed by the crrespnding result n settling behvir. In Sectin V cmputer simultin results re shwn t vlidte the develped thery; nd lstly brief summry cncludes the nte in Sectin VI. II. CMOS ACTIVE-CASCODE GAIN TECHNIQUE Cscde prvides gin-enhncement functin in mplifier circuits llwing the prduct f the intrinsic gins f tw stges cmmn-surce stge (CS) nd cmmn-gte stge (CG) t be develped in ne. This hs n dvntge in the ttinble bndwidth f the mplifier when driving cpcitive ld which itself cts s the cmpenstin cpcitr [5] [6]. As result single-stge cscde mplifier typiclly exhibits better pwer efficiency reltive t Miller-cmpensted tw-stge design nd is widely used in nlg circuits. A. Smll-Signl DC Gin A typicl CMOS cscde gin stge is shwn in Fig. 1 lng with its utput impednce s functin f frequency in Fig. 1b. In vltge-gin mplifier tw-prt frmultin redily shws tht the smll-signl gin is simply the prduct f the effective input trnscnductnce (G m ) nd the utput resistnce (R ) f the stge [7]. In Fig. 1 ssuming bth trnsistrs re bised in sturtin the drin current f M 1 is nly wekly influenced by M (thrugh chnnel-length mdultin) nd the fllwing expressin f G m hlds: g r 1 r G g g m 1 m m1 m1 gmr 1 r 1 r. (1) Thus the extr gin develped by the cscde cn nly be explined by the increse in R : m 1 1 R g r 1 r r. () Eq. () is bvius when we cnsider the stge s degenerted current surce frm the utput-resistnce stndpint i.e. trnsistr M is degenerted by r 1 when the gtes f M 1 nd M re bth c-grunded. The fctr g m r 1 is just the lp-gin f the lcl series feedbck frmed by M nd r 1. Thus the dc gin f the stge is dc m m1 1 m 1. A G R g r g r (3) B. Frequency Respnse Next we cnsider the frequency respnse f the stge by dding ld cpcitr C t the utput. We will neglect ll ther cpcitnce in the circuit fr simplicity. Since the dditin f C hs n effect n the G m prt f - -

3 Hndut I B Z (jω) (lg) Z (jω) = R // (jωc ) -1 Out (jωc ) -1 V B In M X M 1 C R r 1 ~A =g m r ω ω 1 ω u ω (lg) () (b) Fig. 1. CMOS cscde gin stge: () simplified circuit digrm nd (b) Bde plt f the utput impednce. The frequency dependence f the utput impednce derives frm C. (1) the frequency dependence derives slely frm the utput impednce Z (s) which cn be expressed s 1 R Z s R sc (4) 1 sr C nd depicted in Fig. 1b by the slid lines. Since in this cse the G m prt exhibits n frequency dependence the verll frequency respnse f the smll-signl gin is simply GR m As Gm Zs (5) 1 sr C which hs dminnt ple t ω ( 1/R C ) nd unity-gin frequency f ω u ( g m1 /C ). III. CMOS ACTIVE-CASCODE GAIN TECHNIQUE CMOS ctive cscde further imprves the chievble dc gin by emplying lterl uxiliry mplifier A (s) in Fig. t enhnce the cscde effect. The pertin principles f the technique cn be explined s fllws. A. Output Resistnce nd Gin At this pint we understnd tht the extr vltge gin f the nrml cscde stge in Fig. 1 derives frm the imprved utput resistnce due t the lcl series feedbck frmed by M nd r 1. Therefre dditinl gin cn be ptentilly btined by further incresing either g m r r 1. The ctive-cscde technique explits the g m ptin s shwn in Fig.. Let s cnsider the effective trnscnductnce f M due t the presence f the uxiliry mplifier. The gte-surce vltge f M is 0 v x = v x nd v y v x = (A +1)v x befre nd fter the bster insertin respectively. Therefre the net effect f the bster is essentilly t mke the effective trnscnductnce f M - 3 -

4 Hndut V B A (s) Y I B M X C Out Z (jω) (lg) R r r 1 (jωc ) -1 A (jω) Z (jω) = R (jω) // (jωc ) -1 A B C R (jω) ~A ~A In M 1 ω ω 3 ω ω 1 ω ω u Dublet ω (lg) () (b) Fig.. CMOS ctive-cscde gin stge: () simplified circuit digrm nd (b) Bde plt f the utput impednce. The frequency dependence f the utput impednce derives frm C nd the uxiliry mplifier A (s). (A +1) times lrger with everything else being equl between Figs. 1 nd. Thus the dc slutin t the ctivecscde mplifier f Fig. cn be redily btined by substituting (A +1)g m fr g m in (1) (3): A 1 g r 1 r G g g m 1 m m1 m1 A 1 gmr 1r 1 r (6) 1 1 R A 1 gm r 1 r r (7) Adc gm 1r 1 A 1 gmr 1. (8) We see tht the key functin f the bster is t enhnce g m hence t further increse the utput resistnce (nd gin) f the mplifier. 3 This is dne by intrducing push-pull pertin between the surce nd gte vltges f M i.e. between ndes X nd Y thrugh the insertin f bster mplifier. This inevitbly intrduces nther negtive feedbck lp tht is lcl t the cscde M. As the bndwidth f the bster mplifier is finite the frequency respnse f the ctive cscde exhibits n interesting rtifct ple-zer pir r frequency dublet which will be explined next. B. Frequency Dublet Fr simplicity we will ssume single-ple rll-ff fr the uxiliry mplifier: A A 1 sa (9) s. The bdy effect f M cn be redily included in (6) (8). Fr exmple the dc gin is Adc gm 1r 1 A 1 gm gmb r 1 with bdy effect. 3 A similr rgument ls suggests tht the technique wrks nly fr MOSFET nt BJT mplifiers in tht the bse resistnce f BJT will ultimtely limit the chievble mplifier utput resistnce t pprximtely β 0 r where β 0 is the smll-signl current gin f the BJT regrdless f the vlue f A

5 Hndut A r r C /x C Fig. 3. Mdel f the utput impednce f the ctive cscde in Fig.. Therefre the frequency dependence f the gin stge cn be redily btined by replcing A with A (s) in (6) (8). The effect f A (s) n the utput resistnce ws qulittively nlyzed in [] which is sketched in Fig. b. Let s exmine R first. The rll-ff f A (s) t high frequency intrduces frequency dependence f R s illustrted by the dsh-dtted lines in Fig. b mthemticlly 1 1 R s A s 1 gm r r r r. (10) In Fig. b r = g m r 1 r +r 1 +r which cn ls be btined frm (10) by setting A (s) t 0. Thus R (s) exhibits ple t ω 3 nd zer t ω in Fig. b. The verll utput impednce f the stge Z (s) is then the prllel cmbintin f R (s) nd (sc ) 1 1 Z s R s sc (11) which is represented by the slid lines in Fig. b. An equivlent RC mdel f Z (s) ws prpsed in [8] which is sketched in Fig. 3. If we divide the frequency xis int three bnds by ω 3 nd ω in Fig. b the left resistr A r in Fig. 3 cptures the lw-frequency utput resistnce in regin A (ω ω 3 ) the middle series R-C netwrk cptures the rll-ff prt f R (s) in regin B (ω 3 ω ω ) nd the flt prt in regin C (ω ω ) nd lstly the right C represents the shunt ld cpcitr. In regins A nd B n pprximte expressin f the utput impednce is 1 x Z s A r sc sc (1) where x = ω 3 /ω = ω /ω. Obviusly this nly results in ne ple t ω. In regins B nd C n pprximte expressin f the utput impednce is given by rc 1 s x 1 Zs x r. sc 1 rc sc sc 1 s x x (13) Apprently this results in tw ples nd ne zer with ple t s 1 x / r C nd zer t s x / r C p z - 5 -

6 Hndut bth re very clse t the unity-gin frequency f the bster ω when x >> 1 hlds. This is the ple-zer pir r dublet. C. Slw Settling In [9] [11] clsed-lp mplifier cntining clsely spced ple-zer pir in its frequency respnse ws exmined. It ws fund tht lthugh the dublet effect n the pen-lp Bde plt is ften negligible its deleterius impct n the time-dmin settling behvir my be significnt. Specificlly it intrduces s-clled slw-settling cmpnent t the step respnse f the mplifier. The mgnitude f the slw cmpnent is prprtinl t the dublet spcing nd the time cnstnt crrespnds t the dublet frequency. The sme line f develpment will be fllwed here t estblish frmewrk fr the next tw sectins. Let the pen-lp trnsfer functin hve clsely spced ple-zer pir t (ω z ω p ). The dminnt ple nd unity-gin frequencies ω nd ω u respectively re given fr the pen-lp respnse. When the lp is clsed the feedbck will reduce the ple-zer spcing by n munt equl t the lp-gin t the dublet frequency; nd the clsedlp ple frequency will mve t ω p ' [10] [11]. With the ssumptin ω << (ω z ω p ) << βω u the step respnse f the clsed-lp mplifier is given s where β is the feedbck fctr nd ' ut p t 1 V t V 1 k e k e (14) ' 1 z p z p p z z k. u z u (15) The k term in (14) is the slw-settling cmpnent when ω p ' < βω u hlds. IV. SOLVING DOUBLET Fr the CMOS ctive cscde lthugh the pprximte equivlent circuit mdel f Z (s) in Sectin III-B revels the existence f ple-zer pir ner the unity-gin frequency f the uxiliry mplifier ω the results re nly qulittive s the frequency dependence f G m (s) is nt cnsidered in the mdel. In this sectin we will ttempt t btin n exct smll-signl slutin fr the dublet. In the tretment the frequency dependence f the circuit is ssumed t derive frm the ld cpcitr C nd the bster A (s); nd ll ther cpcitnce will be neglected first t keep the mth trctble. After the first-rder ple- zer behvir is derived the effects f ther cpcitnce in the circuit will be exmined in Sectin V using cmputer simultin. A. Open-Lp Trnsfer Functin T slve fr the pen-lp trnsfer functin we first btin the expressins fr G m (s) nd Z (s): - 6 -

7 Hndut m G s g A s 1 g r 1 r m 1 m1 A s 1 gmr 1 r 1 r (16) s 1 R Zs R s. (17) sc 1 sc R s The prduct f (16) nd (17) gives the smll-signl vltge gin A s G s Z s m A s 1 A 1 A1 1 sc R s A A1 A 1 A 1 A 1A 1 s. A A 1 A 1 A 1 r 1 r C s A 1 r 1 r C s (18) where A 1 = g m1 r 1 A = g m r nd the expressin f A (s) in (9) is ssumed. B. Frequency Dublet The numertr f (18) redily slves t ne LHP zer: A 1 sz. A 1 A (19) T slve fr the ples we define γ = r / r 1 ω u = g m1/ C nd r 1 = A 1/ C ω u ; the denmintr f (18) reduces t the fllwing: 1 A 1 s A u u s 0. A A A1 A AA 1 A (0) Due t the presence f the dublet we my ssume tht ne ple is t s p1 = αω with α 1; nd (0) cn be fctrized int u s s 0. A A1 A 1 (1) Cmpre (1) with (0) we btin A 1 A 1 u A 1 A A A A 1 1 () where A A u is ssumed since x >> 1. At this pint we rrive t the slutin fr the tw LHP A 1 1 ples f the pen-lp trnsfer functin: - 7 -

8 Hndut u sp 1 u A1 A 1 A 1 A 1 (3) A 1 A 1 sp u A 1 A AA 1 A 1 (4) where the fct x = ω 3/ ω >> 1 is gin ssumed. C. Clsed-Lp Settling Behvir We recgnize tht s p1 f (3) is the dminnt ple f the pen-lp mplifier nd (s z s p ) f (19) nd (4) frm dublet. Substituting (19) nd (4) in (15) results in n expressin fr the slw-settling cmpnent: ' p (5) 1 A A 1 k. A 1 A 1 u AA 1 A 1 (6) Eq. (6) revels tht three scenris cn rise fr the clsed-lp settling behvir dependent n ω / ω u the rti f the unity-gin bndwidth f the uxiliry mplifier t tht f the pen-lp min mplifier: 1) k = 0 criticlly dmped when ω u/ ω γa 1 = g m1 r. The ple cncels the zer exctly nd the slwsettling term vnishes; ) k > 0 versht when ω u/ ω < g m1 r. This results in flling dublet; 3) k < 0 slw settling when ω u/ ω > g m1 r. This results in rising dublet the ne ften cited in literture []. In dditin s ω u = g m1/ C the criterin ω u/ ω = g m1 r leds t ω = 1/r C. In ther wrds even when cnstnt C is ssumed the significnt dependence f r n the mplifier utput vltge mkes it prcticlly difficult t chieve n exct ple-zer cncelltin. There re tw strtegies t vid the deleterius effect f the dublet. One suggests t mke ω > βω u t vid slw settling []. The ther suggests t mke k smll enugh i.e. t hve slw-but-ccurte dublet. Let s exmine the fesibility f the ltter. Assuming very slw dublet i.e. ω << βω u hlds then fllwing (6) k 1 1. A A A (7) 1 This implies tht k cnnt be mde rbitrrily smll the smllest vlue f k is prprtinl t the ccurcy level f the riginl mplifier withut gin enhncement. A slw-but-ccurte dublet des nt exist

9 Hndut Tble I. Smll-signl prmeters used in simultin β 0.5 r 10 k f u 00 MHz C m C /3 A 40 db C gs1 C /6 g m1 ma/v C gs C /6 g m 1 ma/v C gd1 C /1 r 1 10 k C gd C /1 V. COMPUTER SIMULATION Cmputer simultins re perfrmed t vlidte the nlysis develped in Sectin IV. Fr esy ccess t nd prgrmmbility f ll device prmeters i.e. g m r etc. smll-signl liner mdel f the ctive cscde shwn in Fig. 4 ws used insted f rel trnsistr circuit. An idel VCVS mdels the uxiliry mplifier with trnsfer functin A (s). In Fig. 5 the externl feedbck is ssumed idel with feedbck fctr β = ½ (i.e. the clsed-lp gin is ); nd 1-V step is pplied t the input. A cpcitr C m n nde X (resulting in the secnd ple) nd the C gs nd C gd s f M 1 nd M re ls included fr cmpleteness. All device prmeters used in the simultin re listed in Tble I. A. Intrinsic Dublet Behvir T evlute the intrinsic behvir f the dublet ll cpcitrs re remved except C in Fig. 4; the unity-gin frequency f A (s) is swept t bserve the settling behvir f the clsed-lp mplifier. Figs. 6 nd 6b shw the utput vltge nd the nrmlized settling errr f the circuit respectively. The settling errr is defined s () (b) Fig. 4. Clsed-lp settling behvir fr f = 10 khz 100 khz 1 MHz 5 MHz 9 MHz MHz 0 MHz nd 30 MHz: () the mplifier utput vltge (incresing in f frm bttm up) nd (b) the nrmlized settling errr (incresing in f frm tp dwn). Open-lp prmeters: f = 10 khz f u = 100 MHz nd A t = 80 db. The dshed curves (f = MHz) crrespnd t the cse f k = 0 i.e. exct ple-zer cncelltin

10 Hndut () (b) Fig. 5. The sme results s thse f Fig. 4 with the inclusin f C m. The phse mrgin f the lp-gin is 71. The dshed curves re fr C m = 0. The bsic settling behvir remins the sme in the presence f secnd ple. () (b) Fig. 6. The sme results s thse f Fig. 4 with the inclusin f C m nd the C gs nd C gd s f M 1 nd M. The slw tils f the trnsients clsely resemble thse f the riginl cse (the dshed curves) in spite f the initil significnt vershts. t V Vi t t V t i (8) It is pprent tht indeed three scenris fr the settling behvir exist s predicted in Sectin IV-C. Specificlly criticlly dmped utput trnsient ws bserved cnfirming the pssibility f n exct ple-zer cncelltin. In the exmple used here (6) predicts tht k = 0 when f = (πr C ) 1 10 MHz; while cmputer

11 Hndut Fig. 7. The nrmlized settling errr fr f = MHz (dshed curve) 100 MHz nd 1 GHz with f p 300 MHz. simultin revels tht this ctully ccurs fr f MHz. In dditin Fig. 6b further indictes tht when the slw-settling cmpnent is relly slw (ω << βω u ) the knee ccurcy where the slw term strts t dminte is lwys nerly 40 db crrespnding t k = 1/βA 0 = 0.01 s predicted by (7). B. Effect f the Secnd Ple A cpcitr C m t nde X in Fig. 4 is dded t intrduce nn-dminnt ple with frequency three times lrger thn βω u the clse-lp bndwidth (i.e. the phse mrgin f the lp-gin is rund 71 ). The simultin results re shwn in Figs. 7 nd 7b. The bsic settling behvir is unltered with the inclusin f the secnd ple; nd the slw tils fter the initil vershts die ut clsely resemble thse f the cse with C m = 0 especilly when ω << βω u hlds. C. Effect f Other Prsitics The C gs nd C gd s f the trnsistrs M 1 nd M re further included t mke the smll-signl mdel cmplete. Resnbly lrge vlues fr these cpcitrs re ssumed (Tble I) nd the simultin results re shwn in Figs. 8 nd 8b. Agin the behvir f the slw-settling cmpnent is seemingly independent f the vrius secndrder effects intrduced by the prsitics. An exct ple-zer cncelltin lwys ccurs fr f MHz. In [] the criterin βω u < ω < ω p ws prpsed t ensure prper pertin f the ctive cscdes. This is verified in simultin by keeping C m cnstnt while stepping ω up t nd beynd ω p. Fig. 9 illustrtes tht sluggish settling ccurs when ω is in the vicinity f ω p where the lcl feedbck lp frmed by the bster nd the cscde becmes mrginlly stble. The instbility is lifted when ω is further pushed ut (nt shwn in the figure)

12 Hndut VI. CONCLUSION An ccurte clsed-frm s-dmin nlysis nd cmputer simultin results f the ple-zer pir (dublet) sscited with the widely used CMOS ctive-cscde gin stge re presented. The cnventinl picture f slw settling is clrified nd ugmented with set f equtins tht cmpletely describe the dublet dynmics. These results prvide esy-t-fllw guidelines t the design f such mplifiers in prctice. REFERENCES [1] B. J. Hstick Imprvement f the gin f MOS mplifiers IEEE Jurnl f Slid-Stte Circuits vl. 14 pp Jun [] K. Bult nd G. J. G. M. Geelen A fst-settling CMOS p mp fr SC circuits with 90-dB DC gin IEEE Jurnl f Slid-Stte Circuits vl. 5 pp Dec [3] E. Sckinger nd W. Guggenbuhl A high-swing high-impednce MOS cscde circuit IEEE Jurnl f Slid-Stte Circuits vl. 5 pp Feb [4] H. C. Yng nd D. J. Allstt An ctive-feedbck cscde current surce IEEE Trnsctins n Circuits nd Systems vl. 37 pp My [5] P. R. Gry nd R. G. Meyer MOS pertinl mplifier design- tutril verview IEEE Jurnl f Slid-Stte Circuits vl. 17 pp Dec [6] A. A. Abidi On the pertin f cscde gin stges IEEE Jurnl f Slid-Stte Circuits vl. 3 pp Dec [7] P. R. Gry P. J. Hurst S. H. Lewis nd R. G. Meyer Anlysis nd Design f Anlg Integrted Circuits 4th ed. New Yrk: Wiley 001. [8] K. Bult EE15A curse ntes UCLA [9] F. D. Wldhuer Anlg integrted circuits f lrge bndwidth IEEE Interntinl Cnventin Recrd vl. 11 pp prt [10] P. R. Gry nd R. G. Meyer Recent dvnces in mnlithic pertinl mplifier design IEEE Trnsctins n Circuits nd Systems vl. 1 pp My [11] B. Y. T. Kmth R. G. Meyer nd P. R. Gry Reltinship between frequency respnse nd settling time f pertinl mplifiers IEEE Jurnl f Slid-Stte Circuits vl. 9 pp Dec