Asynchronous Sequen<al Circuits

Transcription

1 Asynchrnus Sequen<l Circuits A type f circuit withut clcks (therefre NO flip- flps), ut with the cncept f memry. n The cncept f memry is tined thrugh the use f: ltches nd/r circuit dely nd cmin<nl lps. Asynchrnus sequen<l circuits resemle cmintril circuits with feedck pths. ECE24 Digitl Circuits nd Systems Pge

2 Blck digrm f n synchrnus circuit Nte difference in likle y secndry vriles nd cpitl Y excit<n vriles. Dely elements re hypthe<cl, nd typiclly re result f gte delys. Nte: When inputs chnge, excit<n vriles Y chnge. It tkes ddi<nl dely fr the secndry vriles (current stte) t ssume the vlues f the excit<n vriles (next stte). circuit inputs x current stte (secndry vriles) y n k cmintril lgic dely m k circuit utputs z Y next stte (excittin vriles) ECE24 Digitl Circuits nd Systems Pge 2

3 Defini<ns imprtnt fr synchrnus circuits Stility: n Fr given set f inputs (i.e., vlues), the system is stle if the circuit eventully reches stedy stte nd the excit<n vriles nd secndry vriles re equl nd unchnging (likle y = cpitl Y), therwise the circuit is unstle. Fundmentl Mde Oper4n: n A circuit is per<ng in fundmentl mde if we ssume/frce the fllwing restric<ns n hw the inputs cn chnge: Only ne input is llwed t chnge t <me, The input chnges nly Yer the circuit is stle. ECE24 Digitl Circuits nd Systems Pge 3

4 Asynchrnus circuit nlysis We iden<fy synchrnus circuits y () the presence f ltches (un- clcked strge elements) nd/r (2) cmin<nl feedck pths (lps thrugh lgic gtes). Anlysis invlves tining tle r digrm tht descries the sequence f internl sttes nd utputs s func<n f chnges in the circuit inputs. The tles we will try t tin re trnsi;n tles nd flw tles (mre r less the sme thing s stte tle in synchrnus circuit design). We cn ls use stte digrms t descrie synchrnus circuits. ECE24 Digitl Circuits nd Systems Pge 4

5 Exmple f n synchrnus circuit Cnsider the fllwing circuit tht hs cmintril feedck pths (nd is therefre iden<fied s synchrnus). N pprent ltches in the circuit: Feedck pth is ne in which n utput feeds ck t its wn input (it cretes lp in the circuit thrugh cmintinl lgic) x y2 y Y Y2 z Circuit hs ne input (x), ne utput (z), tw secndry vriles (y, y2) nd tw excit<n vriles (Y, Y2). ECE24 Digitl Circuits nd Systems Pge 5

6 Anlysis (wri<ng lgic equ<ns) Write lgic equ<ns fr the excit<n vriles in terms f the circuit inputs nd secndry vriles: Write lgic equ<ns fr circuit utputs in terms f the circuit inputs nd secndry vriles: ECE24 Digitl Circuits nd Systems Pge 6

7 Anlysis (trnsi<n tle) Using these equ<ns, we cn write trnsi;n tle tht shws excit<n vriles nd utputs s func<n f inputs nd secndry vriles: curr stte y2y next stte x= x= Y2Y Y2Y utput x= x= z z Nte tht stle sttes (secndry vriles equl t excit;n vriles) re circled. ECE24 Digitl Circuits nd Systems Pge 7

8 Anlysis (flw tle) We cn ls crete flw tle, which is just the trnsi<n tle with inry numers replced with symls (e.g., let =, =, c = nd d = ): curr stte y2y c d next stte x= x= Y2Y Y2Y c d c d utput x= x= z z We culd prceed t drw smething like stte digrm frm this infrm<n, if we chse ECE24 Digitl Circuits nd Systems Pge 8

9 Anlysis (flw tle ltern<ve) Anther wy t drw flw tle: x= x= c d,, d, d, c,, c,, LeY- mst clumn shws current stte (secndry vriles), nd the inputs re listed crss the tp. Entries in the mtrix shw the next stte (excit<n vriles) nd utput vlues. ECE24 Digitl Circuits nd Systems Pge 9

10 Primi<ve flw tle Flw tle with nly ne stle stte per rw is clled primi;ve flw tle. x xx2 c c c d d d Primitive Nt primitive ECE24 Digitl Circuits nd Systems Pge

11 Summry f nlysis Prcedure t determine trnsi<n tle nd/r flw tle frm circuit with cmintril feedck pths: n n n n n Iden<fy feedck pths. Lel Y (excit<n vriles) t utput nd y (secndry vriles t input). Derive lgic expressins fr Y (excit<n vriles) in terms f circuit inputs nd secndry vriles. D the sme fr circuit utputs. Crete trnsi<n tle nd flw tle. Circle stle sttes where Y (excit<n vriles) re equl t y (secndry vriles). ECE24 Digitl Circuits nd Systems Pge

12 Revisi<ng ltches Ltches re simply synchrnus circuits. We cn use the previus nlysis technique t see hw ltches wrk. ECE24 Digitl Circuits nd Systems Pge 2

13 Anlysis f n SR ltch () We cn nlyze n SR ltch using the previus technique: R S Y Q y Equ<ns derived fr secndry vrile (sme equ<n fr utput): Since we wnt t vid the SR= situ<n, we cn write: ECE24 Digitl Circuits nd Systems Pge 3

14 Anlysis f n SR ltch (2) Cn derive the trnsi<n tle nd the flw tle: curr stte next stte SR= utput curr stte next stte SR= utput y Y Y Y Y y Y Y Y Y ECE24 Digitl Circuits nd Systems Pge 4

15 Anlysis f n SR ltch (3) Nte: We cn see the undesirle cse when SR= nd inputs chnge. Depending n the vrius delys nd ssuming SR= chnges t SR= n If SR= - > SR= - > SR=, we get stle stte with utput f. n If SR= - > SR= - > SR=, we get stle stte with utput f. S the stle stte is unpredictle. Cnclusin is tht we need t e creful if we (pssily) need t trnsi<n frm ne stte t nther nd we (smehw) pss thrugh stte. ECE24 Digitl Circuits nd Systems Pge 5

16 Anlysis f n S R ltch () We cn nlyze n S R ltch using the previus technique: S R Y Q y Equ<ns derived fr secndry vrile (sme equ<n fr utput): Since we wnt t vid the SR= situ<n, we cn write: ECE24 Digitl Circuits nd Systems Pge 6

17 Anlysis f n S R ltch (2) Cn derive the trnsi<n tle nd the flw tle: curr stte next stte SR= utput curr stte next stte SR= utput y Y Y Y Y y Y Y Y Y ECE24 Digitl Circuits nd Systems Pge 7

18 Anlysis f n S R ltch (3) Nte: We cn see the undesirle cse when SR= nd inputs chnge. Depending n the vrius delys nd ssuming SR=! SR= n If SR= - > SR= - > SR=, we get stle stte with utput f. n If SR= - > SR= - > SR=, we get stle stte with utput f. S the stle stte is unpredictle. ECE24 Digitl Circuits nd Systems Pge 8

19 Asynchrnus nlysis with ltches present () We might hve synchrnus circuits with ltches in them: x R Y y2 S y R2 Y2 x2 S2 We iden<fy tw inputs (x,x2), tw excit<n vriles (Y,Y2), tw secndry vriles (y,y2) nd tw ltches. ECE24 Digitl Circuits nd Systems Pge 9

20 Asynchrnus nlysis with ltches present (2) Since we see ltches, we tin lgic equ<ns fr the ltch inputs: Since we re wrking with ltches, we shuld cnfirm tht the ltches d nt ever enter the undesirle stte (SR= fr NOR, SR= fr NAND). In ur circuit, we hve NOR ltches, s we find: ECE24 Digitl Circuits nd Systems Pge 2

21 Asynchrnus nlysis with ltches present (3) Derive the trnsi<n tle. We need t find the excit<n equ<ns in terms f secndry vriles nd the circuit inputs. T d this, we need t use the ltch equ<ns: ECE24 Digitl Circuits nd Systems Pge 2

22 Asynchrnus nlysis with ltches present (4) Finlly, use equ<ns t derive trnsi<n tle (culd ls find the flw tle): curr stte yy2 xx2 YY2 ECE24 Digitl Circuits nd Systems Pge 22

23 Summry f nlysis when ltches re present Prcedure: n Lel ech ltch utput with Y j nd its feedck pth with y j. n Derive lgic equ<ns fr ltch inputs S j nd R j. n Check f SR= fr NOR Ltches nd S R = fr NAND Ltches. If nt s<sfied, the circuit my nt wrk crrectly. n Crete lgic equ<ns fr ltch utputs Y j using the knwn ehvir f ltch (Y=S+R y fr NOR Ltches nd Y=S +Ry fr NAND Ltches). n n Cnstruct trnsi<n tle using the lgic equ<ns fr the ltch utputs nd circuit stle sttes. Otin flw tle, if desired. ECE24 Digitl Circuits nd Systems Pge 23

24 Asynchrnus circuit design Similr prcedure t synchrnus circuit design, ut with sme dded cmplexi<es due t the synchrnus prt Given verl prlem descrip<n: n Otin primi;ve flw tle (ne stle stte per rw) frm prlem descrip<n. n Reduce the flw tle t get smller flw tle with less sttes. n Perfrm stte ssignment (need t vid rce cndi;ns) t tin trnsi<n tle. n Otin next stte nd utput equ<ns (need t vid hzrds nd glitches). n Drw circuit (with r withut ltches). ECE24 Digitl Circuits nd Systems Pge 24

25 Asynchrnus design exmple Cnsider circuit with tw inputs, D nd G nd ne utput, Q. Output Q fllws D with G=, therwise Q hlds its vlue. n Assume fundmentl mde per<n nly ne input chnges t <me. ECE24 Digitl Circuits nd Systems Pge 25

26 Asynchrnus design exmple (primi<ve flw tle) Nte: Outputs depend nly ne stte (Mre- like): curr stte c d DG= c - c c DG= - next stte DG= DG= e f - e f f e - - e d d - utput Q Nte: Sme unspecified entries due t the fundmentl mde ssump<n (e.g., in stte, DG=, s we never g frm DG= - > DG=) ECE24 Digitl Circuits nd Systems Pge 26

27 Asynchrnus design exmple (reduced flw tle) Fr the mment, ssume tht the fllwing flw tle will ls wrk fr the verl prlem descrip<n ssume (,c,d) nd (,e,f) cn e merged. Originl flw tle: curr stte DG= DG= next stte DG= DG= utput Q c - - e c c d - d c - d e f - e f f e - Reduced flw tle: curr stte DG= next stte DG= DG= DG= utput Q ECE24 Digitl Circuits nd Systems Pge 27

28 Asynchrnus design exmple (stte ssignment nd trnsi<n tle) We nly hve tw sttes, s we cn let =, nd =. Our trnsi<n tle ecmes: curr stte (y) DG= next stte (Y) DG= DG= DG= utput Q ECE24 Digitl Circuits nd Systems Pge 28

29 Asynchrnus design exmple (lgic equ<ns) We cn mke K- Mps t determine excit<n vriles (Y) nd utput (Z) in terms f circuit inputs nd secndry vriles (y): y DG Output equl t the secndry (stte) vrile. ECE24 Digitl Circuits nd Systems Pge 29

30 Asynchrnus design exmple (circuit) Cn finlly drw the circuit: D G Y Q y ECE24 Digitl Circuits nd Systems Pge 3

31 Design with ltches We cn ls implement synchrnus circuits using ltches t the utputs. Given the mp fr ech excit<n vrile Y, derive necessry equ<ns fr S nd R f ltch t prduce Y. Derive Blen equ<ns fr S nd R. n Need t mke sure the S nd R never hve equl (pten<l prlem in Ltch). ECE24 Digitl Circuits nd Systems Pge 3

32 Revisi<ng SR ltches (excit<n tle) Recll hw SR Ltch (NOR) wrks: R (reset) Q S (set)!q Assuming we never hve the SR= cse. Cn write excit;n tle: ECE24 Digitl Circuits nd Systems Pge 32

33 Revisi<ng S R ltches (excit<n tle) Recll n S R Ltch (NAND) wrks: S (set) Q R (reset)!q Assuming we never hve the SR= cse. Cn write excit;n tle: ECE24 Digitl Circuits nd Systems Pge 33

34 Implement<n using ltches Cnsider ur exmple gin, nd ssume we wnt t use S R ltch: y DG Need t figure ut hw t select S nd R fr the NAND Ltch (while mking sure never t sme <me): y DG X X X y DG X X X ECE24 Digitl Circuits nd Systems Pge 34

35 Implement<n using ltches Cn drw the circuit: D G ECE24 Digitl Circuits nd Systems Pge 35