PREDICTED by Moore s law, semiconductor device dimensions

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1 212 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 1, JANUARY 2012 Static and Dynamic Modeling of Single-Electron Memory for Circuit Simulation Wei Xuan, Arnaud Beaumont, Marc Guilmain, Mohamed-Amine Bounouar, Nicolas Baboux, James Etzkorn, Dominique Drouin, and Francis Calmon, Member, IEEE Abstract Two compact models for single-electron memory (SEM) are proposed and validated by comparisons with the program SIMON. The approach is based on the master equation method and the orthodox theory. The specific and efficient algorithms for each model are presented. The first model is static and allows directly calculating the final number of electrons on the memory dot. The second model is dynamic, which evaluates every electron tunnel event to assess the stored charge variation and determines the writing or retention times. Both static and dynamic models are written in Verilog-A language and implemented in IC design framework. These SEM models are attractive for circuit simulation to find out the optimal biasing strategy and memory architecture. Index Terms Coulomb blockade, modeling, single-electron devices (SEDs), single-electron memory (SEM), Verilog-A. I. INTRODUCTION PREDICTED by Moore s law, semiconductor device dimensions are exponentially scaled down, and consequently, the device density and performance have been greatly improved during the last decade. Due to CMOS process variability and leakage current, we will face the limit in dimension reduction, leading to the investigation of alternative technologies. In this context, the domain of single-electron devices (SEDs) [1], where Coulomb blockade [2] plays a principal role and attracts more and more interests. The simplest device to exhibit the effect of Coulomb blockade is the single-electron transistor (SET). SETs show interesting characteristics such as very low power consumption (based on very low current), large density of integration, and high sensitivity that allows the detection of a single charge. At present, there are several validated SET simulators, for example, SIMON [3] and MIB [4]. Manuscript received March 19, 2011; revised September 27, 2011 and October 17, 2011; accepted October 17, Date of publication November 23, 2011; date of current version December 23, This work was supported in part by the French National Agency ANR (Project SEDIMOS, no. ANR-09-BLAN-0411-CSD1) and in part by the Natural Sciences and Engineering Research Council of Canada NSERC (STPGP ). The review of this paper was arranged by Editor M. A. Reed. W. Xuan, A. Beaumont, N. Baboux, J. Etzkorn, and F. Calmon are with the Lyon Institute of Nanotechnology, University of Lyon, INSA-Lyon, Villeurbanne Cedex, France ( francis.calmon@insa-lyon.fr). M. Guilmain and D. Drouin are with 3IT-CRN2, Department of Electrical and Computer Engineering, Université de Sherbrooke, Sherbrooke, QC J1K 2R1, Canada ( dominique.drouin@usherbrooke.ca). M.-A. Bounouar is with the Department of Electrical and Computer Engineering, Université de Sherbrooke, Sherbrooke, QC J1K 2R1, Canada, and also with the Lyon Institute of Nanotechnology, University of Lyon, INSA-Lyon, Villeurbanne Cedex, France. Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TED Fig. 1. SEM architecture. Floating memory point is added between the SET central island and the gate (the memory island can be charged through the tunnel junction between the two dots). The three most used methods for SET modeling are Monte Carlo [3], master equation [5], and macromodeling methods [6]. Additionally, a mathematical method has been proposed to simulate SETs [7]. Recently, a realistic metallic SET model has been introduced by Dubuc et al. [8], with a specific contribution on the calculation of thermionic current and tunnel resistance. Dubuc et al. extended the SET model validity at room temperature up to 430 K. SET circuits are also widely studied for digital and analog applications. Some low complexity structures have been reported [9] [11]. The impact of circuit parameters of SETs have been also analyzed [12] [14]. Based on the research focused on MOSFET-SET circuits, it seems difficult for a real SET to reach industry requirements due to its high resistance [15]. Therefore, a more prospective application for SEDs may be the single-electron memory (SEM). SEM architectures benefiting from the Coulomb blockade have already been proposed. They all consist of a single-electron box to store information, but some of them use MOSFETs to read it [16], [17], whereas others use only SETs in that role [3], [18], [19]. Other works address the SEM fabrication based on multiple silicon dots with a detailed analysis of the dot charging and discharging [20], [21]. Recently, a metallic SET process developed at Université de Sherbrooke [22], [23] has proved the feasibility of roomtemperature operation. In the prospect of extending this process to SEM fabrication, we propose to study the classical SEM architecture depicted in Fig. 1 by simulation. Among available tools, stand-alone Monte Carlo simulators are suitable to simulate the characteristics of simple circuits composed only of SEDs, but they are not compatible with circuit design environments [3], [18], [24]. To circumvent this issue, several research teams have attempted to propose compact models, first with strong approximations [25], [26]. Later, Kirihara et al. have /$ IEEE

2 XUAN et al.: STATIC AND DYNAMIC MODELING OF SEM FOR CIRCUIT SIMULATION 213 Fig. 2. Simplified schematic of SEM. published a more advanced simulator compatible with circuit design environments named as CAMSET [27]. It is based on the resolution of the master equation but appears not suitable to simulate long retention times commonly found in nonvolatile memory devices. To reach this goal, a compact model has been developed and is described in this paper. Section II details the electron storage in the floating island and emphasizes the retention enhancement due to Coulomb blockade in nanostructures. Section III will focus on the modeling methodology of the SEM architecture. First, a static model will be introduced, allowing us to determine the steady state number of electrons on the floating island. Second, a compact dynamic model is presented featuring the transient analysis of the charge evolution with time during writing, retention, or erasing phases. These models, based on the master equation approach, are implemented in a standard IC simulation platform, allowing the SEM state to be dynamically analyzed with various voltage strategies. Finally, we summarize the main results and point out the advantages to use these two models to complement each other. Fig. 3. Evolution of the charge on the floating island simulated by SIMON. R dc = Ω, R cs = Ω, R fc = Ω, C dc = 0.01 af, C cs = 0.02 af, V ds = 0V,T = 77 K. floating island varying C gf, from 100 to 5 af with the same ratio C gf /C fc (Fig. 3 obtained with SIMON program [3]). We found that reducing the device size will considerably increase its retention time, which is far beyond the limits of Flash. We will show in this section that it is the Coulomb blockade that preserves electrons resting on the floating island. From a pure electrostatic analysis, we obtain V dc + V cs = V ds (1) V gf + V fc + V cs = V gs (2) V fc C fc V gf C gf = N f e (3) V cs C cs V dc C dc V fc C fc = N c e (4) E p = 1 ( Cdc V 2 2 dc+ C cs Vcs+ 2 C fc Vfc+ 2 C gf Vgf 2 ) (5) E s = V ds I d dt + V gs I g dt. (6) II. ANALYSIS OF THE COULOMB BLOCKADE IN A SEM ARCHITECTURE If the size of traditional Flash memory devices keeps reducing, the capacitance relative to the storage node will dramatically decrease and will approach the memory architecture presented in Fig. 1. Therefore, it is even more important to study the impact of Coulomb blockade, since it may affect the two islands of the structure, particularly impacting the retention time compared with larger structures. In our model, each tunnel junction is described by two parameters, namely, capacitor and resistance (see Fig. 2). C dc (R dc ) is the equivalent capacitor (resistance) of the tunneling junction connecting the central island to the drain, whereas C cs (R cs ) refers to the tunneling junction connecting the central island to the source, and C fc (R fc ) refers to the tunneling junction connecting the central island to the floating island. C gf is the equivalent capacitor of the nontunneling junction connecting the floating island to the control gate. Correspondingly, V dc (V cs V fc V gf ) is the voltage across the junction. N c (N f ) is the electron number of the central (floating) island. At present, capacitors in the conventional Flash memory are in the order of some ten attofarads [28]. We compared the charge retention in the Here, e = is the elementary charge, I d (I g ) is the electrical current through the drain (gate), E p is the system potential energy, and E s is the electrical source works. The equations allow us to obtain V dc (V cs, V fc, V gf, E p, and E s ) as a function of V ds, V gs, N f, and N c. The change in Gibb s free energy of the system during tunneling (ΔE) is used to determine whether an electron will pass across any tunneling junction. ΔE is determined taking into account the variations of potential electrostatic energy ΔE p and the works of electrical sources ΔE s :ΔE =ΔE p ΔE s. ΔE c f is the change in Gibb s free energy when an electron crosses the floating junction from the central to the floating island (N c N c 1,N f N f + 1) and ΔE f c when an electron tunnels reversely (N c N c + 1,N f N f 1). Thus ΔE c f = e V fc e 2 1 (7) c + c gf 2 gf +c gf 1 ΔE f c = e V fc e 2 + c gf c 2 gf +c gf. (8)

3 214 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 1, JANUARY 2012 An electron will tunnel only when the change in Gibb s free energy is negative. Then, we define voltage threshold V threshold_fc V threshold_fc = e 2 1 > 0. (9) c + c gf 2 gf +c gf From (7) (9), the Coulomb blockade condition for the floating junction can be written as V fc <V threshold_fc. (10) Now, we pay more attention to the number of electrons that will remain on the floating island after we cut off the electrical sources (V ds = V gs = 0). In this case, V fc can be simplified as V fc = e [c gf N c (c cs + c dc )N f ] c cs + c dc + c cs c gf + c dc c gf + c gf. (11) Both the central and floating islands reach a stable state. From (9) (11), we obtain (12), which illustrates the Coulomb blockade condition of the floating island. Thus c gf N c (C dc + C cs ) N f < c dc + c cs + c gf. (12) 2 SEM can be treated as a SET when there is no electron tunneling across the floating junctions. As V ds = V gs = 0, the potential difference through the drain (source) V dc (V cs ) can be simplified as V dc = V cs = e [ N f +( + c gf )N c ]. c cs + c dc + c cs c gf + c dc c gf + c gf (13) Furthermore, the changes in Gibb s free energy with the change of the number of electrons on the central island when N f is constant ΔE Nc N c ±1 are given as e ΔE Nc N c +1 = e + V dc (14) 2C c_σ e ΔE Nc N c 1 = e + V dc. (15) 2C c_σ Here, C c_σ = C dc + C cs +(1/(1/C fc )+(1/C gf )) can be regarded as the total capacitance seen from the central island. Therefore, in order to have no electron tunneling between the central island and the drain or source, we have V dc < e. (16) 2C c_σ From (13) (16), we obtain the Coulomb blockade condition of the central island as N 1 c c N gf f < 1 2. (17) Equations (12) and (17) are the Coulomb blockade conditions for SEM when V ds = V gs = 0. Through mathematical derivations (see Annex A), we found that N c can only be zero to meet the two inequalities. Therefore, the Coulomb blockage Fig. 4. Evolution of N f_ max and ΔE(N f )/k B T. C dc = 0.01 af, C cs = 0.02 af, C gf /C fc = 208 and C gf from 0.5 to 100 af, T = 77 K. condition can be simplified and, the maximum number of electrons resting on the floating island N f_ max is given by { ( 1 c gf N f_ max =floor min 2 ( ) ; 1 c gf + 1 )}. (18) 2 2 Here, min(x, y) is the smaller value between x and y; floor(x) is the largest integer not greater than x. Fig. 4 illustrates (18), showing the N f_ max evolution function of C gf with a constant ratio C gf /C fc = 208 as in Fig. 3. We can clearly observe that N f_ max will be limited to the maximum constant value C gf /2C fc with the increase of C gf (C fc ). Additionally, we represent in Fig. 4 the energy change ΔE(N f )/(k B T ) when an electron leaves the floating island where there are N f electrons This figure shows the stability of N f electrons state on the floating island under the temperature influence. The greater this value, the steadier is the state. We ignore the high order of possible tunnels and consider only two possible basic paths, i.e., {N f,n c =0} ΔE 1 {N f 1,N c =1} ΔE 2 {N f 1,N c =0} {N f,n c =0} ΔE 3 {N f,n c = 1} ΔE 4 {N f 1,N c =0}. Considering each path, the largest positive value of ΔE will limit the tunneling through this way. Then, to take into account the most probable path and determine the energy change, we extract ΔE(N f ) = min{max(δe 1, ΔE 2 ); max(δe 3, ΔE 4 )}.From Fig. 4, we clearly show that ΔE(N f )/k B T is increasing when reducing the structure size (C gf and C fc ), leading to higher stability and higher retention time. Additionally, ΔE(N f )/k B T is increasing when N f decreases. We may observe that N f_ max is very unstable even at very low temperature. However, the system will become stable with the loss of an electron, as illustrated in Fig. 4 showing the increase of ΔE(N f_ max 1) compared with ΔE(N f_ max). Two examples of these results are validated by SIMON (see Fig. 5) with C dc = 0.01 af, C cs = 0.02 af, and C fc = af. If C gf = 0.5 af, N f_ max will be 8, and if C gf = 5aF,N f_ max will be 83. We point out that this study, which is totally based on a basic electrostatic analysis, is correct at low temperature without thermal effect. In fact, we might observe a tunnel occurring at relatively high temperature even when ΔE >0.

4 XUAN et al.: STATIC AND DYNAMIC MODELING OF SEM FOR CIRCUIT SIMULATION 215 Fig. 5. Electrons on the floating island simulated by SIMON with C dc = 0.01 af, C cs = 0.02 af, C fc = af, V ds = 0; (a) C gf = 0.5 af, (b) C gf = 5aF,T = 77 K. This electrostatic analysis shows that the SEM architecture presented in Fig. 1 with a tunnel junction between the central and floating islands is able to store a predictable number of charges on the floating island due to Coulomb blockade, as illustrated in Fig. 4 We can see that the Coulomb blockade is enhanced when reducing the capacitance (structure size). Therefore, reducing the conventional Flash memory size to introduce Coulomb blockade as in SEM architecture will improve the retention time. The following section will detail our modeling methods and their validation. III. MODELING OF SEM A. Introduction In this section, we present the compact modeling (semianalytical) for the specific SEM architecture (presented in Fig. 1) in Verilog-A language and compatible with IC simulators (SPICEbased). Basically, we use the master equation approach [5] in our steady state and dynamic SEM model to calculate the probabilities from the tunneling rates, but we only consider a limited set of possible events linked to the target SEM architecture, allowing us to propose a compact algorithm that can be efficiently implemented. The main advantage of the developed SEM models, which are validated with SIMON reference program [3], is that they can be used at IC circuit level in a hybrid SEM-CMOS circuitry (see Annex B). B. Static Model The static SEM model is used to obtain the final number of electrons on the floating island for a given voltage biasing (at equilibrium). First based on the previous electrostatic analysis, we calculate the change in Gibb s free energy of the system during tunneling (ΔE) for six possible single-electron tunneling events. Charge e can tunnel across the drain junction (see Fig. 2) from the drain to the central island with the energy variation ΔE d c and ΔE c d in the opposite direction. Additionally, we define ΔE c s and ΔE s c for the electron tunneling across the source junction (between the central island and the source), whereas ΔE c f and ΔE f c are for the electrons tunneling across the floating junction (between the central and floating islands). Then, through Fermi s golden rule, we obtain all the tunneling rates Γ. Thus Γ= 1 e 2 R ΔE ( exp ΔE k B T ). (19) 1 Here, R is the tunnel resistance, k B is Boltzmann s constant, and T is the temperature. Referring to what we discussed at the end of part II, with a relatively small ratio ΔE/(k B T ), Γ might be large enough so that an electron tunnel event will be observed even when ΔE >0. The central island comes to a balance when there is current between the drain and source electrodes. Therefore, we have P c (N c ) [Γ d c (N c )+Γ s c (N c )] = P c (N c + 1) [Γ c d (N c + 1)+Γ c s (N c + 1)]. (20) Here, P c (N c ) is the probability to find N c electrons on the central island. In the same way, as far as the floating island is concerned, we have (21), shown at the bottom of the page. Here, P f (N f ) is the probability to find N f electrons on the floating island. P c (N f,n c ) is the probability to find N c electrons on the central island when there are N f electrons on the floating island. B nopt is the most possible electron number on the central island when there are N f electrons on the floating island. SN is the maximum electron number considered on the central island. Supposing BN is the maximum electron number considered on the floating island, based on (20) and (21), we obtain the final number of electrons on the floating island as Num = N f =+BN N f = BN (P f (N f ) N f ). (22) Moreover, we obtain the current flowing through the drain to source as (23), shown at the bottom of the page. P f (N f ) P f (N f + 1) = [ Nc =B nopt +SN ] N c =B nopt SN P c(n f + 1,N c ) Γ f c (N f + 1,N c ) [ Nc ] =B nopt +SN N c =B nopt SN P c(n f,n c ) Γ c f (N f,n c ). (21) I ds = e N f =+BN N f = BN P f (N f ) N c =B nopt +SN N c =B nopt SN [P c (N f,n c ) (Γ d c ((N f,n c ) Γ c d (N f,n c ))]. (23)

5 216 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 1, JANUARY 2012 Fig. 7. Comparison of our static model with the program SIMON. R dc = Ω, R cs = Ω, R fc = Ω, C dc = 0.01 af, C cs = 0.02 af, C fc = af, C gf = 0.5 af, V gs = 3V. Fig. 6. Algorithm used in the static SEM model. The Verilog-A implementation of the static SEM model follows the flowchart presented in Fig. 6. We have compared the results of our static model with the program SIMON in Fig. 7. The comparison shows that our algorithm is correct, and our model is precise. Based on the static model, we directly obtain the final number of electrons on the floating island. This model ignores the details of the discrete tunnel events. In order to evaluate the writing/retention times and the evolution of electron number in the floating island, we developed a dynamic model to include the charge trapping process. C. Dynamic Model The dynamic SEM model allows simulating the electron tunnel events and obtaining the evolution of number of electrons on the floating island with time. In a dynamic simulation, it is essential to estimate the necessary time for a transition to take place. Through taking the inverse of the Poisson distribution, we get the time τ at which a tunnel event out of state 0 happens, i.e., τ = ln γ Γ. (24) Here, γ is an evenly distributed random number [29] from the interval [0 1], and Γ is the tunneling rate. The main point is to dynamically control the simulator time step function of τ values. For each simulation cycle (time step), as depicted in Fig. 8, the dynamic model evaluates the floating island charge change by: i) calculating the changes in Gibb s free energy and associated tunneling rates (from the source or drain to the central island, between the central and floating island; in both directions); ii) calculating the central island occupation probabilities; iii) determining the most probable event between the central and floating islands, as described below; and iv) updating the number of electrons on the floating island for the next cycle. What follows are the main steps used to determine the most probable event between the central and floating islands (see Fig. 8). 1) Input the electron number N f_n on the floating island for this cycle (No. n). 2) Calculate the tunneling rate Γ c f for the electron flow from the central island to the floating island and the tunneling rate Γ f c for the electron flow from the floating island to the central island. 3) Calculate the time for each tunnel event, t c f = (ln γ 1 /Γ c f ) and t f c = (ln γ 2 /Γ f c ). 4) Determine which tunnel event will probably occur. T step is the maximal time step during the transient simulation, i.e., between two successive points calculated by the simulator (e.g., Spectre); the time difference is less than this time step. 4.a. If t c f <T step, N cf = 1 to describe this situation; otherwise, N cf = 0. 4.b. If t f c <T step, N fc = 1 to describe this situation; otherwise, N fc = 0. 5) Determine which tunnel event will finally occur and the related waiting time t waiting. 5.a. If N cf = 0 and N fc = 0, no tunnel event will happen during this cycle. The next cycle valuation will occur in t waiting = T step and for the next simulation cycle N f_n+1 = N f_n. 5.b. If N cf = 1 and N fc = 0, an electron will tunnel from the central to the floating island in this cycle. Therefore, the next time step is forced when

6 XUAN et al.: STATIC AND DYNAMIC MODELING OF SEM FOR CIRCUIT SIMULATION 217 Fig. 8. Algorithm used in the dynamic SEM model. t waiting = t c f and for the next simulation cycle N f_n+1 = N f_n c. If N cf = 0 and N fc = 1, an electron will tunnel from the floating to the central island in this cycle. Therefore, the next time step is forced when t waiting = t f c and for the next simulation cycle N f_n+1 = N f_n 1. 5.d. If N cf = 1 and N fc = 1, that is to say, during our preliminary selection, both tunnels will probably occur. We suppose that the two tunnels are independent. Based on their occurring time, we determine which tunnel event will occur. 6) Terminate this cycle and enter to the next simulation cycle (No. n + 1). The above methodology describes the outline of the algorithm as represented in Fig. 8. In the model implementation, we use a time step-changing strategy. At the beginning, we initialize T step with a very small value as tunneling time is small. With the increasing of tunneling times, we increase T step as well in order to reduce the simulation duration. We have compared the simulation results of our dynamic model (implemented in Verilog-A language) with the program SIMON in Fig. 9. Based on 100 transient simulations, we statistically analyze the tunnel event time that proves our model. From Fig. 9, both with SIMON and our model, we observe that the 1st tunnel event has a 90% chance of occurring before 4.5 ns, the 2nd tunnel event has a 95% chance of occurring before 16 ns, and the 3rd tunnel event has a 90% chance of occurring before 450 ns. D. Analysis As in SET modeling, we use the master equation in our static SEM model. We directly deal with steady states ignoring discrete tunnel events. In the dynamic SEM model, we use our own algorithm to simulate the dynamic change of electron number on the floating island. Both two models complement each other. Fig. 9. Comparison of simulation results of our dynamic model with SIMON. R dc = Ω, R cs = Ω, R fc = Ω, C dc = 0.01 af, C cs = 0.02 af, C fc = af, C gf = 0.5 af, T=300 K, V ds = 2V, V gs = 3V. We can verify whether the dynamic model converges to the final state obtained by the static model. The number of electrons on the memory island obtained with the static model is presented in Fig. 10 with V ds = 2.5 V. For example, the value of the final charge curve at V gs = 3.5 V in Fig. 9 at 300 K is not an integer, the steady state electron number is about 5.5. The reason is shown in Fig. 11, which presents the dynamic change of electron number on the floating island with constant biasing voltages V ds = 2.5 V and V gs = 3.5 V. We observe that, at the end of the transient simulation (end time > 10 μs), the electron number varies between 5 and 6. Sometimes, after obtaining six electrons on the floating island, another electron may also leave from the floating island, but the coming state (five electrons) is not stable. An extra electron will quickly arrive. From the static simulation in Fig. 10, we should finally find five electrons on the floating island at 30 K. However, in Fig. 11, there are only four electrons on the floating

7 218 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 1, JANUARY 2012 Fig. 10. Static simulation of our model and SIMON. R dc = Ω, R cs = Ω, R fc = Ω, C dc = 0.01 af, C cs = 0.02 af, C fc = af, C gf = 0.5 af, V ds = 2.5 V. Fig. 12. Electron changes in the floating island following the change of V ds and V gs simulated by our model and SIMON. R dc = Ω, R cs = Ω, R fc = Ω, C dc = 0.01 af, C cs = 0.02 af, C fc = af, C gf = 0.5 af. Fig. 11. Dynamic simulation of our model and SIMON. R dc = Ω, R cs = Ω, R fc = Ω, C dc = 0.01 af, C cs = 0.02 af, C fc = af, C gf = 0.5 af, V ds = 2.5 V, V gs = 3.5 V. island at the end of the simulation. That is because the static model directly gives the stable state, whereas in Fig. 11, the final tunneling event needs more than 100 μs to occur at 30 K. As our dynamic SEM model has been implemented in an IC design framework in Verilog-A language, one can simulate the floating charge variation with any biasing. Fig. 12 shows the variation of the electron number on the floating island at low and high temperatures with the change of external voltage biasing. High temperature makes it easier for electrons to tunnel and has influence on final states. At 30 K, eight electrons stay on the floating island after V ds and V gs become 0, which agree with our analysis in Fig. 5 and (18). However, at 300 K, we can also observe another tunnel event, as discussed previously. E. Impact of Tunnel Junction Resistance and Gate Capacitance on the SEM Charging The dynamic SEM model in a SEM-CMOS circuit allows the transient variation of the stored charge to be analyzed as a Fig. 13. Charge time to reach 200 electrons on the floating island function of tunnel junction resistance R fc and gate capacitance C gf. R dc = Ω, R cs = Ω, C dc = 0.01 af, C cs = 0.02 af, C fc = af, V gs = 6V,V ds = 3V,T = 300 K. function of the biasing strategy and therefore extracting timing characteristics, namely, the time needed to reach a certain number of electrons (writing speed) and the time to lose half of the stored charge under zero-voltage biasing (retention time). Furthermore, the reading of SEM cell can be studied at circuit level. An exhaustive parametric study is a huge work, thus, we only illustrate the efficiency of the dynamic SEM model evaluating the impact of tunnel junction resistance R fc and gate capacitance C gf on the SEM charging. To carry out this study, 100 simulations were ran for each set of parameters (R fc,c gf ), with each simulation being executed with a different seed in the random number generator. The average maximum number of electrons reached on the floating island has been extracted as a function of R fc and C gf. We noted that the number of electrons dramatically increases with C gf but only slightly changes with R fc. This is because the total number of charges on the floating island is an electrostatic calculation that does not depend on the tunnel resistance. Fig. 13 shows the time it takes to reach 200 electrons on the floating island. We observe that the average time it takes to reach 200 electrons on the floating island increases with R fc

8 XUAN et al.: STATIC AND DYNAMIC MODELING OF SEM FOR CIRCUIT SIMULATION 219 and decreases with C gf. The reason for the change in charging time with respect to R fc can be explained by the equation for the tunneling rate (19). As R fc increases, the tunneling rate decreases, and therefore, it will take a longer amount of time to reach a given number of electrons. The explanation for the change in charge time with respect to C gf is not as obvious. There are two capacitors between the gate and the central island. This creates a voltage divider. As C gf increases and C fc remains constant, the voltage across the tunnel junction V fc increases. Since the change in free energy decreases as the voltage across the junction increases, based on (7), the tunneling rate increases. Therefore, the time it takes to reach a given number of electrons is lower. IV. CONCLUSION Based on the electrostatic analysis of the SEM architecture, we have verified the benefit of the Coulomb blockade when reducing the device size. A simple formulation is demonstrated to predict the charge on the floating island function of the SEM capacitance values with zero-voltage biasing. The energy change related to a charge lost from the floating island is increasing when reducing the SEM size, leading to higher charge stability and retention time. Then, we presented compact modeling (semianalytical) for a specific SEM architecture (static and dynamic models) based on the master equation approach. We consider the memory point is charged and discharged by electron tunnel events from the central island of the SET, which is also used to sense the stored information. The static model allows us to determine the steady state number of electrons on the floating island, whereas the dynamic model features the transient analysis of charge evolution with time during writing, retention, or erasing phases. These models have some clear advantages: i) the principle is simple, which is just based on the orthodox theory; ii) they can precisely predict the storage information and the current through the drain and the source; and iii) they are implemented in Verilog-A and can be used in a circuit design framework to study the whole memory circuit with any biasing strategy. In addition, our models can be easily improved to take the thermal effect into account to accurately describe the device behavior at room temperature. Based on these results, parametric analysis will be performed to determine the optimal dimensions and materials leading to a tradeoff between retention and writing times. APPENDIX A ANNEX A: ELECTRON NUMBER OF THE CENTRAL ISLAND (N c ) CALCULATION Equations (12) and (17) can be written as system of inequalities (25) c gf N c N f < 1 cgf cgf < c gf N c N f. (25) 1 + c gf N c + N f < c gf 1 2 ( 1 + c gf ) < 1 + c gf N c + N f Through merging like terms, we can eliminate N f and get the conditions for N c as (26) cgf + c gf + N c < 1 2 cgf + c gf ( 1 2 cgf + c gf < cgf + c gf + ) N c. (26) Finally, we get a system of inequalities concerning N c in (27) N c < < 1 c gf c dc +ccs + c gf c +1 fc 1 < <N. (27) c gf c dc +ccs + c gf c c +1 fc From (27), considering that N c can only be integer, we can conclude that N c can only be zero to meet the two inequalities (12) and (17). APPENDIX B ANNEX B: SEM MODEL IMPLEMENTATION The SEM models implemented in Verilog-A language are compatible with standard IC simulators (SPICE-based). The codes are available on the following link: REFERENCES [1] K. Likharev, Single electron devices and their applications, Proc. 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Marc Guilmain was born in Québec, Canada, in He received the electrical engineering diploma from the Université de Sherbrooke, Sherbrooke, Canada, in 2008, where he is currently working toward the Ph.D. degree in the fabrication and simulation of nanoelectronic devices. Mohamed-Amine Bounouar received the B.Sc. and M.Sc. degrees in microelectronics system design from the University of Montpellier 2, Montpellier, France, in 2007 and 2009, respectively. He is working toward the Ph.D. degree in the field of nanoelectronic design jointly with the Department of Electrical and Computer Engineering at the Université de Sherbrooke, Sherbrooke, Canada, and with the Lyon Institute of Nanotechnology, University of Lyon, INSA-Lyon, Villeurbanne, France, since His research interests include circuit design based on emerging technologies. Nicolas Baboux, photograph and biography not available at the time of publication. James Etzkorn, photograph and biography not available at the time of publication. Dominique Drouin received the bachelor s degree in electrical engineering and the Ph.D. degree in mechanical engineering from the Université de Sherbrooke, Sherbrooke, Canada, in 1994 and 1998, respectively. Since 1999, he has been a Professor at the Université de Sherbrooke. His research interests include nanoelectronic devices such as single-electron transistor, single-electron memory, and memristor implanted on CMOS integrated circuit, particularly process development, modeling, and electrical characterization. He is co-director of the Interdisciplinary Institute for Technological Innovation (3IT) at Université de Sherbrooke. Wei Xuan was born on January 20, He received the B.S. and M.S. degrees in electronics from Jilin University, Changchun, China, in 2004 and 2007, respectively, and the Ph.D. degree from INSA-Lyon, Lyon, France, in He is currently with the Lyon Institute of Nanotechnology, University of Lyon, INSA-Lyon. His current research interests include nanoelectronic device simulation and fabrication. Francis Calmon (M 09) was born in Cahors, France, in He received the Engineering diploma and the Ph.D. degree in 1992 and 1995, respectively. He is a Professor at INSA Lyon and a Researcher attached to the Lyon Institute of Nanotechnology, University of Lyon, INSA-Lyon, Villeurbanne, France. His fields of interests are the modeling, the design, and the characterization of mixed and RF IC s, with a particular emphasis on the use of emerging nanodevices and signal integrity issue.