University of Southern California School Of Engineering Department Of Electrical Engineering

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1 University f Suthern Caifrnia Sch Of Engineering Department Of Eectrica Engineering EE 448: Hmewrk Assignment #0 Fa, 200 ( Assigned 08/27/0; Due 09/0/0) Chma Prbem #0: Wideband anag and high-speed digita integrated circuits necessariy use minima gemetry transistrs whse sma breakdwn vtages precude their capabiity t sustain arge cectr-emitter (r drain-surce) vtages ver even reativey sma time perids. T prtect these devices frm transient vtage verstress, a secnd rder LC fiter f the frm shwn in Fig. (P) is ften inserted between the ON/OFF pwer ine switch and the pwer suppy pad f the integrated circuit. In this circuit, R represents the steady state ad t which pwer is t be suppied and is nminay the rati f the steady state ad vtage -t- the steady state ad current. Thus, if the desired quiescent pad vtage f an integrated circuit is 3.3 vts and if this circuit is t draw a quiescent current f 2 ma, R = 3.3/2 ma = 275 Ω. The fiter itsef cnsists f the inductance, L s, which incudes any parasitic inductance assciated with the pwer suppy bus ine ruting n chip, and the capacitance, C, which incudes parasitic pwer suppy pad capacitance. The resistance, R s is generay sma and incudes the effects f pwer bus sses and finite inductance quaity factr (Q). By the way, the rubberized r pastic-cated bump yu see in the pwer ine that cnnects yur aptp cmputer t an energy surce is the inductance in Fig. (P). The indicated vtage, V p is the Thévenin energizing vtage fr the chip, whie the switch, which is csed at time t = 0, aws the fiter input vtage, v i (t), t emuate the step functin, V p u(t). It is t be understd that the fundamenta purpse f the fiter is t sw the rate f pwer deivery frm the input prt, where v i (t) is measured, -t- the utput prt, where vtage v (t) is estabished, s that v (t) rises mntnicay with time tward its steady state vaue with itte r n vtage versht. i t = 0 + V p Rs L s R C Fig. (P) (a). The fiter in Fig. (P) is ceary a secnd rder circuit. In view f the discussin prvided abve, shud the circuit pes, whse frequencies might be abeed, p and p 2, be rea numbers r cmpex cnjugates? Briefy expain yur ratinae.

2 (b). Derive an expressin fr the transfer functin, H(s) = V (s)/v i (s) and in the prcess, shw that the pe frequencies satisfy the reatinships, L s + = + ( R R s ) C p p R + R 2 s and R = LC = H(0)LC. s s p p R + R 2 s (c). Assume that the pes are rea and that their frequencies reate as p 2 = kp, where k is understd t be greater than r equa t ne. Fr k >, shw that the time dmain respnse, nrmaized t the steady state vaue f the respnse, is k p t kp t v (t) = = e e n +, H(0)V k k p whie fr k =, cnfirm that p t v (t) = = n ( + p t ) e. H(0)V p (d). Pt the nrmaized respnses determined in Part (c) -versus- the nrmaized time parameter, t n = p t fr k =,.5, 3, and 0. What vaue f k might be desired t ensure the reaizatin f the swest pssibe step respnse fr any given rea number vaue f p? (e). Let T R represent the rise time f the fiter; that is, T R is the time required after the switch is csed fr the utput respnse t achieve 90% f its steady state vaue. Fr the ptima vaue f k (in the sense f a maximay swed respnse) determined in Part (d), cnfirm that p T R 3.9. (f). Assume nw that R >> R s and L s >> R s R C. Fr the ptima perating cnditin stipuated in Part (e), shw that a rise time f T R is achieved if ( + ) T R R R s L s.95 and T C R. 7.8R (g). Assume that a certain integrated circuit is t be energized by a 3.3 vt battery that is switched n at time t = 0. Assume further that the net effective Thévenin surce resistance (R s ) is 5 Ω and that the effective steady state ad resistance (R ) is 020 Ω. The atter resistance crrespnds nminay t 3.3 vts deivered t a ad drawing 3.23 ma. A 0 - t- 90% rise time (T R ) f at east 200 µsec is desired t prtect the active devices in the given circuit. Design the prtectin fiter and simuate it n SPICE t cnfirm the stipuated rise time bjective. Prbem #02: The tw transistrs in the simpe ampifier f Fig. (P2) are minimum Hmewrk #0 2 Fa Semester, 200

3 gemetry devices manufactured in a cmmerciay avaiabe siicn-germanium heterstructure prcess. This particuar transistr deivers an ptima gain-bandwidth prduct (f T ) f the rder f 55 GHz when it is biased at a cectr current f.6 ma and a cectr -t- emitter vtage f.6 vts. At this perating pint bjective, V BE is abut 822 mv, and h FE is apprximatey 07. +V CC R R CC Q Q2 R 2 R E Fig. (P2) (a). Design the biasing circuit with V CC = 3.3 vts and R E = 50 Ω. Aw the tw transistrs t cnduct nminay identica cectr currents. (b). Simuate the circuit n SPICE using the (reaistic) SPICE parameters itemized bew. If necessary, adjust the biasing eements t ensure that transistr Q perates very near its cectr current and cectr-emitter vtage ptimum. At this quiescent perating pint, nte and recrd the w frequency sma signa parameters (base resistance r b, base-emitter diffusin resistance r π, Eary resistance r, current gain β ac, interna emitter resistance r e, and interna cectr resistance r c ) f each transistr. As, recrd fr use in the subsequent prbem the static current suppied t the circuit by the V CC pwer suppy. Prbem #03: SPICE PARAMETERS - MINIMAL GEOMETRY NPN SiGe TRANSISTOR IS = e-8 amps EG =.8 vts BF = 35 NF = VAF = 20 vts IKF = 6.5 ma ISE = fa NE = 2.34 BR = 0. NR = VAR = 800 vts IKR = 50 µa ISC = 490e-2 amps RB = Ω RBM = 3.2 Ω IRB = µa RE = 3.6 Ω RC = 62.9 Ω CJE = 25.4 ff VJE =.2 vts MJE =.4 CJC = 4.5 ff VJC = 0.78 vts MJC = XCJC = 0.39 CJS = 8.9 ff VJS = 0.80 vts MJS = 0.50 FC = 0.9 TF =.78 psec TR = 0.0 psec XTF = 0 VTF =.8 vts ITF = 30 ma XTB =.5 KF =.0e-2 CN = 2.42 D = 0.87 AF =.0 XTI = 3.0 NC = 2.0 The purpse f this prbem is t examine the effectiveness f the fiter studied in Prbem #0 n the biasing circuit examined in Prbem #02. Hmewrk #0 3 Fa Semester, 200

4 (a). First, suppant the V CC battery by a zer -t- 3.3 vts puse wavefrm whse puse width is perhaps a nansecnd and whse perid is as ng as 4 nsec. T avid SPICE cnvergence prbems, et this puse have 2 psec rise and fa times. Simuate the resutant circuit n SPICE and examine the vtage, v ce (t) deveped acrss the cectr -t- emitter terminas f transistr Q. What prbems d yu see reative t precuding breakdwn, which ccurs fr this transistr at a cectr-emitter vtage f apprximatey 2.3 vts? Might yu be abe t ratinaize, abeit quaitativey, the bserved prbems in terms f the time dmain vtage, v be (t), deveped acrss the base -t- emitter terminas f Q? (b). Nw use the fiter t generate the pwer ine vtage, V CC = 3.3 vts in the steady state. Design the fiter fr a rise time f 200 µsec, and adjust the ampitude f vtage V p s that V CC is indeed nminay 3.3 vts in the steady state. Test yur design n SPICE t ensure that the ptimum quiescent perating pint is achieved under steady state perating circumstances. Examine the resutant wavefrm, v ce (t), and cmpare the resut with that bserved in Part (a). Des the fiter d its jb in the sense f precuding vtage breakdwn? Prbem #04: A signa surce, v s, whse Thévenin resistance is R s, is appied thrugh a cuping capacitr, C c, t the ampifier whse bias circuit has been designed in Prbem #02. The resutant utput signa respnse is extracted as v, as is depicted in Fig. (P4). (a). What purpse is served by the cuping capacitr, C c? (b). Use the parametric resuts btained in Prbem #02b t derive an expressin fr the driving pint input resistance, R in. Fr simpicity, ignre a Eary resistances. (c). Seect capacitance C c s that it emuates an AC shrt circuit fr signa frequencies abve 50 MHz. (d). Cacuate the sma signa vtage gain, v /v s, fr frequencies abve 50 MHz but bew thse signa frequencies fr which the device capacitances becme criticay imprtant. Once again, ignre transistr Eary resistances. Cmpare this cmputed resut with apprpriate sma signa SPICE simuatins. +V CC R R CC R s C c v v s + R in Q2 Q R 2 R E Fig. (P4) Hmewrk #0 4 Fa Semester, 200

5 University f Suthern Caifrnia Sch Of Engineering Department Of Eectrica Engineering EE 448: Hmewrk Assignment #0 Fa, 200 (SOLUTIONS: Due 09/0/200) Chma Prbem #0: Hmewrk #0 5 Fa Semester, 200