Save Power, Increase Performances, Insure Functionality : Bypass your High Speed IC s!

Transcription

1 Save Power, Inrease Performanes, Insure Funtionality : Byass your Hih Seed IC s! Yves Ledu TI Chair Polyteh Sohia (work done with Nathalie Messina) - 1 -

2 Our Motivation: Kee byassin of advaned IC s under ontrol while keein the system ost as low as ossible

3 Abstrat Deoulin is one of the foundations of any ower manaement system. Advaned IC roesses are eneratin noise far above of the frequeny of the oeratin lok. Today we are already sufferin from losses of erformanes. We are lose now to undero non funtionality in our next IC desins! Pakain tehnoloy with low ost onstraints builds a frequeny barrier between the external byass devies and the IC ore. Consequently the IC modules deoulin annot be done at the PCB level but is now the resonsibility of the IC desiners. It is wron to think that more aaitane or lower ESR aaitor is rovidin a better solution. A reise byassin methodoloy must be alied. Surrisinly, the lassial full imedane omensation methodoloy is not the methodoloy to use when byassin ICs. We will show how an IC desiner and a PCB desiner ould share their resonsibility to build a safe Power Distribution System followin an aroriate byassin methodoloy

4 Power Suly Imat on IC s Funtionality How the ower is sulied to an interated iruit reatly affets the funtionality of the system: External byass aaitors annot address the hih frequenies issues [e.. Fujitsu_02]. Not enouh anymore Sulyin ower to hih seed interated iruits is a hallenin task: L di/dt must omlement ir Stati and Dynami Dro analysis!. Fast I transient Hih averae I - 4 -

5 Power Suly Imat on IC s Performanes How the ower is sulied to an interated iruit may affets the erformanes of the system: Power Suly noise limits the maximum oeratin frequeny of an interated iruit [PDN_04, Free_06, ] Freesale ains 8% of erformanes by on hi byassin 90nm NB: C nm C027 [Free_06] - 5 -

6 Definitions Deoulin The art and ratie of breakin oulin between ortions of systems and iruits to ensure roer oeration. Byassin The ratie of addin a low-imedane ath to shunt transient enery to round at the soure. Required for roer deoulin. [Cyress Semiondutor Cororation 1999] - 6 -

7 Byassin Stratey, an Examle: the Pentium 4 4 levels of Byassin 2. On PCB (Soket) 4. On Chi 1. On PCB (Soure) to view bottom view 3. In Pakae Too Exensive in a Wireless Terminal - 7 -

8 Byassin Stratey, an Examle: the Pentium 4 PCB 4 levels of Byassin Pakae with 8 layers of oer and exensive aaitors Pakae 1 VDD 4 VDD Multile VDD 1 VSS 4 VSS Multile VSS Indutane!! Cost " " Fli Chi Multi Layer Pakae et - 8 -

9 AGENDA 1- Bandwidth of Interest 2- Model of a Power Distribution System 3- Imedane of a Power Distribution System 4- Byassin Examles 5- Byassin Methods 6- Buildin the Worst Case Transient 7- IC and PCB Desiners Point of View 8- Power Distribution System Model Extration 9- Conlusion - 9 -

10 AGENDA 1- Bandwidth of Interest 2- Model of a Power Distribution System 3- Imedane of a Power Distribution System 4- Byassin Examles 5- Byassin Methods 6- Buildin the Worst Case Transient 7- IC and PCB Desiners Point of View 8- Power Distribution System Model Extration 9- Conlusion

11 A Traezoidal On-Chi Sinal t r << T si Si T Si = 2ns F 0 = 1.0 /2.0e-9 = 500MHz t r = 0.1ns 1GHz

12 Enery in a Traezoidal Sinal 100% Aumulated Enery [Si] 99.9% 99.98% 99.97% 99.99% 99.1% 99% Si T Si = 2ns BW Si = 0.35/ 0.1e-9 = 3.5GHz F 0 = 1.0 / 2.0e-9 = 500MHz 98% t r = 0.1ns 1GHz 1GHz 3.5 GHz 10GHz BW Si

13 The Bandwidth of Interest 0dB Bandwidth of Interest In our examle, with a t r of 0.1ns, the bandwidth of interest is 3.5GHz f taret = 3.5 GHz

14 Modelin Reality to Traezoidal Simlified Model In a Power Distribution System, the sinal is a Current Sure. I load i I max di/dt BW Si 0.35 / t r t t r

15 PDS Taret Imedane V dd = Power Suly Voltae [V] Tol = Allowed Rile [%] I max = Max Load Current [A] R taret = V dd x (Tol /100) / I max For examle, with an allowed rile of 10% on a Vdd of 1V and a max load urrent of 100mA, the taret imedane is 1Ω

16 PDS Taret Imedane Z out Manitude, lo Ω Bandwidth of Interest R taret = (Power Suly Voltae) x (allowed rile) / urrent 1 R taret KHz Imedane of the PDS must be LOWER than taret in the Bandwidth of Interest, althouh we will see that additional onstraints should be met! 100KHz 1MHz 10MHz 100MHz 1GHz 10GHz f taret = 3.5 GHz lo (Hz)

17 AGENDA 1- Bandwidth of Interest 2- Model of a Power Distribution System 3- Imedane of a Power Distribution System 4- Byassin Examles 5- Byassin Methods 6- Buildin the Worst Case Transient 7- IC and PCB Desiners Point of View 8- Power Distribution System Model Extration 9- Conlusion

18 Low Cost Solution for a Cost Constrained Business exensive aaitors exensive akae + low ost aaitors low ost akae Above IC Passive Interation Proess Module

19 Simlified Model of a Power Distribution System: RLC NB: Global round does not exist! R L r L b L r R b R R L out R b R R R m C b Byass Caaitors C C C m L b L L L m I load R L r L b L L r R b R R Voltae Reulator PCB IC Pakae Chi Module The ower soure and the load are onneted throuh resistive and indutive arasiti imedanes

20 The PCB Byassin does not Solve IC Issues Z out Manitude, lo Ω The Pakae Barrier 10 1 The suly 0.1 The IC limit 10KHz 100KHz 1MHz 10MHz 100MHz 1GHz 10GHz 100GHz lo (Hz)

21 Linear Variation of L and R with the Ciruit Dimensions 2π F res = 1 / LC R L r L b L r R b R R L R b R R R m C b C C C m L b L L L m I load R L r L b L L r R b R R PCB 50 mm Chi 5 mm => R LC Lare ross-setional dimensions of PCB interonnet Module 0.5 mm => R LC Small ross-setional dimensions of the IC interonnet Physial dimensions L r >> L b >> L >> L R r << R b << R << R C b >> C >> C >> C m

22 AGENDA 1- Bandwidth of Interest 2- Model of a Power Distribution System 3- Imedane of a Power Distribution System 4- Byassin Examles 5- Byassin Methods 6- Buildin the Worst Case Transient 7- IC and PCB Desiners Point of View 8- Power Distribution System Model Extration 9- Conlusion

23 Methodoloy 1- We will use the Frequeny Domain to desin: Work on the outut Imedane of the Power Distribution System 2- We will omfort the desin in the Time Domain: Transient resonse from aroriate stimuli

24 FYI, Some Orders of Manitude Pakae 424ZQX 0.3nH 5nH 15mΩ 180mΩ 0.1F 0.6F Bond Wire 50mΩ /mm 1nH /mm 0.05F /mm Tyial PCB Line 0.5nH /mm 0.1F /mm 5mΩ /mm Via throuh 1.6mm PCB 1.3nH Rule of Thumb 0402 Caaitor 100nF 0.5nH 25mΩ L 1nH /mm

25 Our Examle R L r r R b R R L b L L ****** TARGET I load.parms Z ****** PDN BOARD.PARMS Rr 0.25.PARMS Lr 50.0nH R L r L b L L r R b R R VR PCB Pakae IC.PARMS Rb 0.10.PARMS Lb 10.00nH VR ****** PDN IC.PARMS R 0.05.PARMS L 1.00nH IC.PARMS R 0.10.PARMS L 0.10nH PCB

26 PDS with No Byass Caaitor R L r L b L L r R b R R Z out R L r L b L L r R b R R R tot L tot PCB IC Z out R tot = R r + R r + R b + R b + R + R + R + R L tot = L r + L r + L b + L b + L + L + L + L

27 Imedane of a PDS with No Byass Caaitor Z out Manitude, lo Ω 100 Z out 10 Bandwidth of Interest 1 R taret R tot 2πf tot = R tot / L tot KHz 100KHz 1MHz 10MHz 100MHz 1GHz 10GHz A few MHz f taret = 3.5 GHz lo (Hz)

28 AGENDA 1- Bandwidth of Interest 2- Model of a Power Distribution System 3- Imedane of a Power Distribution System 4- Byassin Examles 5- Byassin Methods 6- Buildin the Worst Case Transient 7- IC and PCB Desiners Point of View 8- Power Distribution System Model Extration 9- Conlusion

29 PDS with a Sinle Byass Caaitor on PCB R 1 L 1 R 2 L 2 out Byass aaitor R C L I load R 1 L 1 R 2 L 2 PCB IC

30 PDS with a Sinle Byass Caaitor R 1 L 1 R 2 L 2 out Low Frequeny urrent R C L I load Below f res, the byass aaitane is relatively hih. R 1 L 1 R 2 L 2 R 1 L 1 R 2 L 2 out R C L Hih Frequeny urrent I load Assumin L < L 1, Above f res, the byass aaitane is lower than the (R1, L1) ath. R 1 L 1 R 2 L

31 Imedane of a PDS with a Sinle Byass Caaitor Z out Manitude, lo Ω 100 Bandwidth of Interest 10 Resonane Frequeny f res 1 Caaitive Behavior R taret R tot R 2 = R 2 + R Indutive Behavior Resistive Behavior KHz 100KHz 1MHz 10MHz 100MHz 1GHz 10GHz f res 1/2π A few tens of MHz f taret lo (Hz)

32 Transient of a PDS with a Sinle Byass Caaitor I load = Unit Ste t r = 0.1ns Imax = 0.1A 0A Current onsumed by the load Z out 10 BW = 3.5 GHz 1V 1.0V V out KHz 100KHz 1MHz 10MHz 100MHz 1GHz lo (Hz) V 0.96V 0.94V 25mV 0.95V 0.92V -2.0V 1ns 10ns 100ns 1µs Neative Sike of 3V lo (t)

33 Just Curious: Let s Inrease t r to 10ns I load = Unit Ste t r = 10.0ns Imax = 0.1A 0A Current onsumed by the load Z out 10 BW = 35 MHz 1.00V 1V V out KHz 100KHz 1MHz 10MHz 100MHz 1GHz lo (Hz) V 0.96V Neliible Rile! 0.94V Neative Sike of 80mV 0.95V 0.92V 0.90V 1ns 10ns 100ns 1µs lo (t)

34 Limitation with a Sinle Byass Caaitor The devie should have a hih aaity to store and release a suffiient amount of enery C > L 1 / Z taret (R 1 +R ) To suly suffiient ower at hih frequenies, the devie should be able to store and release enery at a suffiient delivery rate. (L 2 + L ) < Z taret / 2π f taret The ondition of low indutane ath annot be satisfied. Indutane L 2 is the issue: R 1 L 1 R 2 L 2 out L 2 1 nh f taret 3 GHz Z taret 1 Ω R C (1e-9 + L ) >> 1 / (6.28 x 3e9) L I load R 1 L 1 R 2 L 2 Bondin

35 Hierarhial Plaement of Byass Caaitors Exloits the tradeoff between the aaitane and the arasiti series indutane of a byass aaitor. The byass aaitor at eah stae is effetive within a limited frequeny rane. The ranes of effetiveness overla eah other, reahin f taret. R L r L b L r R b R R L out Board Byass Caaitors R b C b Pakae Byass Caaitors R C On Chi Byass Caaitors R C Module Byass Caaitors R m C m L b L L L m I load R L r L b L L r R b R R Voltae Reulator PCB IC Pakae Chi Module

36 Imedane of a PDS with Hierarhial Byass Caaitors Z out Manitude, lo Ω 10 Bandwidth of Interest C b Behavior C Behavior 1 R tot R taret C Behavior C m Behavior KHz 1MHz 10MHz 100MHz 1GHz 10GHz 100GHz f b res f res f res f m res f taret lo (Hz)

37 Transient of a PDS with Hierarhial Byass Caaitors I load = Unit Ste t r = 0.1ns I max = 0.1A Current onsumed by the load BW = 3.5 GHz 0A 1V V out BUT as we will see, this is not the Worst Case 0.98V 0.96V 35 mv 0.95V 0.94V 0.92V 10ns 100ns 1µs lo (t)

38 Worst Case Peak Transient To et the worse ase of sikes on the suly voltae, we aly an aroriate stimulus as I load. 1100mV V out_ositive_sike 1050mV 1000mV 1V 950mV 900mV How to build the worst ase stimulus will be exlained later. Thrust us for the moment, this is the result of the worst ase stimulus. 850 mv 0.0µs 1.0µs 2.0µs 3.0µs t

39 Worst Case Peak-to-Peak Transient We aly the neative and ositive stimulus to et the eak to eak value. 1100mV 1050mV V out_ositive_sike V out_neative_sike Worst ase stimulus 232 mv Unit ste resonse 35 mv 1000mV 950mV 232 mv 1V 0.95V 900mV Bad Rile! Althouh the PDS imedane is below R taret. 850 mv 0.0µs 1.0µs 2.0µs 3.0µs t

40 Flat Imedane of a PDS with Hierarhial Byass Cas Z out Manitude, lo Ω It is ossible to flatten the PDS imedane by roer tunin of the byass aaitors. Method alled full imedane omensation will be exlained later. 10 Bandwidth of Interest 1 R tot R taret 0.1 Flat Imedane = Resistive Behavior in the Bandwidth KHz 1MHz 10MHz 100MHz 1GHz 10GHz 100GHz f taret lo (Hz)

41 Transient of a PDS with a Flat Imedane I load = Unit Ste t r = 0.1ns 0.1A Current onsumed by the load BW = 3.5 GHz 0A 1V 0.990V V out With a Flat Imedane in the Bandwidth 0.980V Worst ase will not be 0.970V very different than this ste 0.960V resonse 0.950V 0.9 mv 0.95V 0.940V 0.930V 10ns 100ns 1µs Quasi-resistive Behavior dominated by the IR Dro

42 AGENDA 1- Bandwidth of Interest 2- Model of a Power Distribution System 3- Imedane of a Power Distribution System 4- Byassin Examles 5- Byassin Methods 6- Buildin the Worst Case Transient 7- IC and PCB Desiners Point of View 8- Power Distribution System Model Extration 9- Conlusion

43 Method to Flatten the Imedane of a PDS with HBC R L r L b L L r R b R R A full imedane omensation at eah byassin stae R b C b R C R C R m C m L b L L L m I load Z out Manitude, lo Ω R L r L b L L r R b R R Resistive Imedane in the Bandwidth of Interest Asymtoti imedane of byassin staes R tot R taret f res = 1/ L C R b = R r C b = L r / (R b ) 2 R = R r + R b C = (L b + L b ) / (R ) 2 R = R r + R b + R C = (L + L ) / (R ) 2 R m = R r + R b + R + R = R tot C m = (L + L ) / (R m ) 2 f taret lo (Hz)

44 Method to Flatten the Imedane of a PDS with HBC A full imedane omensation at eah byassin stae L r L R b L r R b R R L R b R R R m C b C C C m L b L L L m I load R L r L b L L r R b R R R b = R r C b = L r / (R b ) 2 R = R r + R b C = (L b + L b ) / (R ) 2 R = R r + R b + R C = (L + L ) / (R ) 2 R m = R r + R b + R + R = R tot C m = (L + L ) / (R m )

45 How it Works? R L r L b L r R b R R L R b R R R m Low Frequeny urrent C b C C C m Hih Frequeny urrent L b L L L m I load R L r L b L L r R b R R (db) 0dB I(Vre) / I load I(Cb) / I load I(C) / I load I(C) / I load I(Cm) / I load -20dB -40dB -60dB 1MHz 10MHz 100MHz 1GHz lo (Hz)

46 Byass Caaitors Comutation L r R L b L r R b R R L R b R R R m C b C C C m ****** TARGET L b L L L m I load.parms Z R L r L b L L r R b R R ****** PDN BOARD.PARMS Rr 0.25.PARMS Lr 50.0nH.PARMS Rb 0.10.PARMS Lb 10.00nH ****** PDN IC.PARMS R 0.05.PARMS L 1.00nH.PARMS R 0.10.PARMS L 0.10nH ****** BYPASS ON THE BOARD.PARMS RCb 0.25.PARMS Cb nF.PARMS LCb 5.00nH.PARMS RC 0.35.PARMS C 122.4nF.PARMS LC 1.50nH ****** BYPASS ON THE IC.PARMS RC 0.4.PARMS C 15.6nF.PARMS LC 0.10nH.PARMS RCm 0.5.PARMS Cm 0.75nF.PARMS LCm 0.01nH R b = R r C b = L r / (R b ) 2 R = R r + R b C = (L b + L b ) / (R ) 2 R = R r + R b + R C = (L + L ) / (R ) 2 R m = R r + R b + R + R = R tot C m = (L + L ) / (R m )

47 Flat Imedane of a PDS with Hierarhial Byass Cas Z out Manitude, lo Ω 10 Bandwidth of Interest 1 R tot R taret 0.1 Flat Imedane = Resistive Behavior in the Bandwidth KHz 1MHz 10MHz 100MHz 1GHz 10GHz 100GHz f taret lo (Hz)

48 The ESR Issue R L r L b L r R b R R L R b R R R m C b C C C m ****** TARGET L b L L R L r L b L L r R b R R L m I load.parms Z ****** PDN BOARD.PARMS Rr 0.25.PARMS Lr 50.0nH.PARMS Rb 0.10.PARMS Lb 10.00nH ****** PDN IC.PARMS R 0.05.PARMS L 1.00nH.PARMS R 0.10.PARMS L 0.10nH ****** BYPASS ON THE BOARD.PARMS RCb 0.25.PARMS Cb nF.PARMS LCb 5.00nH.PARMS RC 0.35.PARMS C 122.4nF.PARMS LC 1.50nH ****** BYPASS ON THE IC.PARMS RC 0.4.PARMS C 15.6nF.PARMS LC 0.10nH.PARMS RCm 0.5.PARMS Cm 0.75nF.PARMS LCm 0.01nH Imossible to realize suh lare ESR on Chi

49 Bi V Imedane of a PDS Z out Manitude, lo Ω 10 Bandwidth of Interest 1 R tot R taret -3dB 0.1 Lower the ESR of all On Chi Byassin Caaitors 0.01 Bi V Imedane in the Bandwidth KHz 1MHz 10MHz 100MHz 1GHz 10GHz 100GHz 12 MHz f F taret w = 275 MHz lo (Hz)

50 The Bi V Values R r L r R b L b R L R R b R R L R m C b C C C m L b L L L m I load R L r L b L L r R b R R Values for a Flat Imedane ****** BYPASS ON THE BOARD Values for a BiV Imedane ****** BYPASS ON THE BOARD.PARMS RCb 0.25.PARMS Cb nF.PARMS LCb 5.00nH.PARMS RC 0.35.PARMS C 122.4nF.PARMS LC 1.50nH ****** BYPASS ON THE IC.PARMS RC 0.4.PARMS C 15.6nF.PARMS LC 0.10nH.PARMS RCm 0.5.PARMS Cm 0.75nF.PARMS LCm 0.01nH =.PARMS RCb 0.25.PARMS Cb nF.PARMS LCb 5.00nH.PARMS RC 0.35.PARMS C 122.4nF.PARMS LC 1.50nH ****** BYPASS ON THE IC.PARMS RC 0.01.PARMS C 4.0nF.PARMS LC 0.10nH.PARMS RCm 0.01.PARMS Cm 35.0nF.PARMS LCm 0.01nH

51 Transient on a PDS with Bi V Imedane I load = Unit Ste t r = 0.1ns 0.1A Current onsumed by the load BW = 3.5 GHz 0A 1V 1.00V 0.990V V out With a Bi V Imedane in the Bandwidth 0.980V 0.970V τ 14ns 0.960V 0.950V 0.940V slower resonse RC behavior 0.95V 0.930V 10ns 100ns 1µs

52 Transient on a PDS around the Imedane Di 275 MHz 100mA Load 275 MHz F W 0mA 0mV -20mV Full Imedane Comensation 9 mv Load If the oeratin frequeny oinides to the frequeny di -40mV BiV -55 mv Pakae 0mV -20mV Bi V is better! - 16 mv Load 0ns 50ns 100ns - 34 mv

53 AGENDA 1- Bandwidth of Interest 2- Model of a Power Distribution System 3- Imedane of a Power Distribution System 4- Byassin Examles 5- Byassin Methods 6- Buildin the Worst Case Transient 7- IC and PCB Desiners Point of View 8- Power Distribution System Model Extration 9- Conlusion

54 Build the Worst Case Transient Exitations V out Ste Resonse V DC V DC = 50.00mV t 0 lo (t) V 0 = 50.09mV t 0 = 0 V 1 = 49.65mV t 1 = 342ns V 2 = 51.42mV t 2 = 684ns V 3 = 44.25mV t 3 = 1026ns V 4 = 75.09mV t 4 = 1356ns V 5 = 61.40mV t 5 = 1428ns V 6 = 78.90mV t 6 = 1486ns V 7 = 59.41mV t 7 = 1501ns V 8 = 77.10mV t 8 = 1509ns V 9 = 54.43mV t 9 = 1512ns V 10 = 77.78mV t 10 = 1513ns 100mA 0mA 100mA 0mA t 0 t 1 t 2 t 3 t 4 t

55 the Worst Case Transient Resonses Worst Case Exitation Combination of Ste Funtions Worst Case Exitation Combination of Ste Funtions Worst Case Neative Resonse Worst Case Positive Resonse V = 232 mv 0.0µs 1.0µs 2.0µs 3.0µs t

56 Worst Case Transient Comuted from Ste Resonse V out V DC 2 3 Ste Resonse V DC = 50.00mV t 0 lo (t) V 0 = 50.09mV t 0 = 0 V 1 = 49.65mV t 1 = 342ns V 2 = 51.42mV t 2 = 684ns V 3 = 44.25mV t 3 = 1026ns V 4 = 75.09mV t 4 = 1356ns V 5 = 61.40mV t 5 = 1428ns V 6 = 78.90mV t 6 = 1486ns V 7 = 59.41mV t 7 = 1501ns V 8 = 77.10mV t 8 = 1509ns V 9 = 54.43mV t 9 = 1512ns V 10 = 77.78mV t 10 = 1513ns As the PDS model is linear, it is not neessary to simulate the worst ase transient resonse: The worst eak to eak variation an be omuted from the ste resonse: V = V 0 - V 1 + V 2 - V V 9 + V 10 = 141mV V = 2 V V DC = 232mV

57 AGENDA 1- Bandwidth of Interest 2- Model of a Power Distribution System 3- Imedane of a Power Distribution System 4- Byassin Examles 5- Byassin Methods 6- Buildin the Worst Case Transient 7- IC and PCB Desiners Point of View 8- Power Distribution System Model Extration 9- Conlusion

58 Bandwidth of a Traezoidal Sinal 0dB -20dB FFT [Si] - 20dB / deade BW Si 0.35/ t r = 3.5 GHz F 0 = 500 MHz BW Si >> F 0-40dB Traezoidal Shae -60dB Si T Si = 2ns - 40dB / deade dB BW Si = 0.35/ 0.1e-9 = 3.5GHz F 0 = 1.0 / 2.0e-9 = 500MHz t r = 0.1ns 1GHz 100MHz 1GHz 10GHz 100GHz

59 PCB Desin, IC Desin: Imedane Mathin R tot = R Ext + R IC PCB IC PCB byassin, fun(f math, R IC, R Ext ) F math R Ext F math R IC IC byassin, fun(f math, R IC, R Ext ) Full ower distribution system byassin

60 The IC Desiner Point of View R tot = R Ext + R IC VDD R IC PCB F math IC Aordin to the desin methodoloy resented in the revious slides, the IC desiner needs to fix the aroriate Resistane Budet R Ext of the external ower suly to obtain the seified erformanes. The desiner will use the BiV method to hoose the byass aaitors on the IC. The IC desiner will ommuniate to the PCB desiner the resistane budet R Ext, the internal resistane of the IC R IC and the frequeny F math

61 The Job of the IC Desiner R L r L b L r R b R R L R Ext C b L b C L C L C m L m I load R b R R R m R L r L b L L r R b R R The IC must behave as a resistane R IC at F math PCB Z out Manitude, lo Ω BiV byassin method is reommended for frequenies above F math R tot = R Ext + R IC The PCB is modeled as a resistane R Ext F math lo (Hz)

62 The PCB Desiner Point of View Aordin to the desin methodoloy resented in the revious slides, the PCB desiner needs to know the Resistane Budet R Ext of the ower suly, the Resistane of the IC R IC and the Frequeny F math to realize the imedane mathin. These resistanes are rovided by the IC vendor. R Ext inludes the PCB line resistane and the internal resistane of the voltae reulator. R Ext = R Reulator + R PCB line The PCB desiner will then use the Full Imedane Comensation method to hoose the byass aaitors on the PCB

63 The PCB Desiner Point of View R r L r R b L b R b C b L b R C L R IC R r The PCB must behave as a resistane R ext below F math L r R b L b IC Z out Manitude, lo Ω The IC is modeled as a resistane R IC R tot = R Ext + R IC Usin the R Ext, R IC and the Frequeny F math, the PCB desiner is able to et a erfet imedane mathin. F math lo (Hz)

64 AGENDA 1- Bandwidth of Interest 2- Model of a Power Distribution System 3- Imedane of a Power Distribution System 4- Byassin Examles 5- Byassin Methods 6- Buildin the Worst Case Transient 7- IC and PCB Desiners Point of View 8- Power Distribution System Model Extration 9- Conlusion

65 Model Partitionin of a Power Distribution System Module3 Module4 Module2 Extration Module1 Module5 Funtional artitionin VDD 4 VDD 3 VDD 2 VDD 1 Simler Equivalent Model

66 Model of a Power Distribution System with n Modules R L r L b L r R b R R 1 L 1 out1 R b R R R m1 C b C C C m1 L b L L L m1 I load1 R L r L b L L r R b R R 1 1 R 2 L 2 out2 R m2 The same methodoloies may be alied to larer strutures C m2 L m2 I load2 R 2 L

67 Byassin and Deoulin R Ext ΔI Aressor MA R tot = R Ext + R IC ΔV = R Ext x ΔI Vitim MV A ood byassin does imrove the deoulin. R tot Lowerin R Ext imroves the deoulin of the system. Best deoulin is obtained with low R Ext. Byassin onstrains R tot Deoulin onstrains R Ext R tot small R Ext small

68 AGENDA 1- Bandwidth of Interest 2- Model of a Power Distribution System 3- Imedane of a Power Distribution System 4- Byassin Examles 5- Byassin Methods 6- Buildin the Worst Case Transient 7- IC and PCB Desiners Point of View 8- Power Distribution System Model Extration 9- Conlusion

69 Power Distribution Networks in Hih Seed IC s Byassin Stratey Methodoloy Hih Density Caaitors Hierarhial Byassin, Full Comensation, BiV, Above - IC Caaitors

70 A Few Referenes [PDN_04] Power Distribution Networks in Hih Seed Interated Ciruits Andrey V. Mezhiba, Eby G. Friedman, 2004 by Kluwer Aademi Publishers [Fujitsu_02] Yoshihiko Imanaka, Takeshi Shioa, John D. Banieki, Deoulin Caaitor with Low Indutane for Hih Frequeny Diital Aliations Fujitsu Si. Teh. J., 38,1,22-30 June 2002 [Free_06] Miroroessor Desin Forum ISSCC 2006, Multi-Core Arhitetures, Desins and Imlementation Challenes Presentation of D. Bouvier, Freesale, hallene of Hih Performane Multi-Core Proessors for embedded Infrastruture [SPI_05] CEI-Euroe Course on Sinal and Power Interity of Hih Seed System Desin Dr Istvan Novak, November