DV722SI DV525SI Service Manual

Transcription

1 DVSI DVSI Service Manual Note: these models machine are the deviation ones of DK00S, so this service manual only introduces the circuit different from DK00S, please refer to DK00S Service Manual for details.

2 DVSI Service Manual DVSI changes UI and remote controller on the basis of DK00S, the circuit principle of the two is the same on the whole, the adopted aschme is MT C+M FLSH+M SDRM+CS0+HD+tuning+0 appearance+new UI. The main difference of the two models is that DVSI has no speakers. s for working principle of DVSI, please refer to DK00SI Service Manual... Collocation table The collocation table of this two models are listed here, so please refer to them for the difference of the two models.. The collocation table of the player DK00S is shown in the following table: Model Vers ion of player Decode board Output board OK board Power board Main panel Loader Scheme DK00S Ver.00 S- Ver.0 B0S-0 Ver.0 0S-0 Ver.0 0S- Ver.0 0S- Ver.0 DVS+ 0B MTEE+HD0+M FLSH+M SDRM+CS+tuning+0 appearance DK00S- Ver. VER. S- Ver.0 - Ver.0 0S-0 Ver. 0S- Ver.0 0S- Ver.0 DVS+ 0B MTEE+HD+M FLSH+M SDRM+CS+tuning+0 appearance DK00S- Ver.0~V RT. T-0 Ver.0 - Ver.0 0S- Ver.0 0S- Ver.0 0S- Ver.0 DVS+ 0B MTC+HD+M FLSH+M SDRM+CS+tuning+0 appearance DK00S- Ver.0 00S-0 Ver.0 - Ver.0 0S- Ver.0 0S- Ver.0 0S- Ver.0 DVS+ 0B # MTC version+hd +M FLSH+M SDRM+CS0+tuning+0 appearance DK00S- Ver.0 00S-0 Ver.0 - Ver.0 0S- Ver.0 0S- Ver.0 0S- Ver.0 DVS+ 0B # C+HD+M FLSH+M SDRM +tuning+0 appearance - -

3 . The collocation table of the player DVS is shown in the following table: Model Vers ion of player Decode board Output board OK board Power board Main panel Loader Scheme DVS VER.00 S- Ver. - Ver.0 0S- Ver. 0S- Ver.0 0S- Ver.0 DVS+ 0B # MTEE+HD+M FLSH+M SDRM+CS+tuning+0 appearance DVS- Ver.0 00S-0 Ver.0 - Ver.0 0S- Ver.0 0S- Ver.0 0S- Ver.0 DVS+ 0B # MTC version+hd loader+m FLSH+M SDRM+CS0+tuning+0 appearance DVS- Ver.0 00S-0 VER.0 - Ver.0 0S- Ver.0 0S- Ver.0 0S- V.0 DVS 0B # C+HD+M FLSH+M SDRM +tuning+0 appearance DVSI SI.00 00S-0 Ver.0 - Ver.0 0S- Ver.0 0S- Ver.0 0S- Ver.0 DVS +0B MTC+M FLSH+M SDRM+CS0+HD+tuning +0 appearance.. /D conversion circuit DVSI and DK00S have some differences in audio /D conversion circuit, when microphone has signal input, MIC signals are amplified through MIC board, and OK signals after being amplified pass through limiter circuit, shown in the figure..., limiting the range of input signals can effectively prevent the distortion produced by the too large input signal and avoid the strike caused by the peak value voltage from outside interference to /D converter. Karaoke signals after limiting circuit are divided into two ways, which input to pin 0, of Cs0 respectively, shown in the figure..., through /D conversion inside Cs0 and MCDT ( ) pin, output to decode chip, after being processed inside, overlap output with audio signal outputted by DVD player to realize Karaoke function. DV DV OK R 0K OK# R R R K R 0K R 0K(NC) R 0K DV DV C TC0 uf/v R (NC) C SCLK MCDT SBCLK SLRCK M0 M MCLK FILT+ VL REF_ SDOUT V INR VD VQ SCLK INL LRCLK RST U0 CS0 0 C 0 RST# C0 R (NC) C 0 C N VD OKRC 0 R0 OKL C 0 DV C C 0 VD N Figure... Limiting circuit diagram OK# Figure... Karaoke /D conversion circuit diagram - -

4 .. PCB board. Surface layer of KEY SCN Board - -

5 . Bottom layer of KEY SCN Board R0 R0 C0 Q0 C0 R0 R0 XS0 R0 R0 R0 U0 C0 R0 Q0 R R - -

6 . Surface layer of MPEG & SERVO Board - -

7 . Bottom layer of KEY SCN Board - -

8 . Surface layer of V OUT Board - -

9 . Bottom layer of V OUT Board R L0 C0 L0 L0 C0 L0 L0 C0 C0 C0 C0 C0 L0 C L L R0 L L C0 C C ZD0 R0 R0 ZD0 C ZD0 ZD0 C C D0 D0 R C C R0 C0 C C C C R C C - -

10 . Surface layer of MIC Board MIC0 JK0 JP0 TC0 TC TC0 JP0 JP0 TC C0 TC0 R JP0 TC S V 0S- DVD 00/0/0 JP0 TC0 U0 TC R R R R TC TC JP0 JP0 TC JP0 JP0 JP0 +V XS0 DET R +V -V TL TR XS0 OK - -

11 . Bottom layer of MIC Board C R C0 C C U0 R R C C R C R R0 R R R0 C0 R0 C0 R0 L0 R0 R0 R R C0 R R C0 R R R R C0 VD0 VD0 R0 VD0-0 -

12 . POWER Board (mm) L0 D0 D0 HIGH VOLTGE C0 L0 DET OK -V +V +.V S+V NC NC G0 BC0 C0 T0 D0 TC0 CN0 C0 JP0 JP0 (mm) R0 BC0 L0 F0 T. 0V 0S- 00// BCN0 D0 LEI D0 U0 L0 TC0 C0 TC0 C0 CUTION: FOR CONTIUED PROTECTION R0 GINST RISK OF FIRE REPLCE ONLY WITH SME TYPE F0 BCN0 ~0V T. L0V FUSE R0 R0 R0 C0 JP0 D0 D0 C0 TC0 D0 D0 D 0 C JP0 BC0 C U0 D U0 C R0 R0 R0 C0 TC0 C TC R0 TC0 TC JP0 JP0 R0 JP0 L0 TC0 L0 ZD0 C0 JP0 R JP0 TC0 JP0 TC ZD0 U0 R FL- -V CN0 G0 TC0 JP NC DET OK -V S+V NC FL+ - -

13 MPTH DVN SD SCL 0 PSWN FIN LVIN 0 SCOUT CIN MRO OSCI MPXIN VDD VDDD VREF MD VSSD VSS OSCO TCON U S R 0 R 0 R 0 R 0 R 0K R 0K R 0K R 0K R0 0K R K R 00 C 0P C0.n C0 00n C P C P C0 0P TC.U TC U TC 0U/V ZD0 V X0.MHZ C0 0.U C0 0.U RDS_MPX DVNIN SD SCL RDSCE R 0 RDSID _DTS R R 0 R 0 R0 0 R 0 R 0K R00 0K R0 0K R 0K RDS_MPX TUNER-R TUNER-L DTS_DO DTS_CL DTS_DI DTS_CE _DTS R0 0 TC 0uF/V C L 00 U 0 UB 0 R 0K R0.K R.K R 0K R R R 00K R 00K R.K R.K TC 0UF/V TC 0UF/V C 0 C CP C CP C CP C CP C 0 -V Q SC-Y Q SC-Y LL RR MUTE- TL TR R0 0K(DNS) R 0K(DNS) C0 0 OK L 00 TC 0U C _DTS X0 X X X Y0 Y Y Y INH 0 B VEE X Y VDD VSS U0 CD0 R 00K R 00K TUNER-L R 00K R 00K TUNER-R -V FL FR L R OB O L L TC0 0UF/V C C TC 0UF/V R0 K R K R 0K Q0 00 R0 K R 0K Q0 00 R K O O OB OB R0 K R0.K R TUNER_ON Q0 0 Q0 00 R K 0 XS0 XS RDS_CLK RDS_DT R 0K R 0K RDS_ RDS_.. circuit diagram. MPEG & SERVO Board - -

14 DVD CEQP 0 DVDB DVDC DVDD OSP OSN DVDRFIP DVDRFIN M MB MC 0 MD S SB SC SD CDFON CDFOP TNI TPI MDI 0 MDI LDO LDO VDD VREFO S VREFO 0 V0 TEO FEO USB_VSS RFLVL/RFON CSO/RFOP TEZISLV OP_OUT OP_INN OP_INP FOO TRO USBM TROPENPWM PWMOUT/V_DIN 0 USB_VDD FMO DMO HIGH0 HIGH HIGH HIGH HIGH HIGH 0 HIGH HIGH DVDD D PLLCP D D PLLVSS PLLVDD D D D D0 DVDD IO0 IO IO IO IO DVDD 0 IO IO IO 0 IO IO0 IO LE 0 IOOE IOWR IOCS UWR URD DVDD UP_ UP_ UP_ 00 UP_ 0 UP_ 0 UP_ 0 UP_0 UP_ 0 UP_ 0 UP_ 0 RFVDD RFRPDC DVDD 0 ICE 0 PRST 0 IR INT0 DVDD DQM0 DQS0 RD RD RD RD 0 RD RD RD RD0 RD RD DVDD RD YUV0/CIN FS VREF 0 DCVDDC RD RD RD RD RD0 RD DVDD RD RD 0 DQM DQM RD RD RD DVDD RD RD RD 0 RD0 DVDD RD/SDT R R R R R 0 R R RCLK CKE DVDD RCLKB RVREF/V_DIN DVDD R R 0 R R0 R0 B B0 DVDD RCS RS 0 CS RWE DQM DQS RD RD RD0 RD DR 0 RF IREF SVDD RFGC JITFN JITFO 0 LPFOP LPFIN CRTPLP HRFZC LPFIP CEQN RFRPC S_VREFN DCVSS S_VREFP S_VCM 0 DCVDD PLLVDD LPFON PLLVSS MC_DT SPDIF SDT DVDD SDT 0 SDT RF SDT SDT0 CLK LRCK BCK DVDD 0 SPBCK/SDT SPLRCK 0 SPDT 0 SPMCLK 0 DVDD HSYNC/V_DIN 0 YUV/SDT 0 VSYNC/V_DIN 0 YUV/R 0 YUV/B 0 DCVSS 0 YUV/G 00 DCVDD YUV/CVBS DCVSSB YUV/C DCVDDB YUV/Y DCVSSC IDCEXLP USBP FG/V_DIN TDI/V_DIN TMS/V_DIN TCK/V_DIN 0 TDO/V_DIN D IO/V_DIN0 XTLO XTLI RFVDD U0 MTC C0 uf C0 uf C0 uf C0 uf C0 DNS C0 0p C B D RFO R0 R0 R0 R0 C B D E F MDI MDI LDO LDO RFOP RFON VP V0 VP FEO TEO TEZISLV OPO OP- OP+ DMO FMO TROPEN C0 R0 R0 R0 C0 C0 TRO FOO L0 V USBVDD DIN TROUT TRIN STBY TRCLOSE V C C 00pF R R0 K R 0K C 0pF C 0pF C C0 pf R0 K R0 0K DMSO FMSO TRSO FOSO VP VP DIN L0 R V PWR# 0 0 PCE# PRD# D0 D D D D D D D 0 V VSCK VSD VSTB SCL SD RXD TXD URST# IR DQM0 DQS0 DQ DQ DQ DQ DQ DQ DQ DQ0 DQ DQ R K DQ DQ0 DQ DQ DQ DQ RS# CS# WE# DQM LIMIT CS# B0 B DM0 DM0 DM DM DM DM DM DCKE DCLK DM DM DM DM DM RDS_DT RDS_CLK RDSCE RDSID DVNIN MUTEB TUNER_ON OB DTS_DO DTS_CL DTS_DI DTS_CE O R C Y0 FS V V L0 DCVDD DV C TC0 0uF/V Y DV Y Y Y Y Y VSYNC# HSYNC# RGB_SWITCH FS FS0 R K LRCK BCK CLK R (DNS) R (DNS) R (DNS) SDT0 SDT SDT V R0 (DNS) RESET# SPDIF RFV XI XO JITFO JITFNC 0.uF TC0 0uF/V PLLVDD C 0.0uF C0 0.0uF C uf DCVDD RFVDD VREFN VREFP C 0pF C 000pF R 00K C C 0.0uF C C C R K C VP VDD V C 00pF R 0K JITFN JITFO L0 L0.R L0 L0 L0 C C C C RFV PLLVDD DCVDD RFVDD RFSVDD C C C0 uf VREFN VREFP C TC0 uf/v C TC0 uf/v C TC0 uf/v C0 C C C C C C C C C C C C C V L L VDD DV 0 0 XS0 P0.mm C L L L L L L0 L0 L0 L0 0uH L0 L0 L0 0uH L L0 L L L L C0 TC0 0uF/V C E V0 SB-S V0 SB-S R0 R0 TC0 uf/v TC0 uf/v LDO-V LDO-V LDO LDO R0 L0 MDI F L B RFO IO D C V0 R0 0K R0 00K R 0K R0 00K V0 SK0-S V0 SK0-S V0 0-S IO L C0 V RFV R 0K R 0K R 0K C0 C0 C0 C0 TC0 uf/v R0 R R0 R R 0K R0 R R0 R C0 VINFC CF CF VINSL+ VINSL- VOSL VINFFC 0 P P 0 VOSL- VO+ VOFC- VOFC+ VOTK+ VOTK- VOLD+ VOLD- P VNFTK 0 P PRE VINLD CTK CTK VINTK BIS STBY U0 B TRSO VP STBY SL+ SL- FMSO MO_ MO_ SP- SP+ VP FOSO DMSO L0 R 0K R R R R R0 0K R 0K R 0K R 0K R C0 00pF DIN OP- OP+ VP SP- OPO C0 DNS V0 00 V0 00 V0 0 V0 0 R.K R.K R 0K R.R\/W TC0 uf/v TC0 uf/v LOD+ LOD- TRCLOSE V0 0-S TROPEN (TRCLOSE) (TROPEN) (TRCLOSE) TROPEN XS0 P.0mm LOD- LOD+ TROUT TRIN C0 SP+ SL+ SL- LIMIT XS0 XS0 L0 DV R TDI TMS TCK TDO R0 0K DV C TC 0uF/V L DV R0 R C0 00pF R 0K R0 0K DV RFSVDD R DQS0 R R R PWR# PCE# PRD# DWR# DCE# DRD# MDT R R C TC uf/v C TC uf/v R VOICE-DET - -. MPEG & SERVO Board

15 L L0 L R0.K C pf IR VSCK VSTB VSD XS0 XS0(DNS) DV RXD TXD C TC0 uf/v C C SD L DV C 0 TC 00uF/V VD0 N R 0K R K R R U0C HCU0 URST# DV DC/NC RST_/NC WP/RST_ VSS RST/WP SCL SD U0 TCX00 SD SCL C DV R R0 C pf C pf C pf RY/BY NC NC 0 NC 0 WE RESET 0 DQ 0 DQ DQ0 DQ DQ DQ/- DQ DQ DQ BYTE Vss DQ DQ DQ DQ 0 DQ Vcc DQ0 OE Vss DQ CE 0 U M_FLSH(TSOP) 0 0 D D D D D D D VD D D D0 D D D D D0 DRD# DCE# UP[0..0] UPD[..0] R.K(DNS) VP R0.K R.K R.K VD C TC uf/v R VD DV 0 L0 (DNS) R (DNS) L L C pf XS0 XS0 C0 0(DNS) C 0(DNS) U0 HCU0 X0 MHz U0B HCU0 R 00K C pf C pf R (DNS) MHZ C C 0pF(DNS) R (DNS) R (DNS) XI R XO XTLI R U0F HCU0 0 U0E HCU0 SPDIF IEC R0 (DNS) R R0 C0 0 C pf L.uH V R C0 0 C0 pf L.uH V R C0 0 C pf L0.uH V R C 0 C pf L.uH V R0 C 0 C pf L.uH V R C 0 C pf L.uH V L L L L L L Y Y Y Y Y Y 0 0 0/P B0/ 0 B/ CLK CKE /CS /RS /CS /WE DQML DQMH NC NC 0 VSS VSS VSS DQ0 DQ DQ DQ DQ DQ 0 DQ DQ DQ DQ DQ0 DQ DQ DQ 0 DQ DQ Q Q Q Q VSSQ VSSQ VSSQ VSSQ U SDRM M DM0 DM DM DM DM DM DM DM DM DM DM0 M B0 #B SDCLK SDCKE DCS# DRS# DCS# DWE# DQM0 DQM DQ0 DQ DQ DQ DQ DQ DQ DQ DQ DQ0 DQ DQ DQ DQ DQ DQ SD SD R R R R DM B C L L L L0 L L VOICE-DET OK C C C0 C TC0 0uF/V TC0 0uF/V -V DV C TC 0uF/V L DV 0 XS0 XS MUTE L VD0 N00 VD0 N00 IN OUT U0 LMMP-.(DNS) C TC0 0uF/V R.K R.K V DV R0 R (DNS) R (DNS) 0 R R R R R R R R R R R R DCLK DCKE CS# RS# CS# WE# L VV DWR# TC 0uF/V C FS0 C pf(dns) L.uH(DNS) C C C0 C L0 R (DNS) DV VV V VV VIDEO_U VIDEO_V VV VIDEO_C V VIDEO_Y VV V VIDEO_COMP VV VIDEO_Y V VD0 N VD N VD N VD N VD N VD N VD N VD N VD N VD N VD0 N VD N VV V V C C C0 TC0 0uF/V VV V R (DNS) XI URST# Q0 0 V LFE Cc SR SL Rt VIDEO_COMP VIDEO_U VIDEO_V VIDEO_C VIDEO_Y IEC HSYNC# VSYNC# R (DNS) R FS R (DNS) R VIDEO_Y R TL TR Lt XS0 XS0 R MUTE MPEG & SERVO Board

16 R0 R0 0K R0 R K VD0 N R0 K VD0 N -V MUTE- TC 0uF/V TC uf/v R0 0K Q SC-Y Q 0 Q 0 C (DNS) C C (DNS) SW /C SR# SL# R L TC 0uF/V TC 0uF/V TC 0uF/V TC 0uF/V TC 0uF/V TC0 0uF/V R0.K R.K C C 0 C 0 R 0K R 0K C0 0 C 0 C (DNS) R.K R.K R.K R.K C C 0 C 0 R 0K R.K R.K C 0 C 0 R 0K R.K R.K C 0 C 0 R 0K R 0K C 0 C 0 R.K R0.K U 0 UB 0 U 0 U0B 0 U0 0 UB 0 -V -V -V -V -V -V TC 0uF/V TC 0uF/V TC 0uF/V TC 0uF/V TC0 0uF/V TC 0uF/V CH-L CH-R CH-SL CH-SR CH-C CH-SW R K R K R0 K R K R K R K R K R K R 00K R 00K R 00K R 00K MUTE- Q0 SC-YS Q0 SC-YS Q0 SC-YS Q0 SC-YS R K R K R K R K R 00K R 00K Q0 SC-YS Q0 SC-YS C C C0 C C C -V SDT SDT SDT0 SLRCK SCLK SBCLK SCL SD RESET# RS LS LFE# C# R 0K C 0 OK R 0K R.K R.K R.K R.K R.K R.K C C C0 C C C VOICE-DET VLS SDIN SDIN SDIN SCLK LRCK MCLK VD RST 0 SCL SD CS VLC MUTEC OUT OUTB MUTEC OUT OUTB V OUT 0 OUTB MUTEC VQ FILT+ M U0 CS0 C C DV MUTE C TC 0uF/V C TC 0uF/V C TC 0uF/V R TC 0uF/V MUTE MUTE R RS L LS LFE# C# MUTE Q 0 R0 K R0 K VD0 N VD0 N VD0 N MUTE MUTE TC.uF/V(DNS) R R CLK SCLK R R R R R R R R R R BCK SBCLK LRCK SLRCK SDT0 SDT0 SDT SDT SDT SDT R0 Cc LFE SL SR Rt Lt R.K RR R00.K LL TC 0U C00 TC 0U C FR FL R0 K MUTE R0 MUTEB C C R 0K C 0 C 0 R0 OK# C 0 R (NC) R DV R 0K(NC) M0 MCLK VL SDOUT VD SCLK LRCLK RST INL 0 VQ INR V REF_ FILT+ M U0 CS0 SCLK SBCLK SLRCK DV RST# C0 C 0 C C C 0 MCDT DV DV R (NC) R DV TC0 uf/v R 00K R 00K DV R0 00K R 00K DV OKL OKR OKL OKR R0 0K R K R 0K VD0 N VD N OK OK# - -. MPEG & SERVO Board

17 U0 HS00 K0 K0 K0 D0 N KEY KEY KEY S C0 R 00 IR TC0 00uF/V C0 C0 LEDST LEDCK LEDT R0 K R0 0K R0 0K R0 0K IR OSC DOUT DIN CLK STB K K K VDD NC SEG/KS 0 SEG/KS SEG/KS SEG/KS SEG/KS GR SEG/KS SEG/KS SEG/KS SEG/KS SEG0/KS0 0 SEG SEG/GR VDD GR GR GR GR 0 GR U0 PT LEDT LEDCK LEDST KEY KEY KEY S S S S S S S S G G G G G G G TC0 00uF/V S G G G G G G G S S S 0 S S S S S S LED0 ZDC-0YGB- G G G G G G G S S S S S S S S S XS0 XS Q0 00 R0 0K R0 LED0 R0 LEDB LEDB LED LED0 R LED0 R0 K LED Q0 00 R R. KEY SCN Board - -

18 R0 0K R K C0 0 R0 R0 0K R0 K C0 p R0 K R0 K TC0 uf/v TC0.uF/V TC0.u R 0ohm/W TC uf/v C0 R 0ohm/W TC uf/v C0 -V -V MIC0 L0 R 00K R 0 R K VD0 N VD0 N VD0 N DET R 0K +V C0 0 R 00K FROM MPEG BORD C0 TC 00uF/V C R.K R.K TC uf/v TC 00uF/V C R0.K R.K TC uf/v TL +V R.R R.R C OUT IN- IN+ VDD OUT IN- IN+ U0 TD0 R.K R.K R 0K R 0K C (DNS) C0 (DNS) TC0 00uF/V(DNS) TR C C R 0K R 0K R 0K R 0K JK0 HP -V TR TL -V +V XS0 XS0 * OK DET TO POWER ND V BORD OK U0 U0B +V XS0 XS MIC Board

19 U0 LM C L0 0uH/ C0 L0 0uH/ L0 0uH/ R K R0.K R0 0K R0.K R0 0 R0 ohm R0 0K/W R0 K/W U0 0 TC0 UF/0 TC0 uf/00v D0 HER0 C0 0/KV C0 0/KV L0 BC0 ~00V C0 0 C 0 C0 0 C 0 C 0 C0 TC0 0uF/V TC 00uF/V TC uf/0v TC0 000uF/0V TC0 000uF/0V TC0 000uF/0V TC0 000uF/0V D0 HER0 C0 0 TC0 0uF/V R /W D U0 L0 R0 K R0 M IN OUT U0 LM0 TC0 00uF/V S+V D0 HER0 ZD0.V D0 HER0 D0 SR0 D HER0 D HER0 +.V 0 T0 EI/ TC 00uF/V D0 N00 D0 N00 D0 N00 D0 N00 C0 C0 -V +V ZD0.V/W R /W OK -V 0 CN0 XS.0MM FL+ FL- -V DET S+V -V +.V +V S+V 0 CN0 XS.MM DET OK OPEN OPEN OPEN BC0 ~V L0 F0 T./0V R0 0KW BCN0 ~0V IN BCN0 SW-SPST OPEN L0 BC0 ~V - -. POWER Board

20 CC LFE SL SR L R RED WHITE L0 L0 L0 L0 L0 L0 C0 0 C0 0 C0 0 C0 0 C0 0 C0 0 0 JK0 V (B)OUT ()OUT RETURN BLUE I/O RETURN GREEN I/O RETURN RED I/O RETURN V-OUT (B)IN -COM ()IN FUNC SW CONT 0 NC RETURN BLK I/O TRTURN V-IN 0 JK0 VJS R0.K R0 R V0 00 V0 00 R0 R R0 R0.K +0V +0V PDT0 V0 00 R K R.K +0V PDT C R0 +0V V V Pr L0 L0 L0 Y Pb V GREEN BLUE RED B G R JK0 RC-0 BLCK TC0 000uF/0V TC0 0uF/V TC0 0uF/V L0 SPDIF R0 C0 L FCM L FCM C0 0 V R V R0 R VIN JK0 OPTICL V C SPDIF L L JK0 S-VIDEO JK0B V-OUT R0.R TC0 0uF R00 VIEDO TC0 0uF/V TC0 0uF/V Y C V V L L C 0P V C 0P C 0 C 0 C0 0 C 0 C 0 C 0 V LFE CC SR SL R L VIEDO Pb Y Pr PDT PDT SPDIF Y C PDT0 +0V XS0 XS0 TR TL - -. V OUT Board

21 DVSI Service Manual DVSI adopts the electronic scheme of DVSI, the appearance and function of DVS, and changes new UI and remote controller on the basis of DVS. For working principle of decode board and V board, please refer to DK00S Service manual... PCB board composition diagram of the player PCB board composition diagram of the player is shown in the figure...: Loader frame Small bracket Laser head LOD- LOD+ TROUT TRIN SL+ SL- LIMIT# SP+ SP- FC- FC+ TK+ TK- C D IO RFO B F V0 E VR-CD VR-DVD CD-LD MDI HFM DVD-LD -LD Power board K--0 Cn0 Cn0 MIC-DET OK -V +V +.V S+V VOICE-DET OK -V +V +.V LOD- LOD+ TROUT# TRIN# SL+ SL- LIMIT# SP+ SP- FC- FC+ TK+ TK- C D IO RFO F V0 XS0 XS0 XS0 CS0 Decode board XS0 00S-0 B E VR-CD VR-DVD CD-LD MDI HFM XS0 DVD-LD -LD XS0 HSYNC# VSYNC# IEC VIDEO_Y V VIDEO_C V VIDEO_V V VIDEO_Y V VIDEO_U V VIDEO_COMP FS Lt Rt TL TR SL MUTE SR Cc LFE V output board - XS0 -V OK DET MIC board S-0 XS0 Subsidiary board -0 IR VSTB VSCK VSD FS0 Panel S-0 RDS_MPX NC TUNER-R R TUNER-L Tuner DTS_DO DTS_CL DTS_DI DTS_CE H_R H_L Figure... PCB board composition diagram of the player - 0 -

22 .. Headphone amplifying circuit udio signals outputted by decode board are firstly sent to V board, and then one path of signals inputs to the socket XS0 of MIC board, shown in the figure..., firstly voltage dividend through R, R and R, R, then coupled by TC, TC, and then connected to pin and of headphone drive chip U0 (TD0), after inside operational amplifying, outputted by pin and of U0 (TD0), after being coupled by TC, TC, filtered by R, C, R and by R, C0, R, the output signals output. H_R R K TC uf/vr.k C 0 R TC 00uF/V JK0 PHONEJCK XS0 P.0 H_L V R K R.K R0.K R K R K C0 uf TC uf/v TC uf/v R.K.K IN+ IN+ IN- IN- OUT OUT VDD R.K V U0 TD0 TC0 00uF/V R 0K R 0K C (NC) C R (NC) R(NC) R R(NC) C (NC) C0 (NC) C 0 Figure... headphone amplifying circuit diagram.. MIC circuit. MIC circuit diagram is shown in the figure...: V MIC0 L0 OK R.K DET R0 K L0 TC0 uf/v C0 uf R0 K R0 C0 0 R0 K R0 0K R0 0K C0 0 R.K C U0B uf R.K C0 0 -V U0 C uf C uf(dns) C0 0 OK R 00K Figure... MIC circuit diagram - -

23 . Working principle: when there is MIC signal input, after L0 filtering and RC filtering circuit of C0, R0, signals are sent to pin of U0 () for operational amplifying and then outputted by pin of U0 (), after being coupled by C, input to pin of U0 for the second amplifying and then output OK signal from pin to decode board. DET is microphone detect signal, when U0 (MT) is detecting high level, it processes MIC signals.. Echo principle: From MIC board to decode board, OK signals are connected to U0 (CS0), after /D conversion, inputted to U0 (MT), now U0 (MT) detect DET microphone identifying signals and processes the inputted OK signals and then inputs this signal to U0 (CS0), after D/ conversion, input to operational amplifier U (0)... Panel control circuit. Panel control circuit block diagram is shown in the figure...: LED XS0-0 Subsidiary board Seg0 Grid Seg KEY PT STB CLOCK DT Panel indicator light XS0 IR Remote control receiver Figure... panel control circuit block diagram. Working principle Realize buttons function: when users are operating machine, button matrix circuit will produce a button function code that transmits to the main CPU inside decode chip, CPU performs the corresponding switch to the module inside system, and a signal will produce at the same time to control OSD and panel display part and makes the relevant display. Display drive: when the serial signals conveyed by decode chip are transmitting to panel IC(PT), IC performs LED drive according to the information transmitted from decode and displays the relevant content (controlled by software). Indicator light control circuit: this control is performed by FSO pin of decode chip to indicator light. Definition and function of main jacks of panel: - -

24 Xs0 is connected to subsidiary panel, and he function is to transmit button control signal and indicator light control voltage. XS0 is connected to decode board and the jack that communicates with decode system, in which IR is remote control signal output pin, is panel power supply. DT is data transmission pin (dual direction) and controlled through STB. CLOCK is working clock signal input displayed by panel, and panel light is controlled by PT... Power circuit. Power circuit block diagram is shown as in the following figure...: Rectification Power grid filtering Protector tube Filtering HOST Switch IC bsorption loop VIPER Feedback winding Photoelectric coupling Transformer Rectification Rectification Rectification Rectification Rectification Rectification Filtering Filtering Filtering Filtering Filtering Filtering LED+V +V +.V -V FL- FL+ Voltage -V regulating circuit Power socket TLV Sampling circuit Figure... Power circuit block diagram. Working principle () Power grid filtering circuit: various electromagnetic radiation exists in surroundings, so it will produce interference to the inputted C power, and the function of power grid filtering circuit is to filter these interference to make those that enter bridge rectification circuit are pure 0V C power. () Bridge rectification and filtering circuit: the function of this circuit is to converse electric supply into DC power, the voltage after being rectified and filtered is. times of input power, so the DC voltage at the two ends of TC0 is about equal to 00V () bsorption loop: for power is always working in on/off state and will produce very high peak voltage, in order to well protect switch IC, a peak absorption loop is added. () Filtering circuit: the function is to produce a stable and slamm-wave DC voltage. In filtering circuit, " type filter is mostly adopted. The feature of capacitor filtering is high load resistance, when current is small, filtering is obvious, but inductor filtering is small load resistance, when current is large, filtering is obvious. To compose capacitor into " type filter can make better filtering effect. - -

25 () Feedback loop: the time length of on and off within the same cycle inside switch module VEPR is decided by feedback loop. Feedback loop performs sampling to +.V output stage voltage, when output stage voltage is too high, the sampled voltage is on high side, through feedback loop, to change the duty ratio of pin signal of VEPR and reduce on time, and output voltage begins to reduce. When output voltage is too low, the sampled voltage is on low side, through feedback loop, to make duty radio of VEPR increase, output voltage increases, through the function of feedback loop, power board is made to output stable voltage. The used LM in this power is a.v comparator, sampling voltage is compare with this.v voltage, when sampling voltage is more than.v (means that output voltage is on high side), LM is on, light emitting diode in photoelectric diode begins to emit light to make the other end of photoelectric coupler begin to be on, light emitting diode is stronger, the on degree bigger, the on time of switch module VEPR decreases, output voltage begins to decrease. When sampling voltage is less than.v (means output stage voltage is on low side), Lm is cut off, on time of VEPR increases, output voltage increases. Thus through auto control function of feedback loop, power board is made to output stable voltage. - -

26 .. PCB board. Surface layer of KEY SCN Board LED0 U0 K0 K0 K0 R0 O G V XS0 KEY SEG GRID SEG0 LED0 TC0 XS0 IR STB CLOCK DT DVD 00/0/ S-0 TC0 - -

27 . Bottom layer of KEY SCN Board C0 C0 R0 R0 C0 C0 C0 R0 R0 R0 C0 C0 Q0 R0 R0 U0 ZD0 C V VD0 ZD0 ZD0 ZD0 C0 ZD0 C C C R C0 ZD0 ZD0 C - -

28 . Surface layer of MPEG & SERVO Board - -

29 . Bottom layer of MPEG & SERVO Board - -

30 . Surface layer of MIC Board R L XS0 -V OK DET XS0 V S DVD 00/0/0 TC0 R JP0 U0 JP0 TC TC TC0 JP0 R TC TC TC0 JP0 S-0 TC JP0 TC MIC0 JK0 - -

31 . Bottom layer of MIC Board R R C R R U0 C0 R R R0 C R R R0 R C R R C0 R Q0 ZD0 R0 R R0 C0 R0 R0 C0 L0 R R0 C0 R0 C0 R0 C0 R C C0 R0 C0 R C C JP0 C R C0 C C L0-0 -

32 . POWER Board G0 BC0 BCN0 L N ~0V CUTION: FOR CONTIUED PROTECTION GINST RISK OF FIRE REPLCE ONLYWITHSME TYPE F0 T. L0V FUSE G0 D0 BCN0 ~0V D0 BCN0 T.L0V F0 F0 R0 BC0 BC0 L0 D0 D0 TC0 R0 C0 U0 C0 C0 C0 R JP R0 HIGH VOLTGE L0 D0 TC0 BC0 U0 D0 R0 R0 G0 T0 R0 K R C C U0 C D0 C R0 TC0 D0 JP0 C D0 D D JP TC R D TC R0 JP TC0 R TC JP JP JP LEDV JP0 L0 TC JP0 JP0 JP ZD0 SV CN0 L0 L0 R +.V +V E TC0 L0 TC0 C0 TC0 JP0 Q0 JP0 B C C C -V CN0 C0 TC0 JP0 ZD0 RJP K- TC0 DVD 00// JP0 G0 OK DET R R CN0 JP0 G0 JP0 DET OK -V +V +.V FL+ FL- -V - -

33 MPTH DVN SD SCL 0 PSWN FIN LVIN 0 SCOUT CIN MRO OSCI MPXIN VDD VDDD VREF MD VSSD VSS OSCO TCON U S R 0 R 0 R 0 R 0 R 0K R 0K R 0K R 0K R0 0K R K R 00 C 0P C0.n C0 00n C P C P C0 0P TC.U TC U TC 0U/V ZD0 V X0.MHZ C0 0.U C0 0.U RDS_MPX DVNIN SD SCL RDSCE R 0 RDSID _DTS R R 0 R 0 R0 0 R 0 R 0K R00 0K R0 0K R 0K RDS_MPX TUNER-R TUNER-L DTS_DO DTS_CL DTS_DI DTS_CE _DTS R0 0 TC 0uF/V C L 00 U 0 UB 0 R 0K R0.K R.K R 0K R R R 00K R 00K R.K R.K TC 0UF/V TC 0UF/V C 0 C CP C CP C CP C CP C 0 -V Q SC-Y Q SC-Y LL RR MUTE- TL TR R0 0K(DNS) R 0K(DNS) C0 0 OK L 00 TC 0U C _DTS X0 X X X Y0 Y Y Y INH 0 B VEE X Y VDD VSS U0 CD0 R 00K R 00K TUNER-L R 00K R 00K TUNER-R -V FL FR L R OB O L L TC0 0UF/V C C TC 0UF/V R0 K R K R 0K Q0 00 R0 K R 0K Q0 00 R K O O OB OB R0 K R0.K R TUNER_ON Q0 0 Q0 00 R K 0 XS0 XS RDS_CLK RDS_DT R 0K R 0K RDS_ RDS_ R0.. circuit diagram. MPEG & SERVO Board R0 - -

34 DVD CEQP 0 DVDB DVDC DVDD OSP OSN DVDRFIP DVDRFIN M MB MC 0 MD S SB SC SD CDFON CDFOP TNI TPI MDI 0 MDI LDO LDO VDD VREFO S VREFO 0 V0 TEO FEO USB_VSS RFLVL/RFON CSO/RFOP TEZISLV OP_OUT OP_INN OP_INP FOO TRO USBM TROPENPWM PWMOUT/V_DIN 0 USB_VDD FMO DMO HIGH0 HIGH HIGH HIGH HIGH HIGH 0 HIGH HIGH DVDD D PLLCP D D PLLVSS PLLVDD D D D D0 DVDD IO0 IO IO IO IO DVDD 0 IO IO IO 0 IO IO0 IO LE 0 IOOE IOWR IOCS UWR URD DVDD UP_ UP_ UP_ 00 UP_ 0 UP_ 0 UP_ 0 UP_0 UP_ 0 UP_ 0 UP_ 0 RFVDD RFRPDC DVDD 0 ICE 0 PRST 0 IR INT0 DVDD DQM0 DQS0 RD RD RD RD 0 RD RD RD RD0 RD RD DVDD RD YUV0/CIN FS VREF 0 DCVDDC RD RD RD RD RD0 RD DVDD RD RD 0 DQM DQM RD RD RD DVDD RD RD RD 0 RD0 DVDD RD/SDT R R R R R 0 R R RCLK CKE DVDD RCLKB RVREF/V_DIN DVDD R R 0 R R0 R0 B B0 DVDD RCS RS 0 CS RWE DQM DQS RD RD RD0 RD DR 0 RF IREF SVDD RFGC JITFN JITFO 0 LPFOP LPFIN CRTPLP HRFZC LPFIP CEQN RFRPC S_VREFN DCVSS S_VREFP S_VCM 0 DCVDD PLLVDD LPFON PLLVSS MC_DT SPDIF SDT DVDD SDT 0 SDT RF SDT SDT0 CLK LRCK BCK DVDD 0 SPBCK/SDT SPLRCK 0 SPDT 0 SPMCLK 0 DVDD HSYNC/V_DIN 0 YUV/SDT 0 VSYNC/V_DIN 0 YUV/R 0 YUV/B 0 DCVSS 0 YUV/G 00 DCVDD YUV/CVBS DCVSSB YUV/C DCVDDB YUV/Y DCVSSC IDCEXLP USBP FG/V_DIN TDI/V_DIN TMS/V_DIN TCK/V_DIN 0 TDO/V_DIN D IO/V_DIN0 XTLO XTLI RFVDD U0 MTC C0 uf C0 uf C0 uf C0 uf C0 DNS C0 0p C B D RFO R0 R0 R0 R0 C B D E F MDI MDI LDO LDO RFOP RFON VP V0 VP FEO TEO TEZISLV OPO OP- OP+ DMO FMO TROPEN C0 R0 R0 R0 C0 C0 TRO FOO L0 V USBVDD DIN TROUT TRIN STBY TRCLOSE V C C 00pF R R0 K R 0K C 0pF C 0pF C C0 pf R0 K R0 0K DMSO FMSO TRSO FOSO VP VP DIN L0 R V PWR# 0 0 PCE# PRD# D0 D D D D D D D 0 V VSCK VSD VSTB SCL SD RXD TXD URST# IR DQM0 DQS0 DQ DQ DQ DQ DQ DQ DQ DQ0 DQ DQ R K DQ DQ0 DQ DQ DQ DQ RS# CS# WE# DQM LIMIT CS# B0 B DM0 DM0 DM DM DM DM DM DCKE DCLK DM DM DM DM DM RDS_DT RDS_CLK RDSCE RDSID DVNIN MUTEB TUNER_ON OB DTS_DO DTS_CL DTS_DI DTS_CE O R C Y0 FS V V L0 DCVDD DV C TC0 0uF/V Y DV Y Y Y Y Y VSYNC# HSYNC# RGB_SWITCH FS FS0 R K LRCK BCK CLK R (DNS) R (DNS) R (DNS) SDT0 SDT SDT V R0 (DNS) RESET# SPDIF RFV XI XO JITFO JITFN C 0.uF TC0 0uF/V PLLVDD C 0.0uF C0 0.0uF C uf DCVDD RFVDD VREFN VREFP C 0pF C 000pF R 00K C C 0.0uF C C C R K C VP VDD V C 00pF R 0K JITFN JITFO L0 L0.R L0 L0 L0 C C C C RFV PLLVDD DCVDD RFVDD RFSVDD C C C0 uf VREFN VREFP C TC0 uf/v C TC0 uf/v C TC0 uf/v C0 C C C C C C C C C C C C C V L L VDD DV 0 0 XS0 P0.mm C L L L L L L0 L0 L0 L0 0uH L0 L0 L0 0uH L L0 L L L L C0 TC0 0uF/V C E V0 SB-S V0 SB-S R0 R0 TC0 uf/v TC0 uf/v LDO-V LDO-V LDO LDO R0 L0 MDI F L B RFO IO D C V0 R0 0K R0 00K R 0K R0 00K V0 SK0-S V0 SK0-S V0 0-S IO L C0 V RFV R 0K R 0K R 0K C0 C0 C0 C0 TC0 uf/v R0 R R0 R R 0K R0 R R0 R C0 VINFC CF CF VINSL+ VINSL- VOSL VINFFC 0 P P 0 VOSL- VO+ VOFC- VOFC+ VOTK+ VOTK- VOLD+ VOLD- P VNFTK 0 P PRE VINLD CTK CTK VINTK BIS STBY U0 B TRSO VP STBY SL+ SL- FMSO MO_ MO_ SP- SP+ VP FOSO DMSO L0 R 0K R R R R R0 0K R 0K R 0K R 0K R C0 00pF DIN OP- OP+ VP SP- OPO C0 DNS V0 00 V0 00 V0 0 V0 0 R.K R.K R 0K R.R\/W TC0 uf/v TC0 uf/v LOD+ LOD- TRCLOSE V0 0-S TROPEN (TRCLOSE) (TROPEN) (TRCLOSE) TROPEN XS0 P.0mm LOD- LOD+ TROUT TRIN C0 SP+ SL+ SL- LIMIT XS0 XS0 L0 DV R TDI TMS TCK TDO R0 0K DV C TC 0uF/V L DV R0 R C0 00pF R 0K R0 0K DV RFSVDD R DQS0 R R R PWR# PCE# PRD# DWR# DCE# DRD# MDT R R C C TC uf/v C TC uf/v R VOICE-DET. MPEG & SERVO Board - -

35 L L0 L R0.K C pf IR VSCK VSTB VSD XS0 XS0(DNS) DV RXD TXD C TC0 uf/v C C SD L DV C 0 TC 00uF/V VD0 N R 0K R K R R U0C HCU0 URST# DV DC/NC RST_/NC WP/RST_ VSS RST/WP SCL SD U0 TCX00 SD SCL C DV R R0 C pf C pf C pf RY/BY NC NC 0 NC 0 WE RESET 0 DQ 0 DQ DQ0 DQ DQ DQ/- DQ DQ DQ BYTE Vss DQ DQ DQ DQ 0 DQ Vcc DQ0 OE Vss DQ CE 0 U M_FLSH(TSOP) 0 0 D D D D D D D VD D D D0 D D D D D0 DRD# DCE# UP[0..0] UPD[..0] R.K(DNS) VP R0.K R.K R.K VD C TC uf/v R VD DV 0 L0 (DNS) R (DNS) L L C pf XS0 XS0 C0 0(DNS) C 0(DNS) U0 HCU0 X0 MHz U0B HCU0 R 00K C pf C pf R (DNS) MHZ C C 0pF(DNS) R (DNS) R (DNS) XI R XO XTLI R U0F HCU0 0 U0E HCU0 SPDIF IEC R0 (DNS) R R0 C0 0 C pf L.uH V R C0 0 C0 pf L.uH V R C0 0 C pf L0.uH V R C 0 C pf L.uH V R0 C 0 C pf L.uH V R C 0 C pf L.uH V L L L L L L Y Y Y Y Y Y 0 0 0/P B0/ 0 B/ CLK CKE /CS /RS /CS /WE DQML DQMH NC NC 0 VSS VSS VSS DQ0 DQ DQ DQ DQ DQ 0 DQ DQ DQ DQ DQ0 DQ DQ DQ 0 DQ DQ Q Q Q Q VSSQ VSSQ VSSQ VSSQ U SDRM M DM0 DM DM DM DM DM DM DM DM DM DM0 M B0 #B SDCLK SDCKE DCS# DRS# DCS# DWE# DQM0 DQM DQ0 DQ DQ DQ DQ DQ DQ DQ DQ DQ0 DQ DQ DQ DQ DQ DQ SD SD R R R R DM B C L L L L0 L L VOICE-DET OK C C C0 C TC0 0uF/V TC0 0uF/V -V DV C TC 0uF/V L DV 0 XS0 XS MUTE L VD0 N00 VD0 N00 IN OUT U0 LMMP-.(DNS) C TC0 0uF/V R.K R.K V DV R0 R (DNS) R (DNS) 0 R R R R R R R R R R R R DCLK DCKE CS# RS# CS# WE# L VV DWR# TC 0uF/V C FS0 C pf(dns) L.uH(DNS) C C C0 C L0 R (DNS) DV VV V VV VIDEO_U VIDEO_V VV VIDEO_C V VIDEO_Y VV V VIDEO_COMP VV VIDEO_Y V VD0 N VD N VD N VD N VD N VD N VD N VD N VD N VD N VD0 N VD N VV V V C C C0 TC0 0uF/V VV V R (DNS) XI URST# Q0 0 V LFE Cc SR SL Rt VIDEO_COMP VIDEO_U VIDEO_V VIDEO_C VIDEO_Y IEC HSYNC# VSYNC# R (DNS) R FS R (DNS) R VIDEO_Y R TL TR Lt XS0 XS0 R MUTE-. MPEG & SERVO Board - -

36 R0 R0 0K R0 R K VD0 N R0 K VD0 N -V MUTE- TC 0uF/V TC uf/v R0 0K Q SC-Y Q 0 Q 0 C (DNS) C C (DNS) SW /C SR# SL# R L TC 0uF/V TC 0uF/V TC 0uF/V TC 0uF/V TC 0uF/V TC0 0uF/V R0.K R.K C C 0 C 0 R 0K R 0K C0 0 C 0 C (DNS) R.K R.K R.K R.K C C 0 C 0 R 0K R.K R.K C 0 C 0 R 0K R.K R.K C 0 C 0 R 0K R 0K C 0 C 0 R.K R0.K U 0 UB 0 U 0 U0B 0 U0 0 UB 0 -V -V -V -V -V -V TC 0uF/V TC 0uF/V TC 0uF/V TC 0uF/V TC0 0uF/V TC 0uF/V CH-L CH-R CH-SL CH-SR CH-C CH-SW R K R K R0 K R K R K R K R K R K R 00K R 00K R 00K R 00K MUTE- Q0 SC-YS Q0 SC-YS Q0 SC-YS Q0 SC-YS R K R K R K R K R 00K R 00K Q0 SC-YS Q0 SC-YS C C C0 C C C -V SDT SDT SDT0 SLRCK SCLK SBCLK SCL SD RESET# RS LS LFE# C# R 0K C 0 OK R 0K R.K R.K R.K R.K R.K R.K C C C0 C C C VOICE-DET VLS SDIN SDIN SDIN SCLK LRCK MCLK VD RST 0 SCL SD CS VLC MUTEC OUT OUTB MUTEC OUT OUTB V OUT 0 OUTB MUTEC VQ FILT+ M U0 CS0 C C DV MUTE C TC 0uF/V C TC 0uF/V C TC 0uF/V R TC 0uF/V MUTE MUTE R RS L LS LFE# C# MUTE Q 0 R0 K R0 K VD0 N VD0 N VD0 N MUTE MUTE TC.uF/V(DNS) R R CLK SCLK R R R R R R R R R R BCK SBCLK LRCK SLRCK SDT0 SDT0 SDT SDT SDT SDT R0 Cc LFE SL SR Rt Lt R.K RR R00.K LL TC 0U C00 TC 0U C FR FL R0 K MUTE R0 MUTEB C C R 0K C 0 C 0 R0 OK# C 0 R (NC) R DV R 0K(NC) M0 MCLK VL SDOUT VD SCLK LRCLK RST INL 0 VQ INR V REF_ FILT+ M U0 CS0 SCLK SBCLK SLRCK DV RST# C0 C 0 C C C 0 MCDT DV DV R (NC) R DV TC0 uf/v R 00K R 00K DV R0 00K R 00K DV OKL OKR OKL OKR R0 0K R K R 0K VD0 N VD N OK OK# - -. MPEG & SERVO Board

37 K0 Play/Pause K0 Stop R0 K TC0 00uF/0V OSC DOUT DIN CLK STB K K K VDD NC SEG/KS 0 SEG/KS SEG/KS SEG/KS SEG/KS GR SEG/KS SEG/KS SEG/KS SEG/KS SEG0/KS0 0 SEG SEG/GR VDD GR GR GR GR 0 GR U0 PT DT CLOCK STB KEY Seg Seg Seg Seg Seg Seg Grid Grid Grid Grid Grid Grid Grid Seg Seg Seg U0 HS00BV C0 IR TC0 00uF/0V R0 0 R0 0K R0 0K R0 0K R0 0K DT CLOCK STB C0 0 K0 Open/Close C0 C0 (DNS) C0 (DNS) C0 (DNS) C0 KEY KEY Seg Seg0 STB CLOCK DT IR XS0 P/.0mm LED KEY Seg C0 C0 R.K XS0 XS0.0 K VD0 N C C C R0 K B C E Q0 00D LED0 R0 R BLUE LED LED C K ZD0.V/0.W K ZD0.V/0.W K ZD0.V/0.W K ZD0.V/0.W K ZD0.V/0.W K ZD0.V/0.W Grid Grid Grid Grid Grid Grid Grid Seg Seg Seg Seg Seg K ZD0.V/0.W Seg0 Grid Grid Grid Grid Grid Grid Grid Seg/ks Seg/ks Seg/ks 0 Seg/ks Seg/ks Seg/ks Seg/ks Seg/ks Seg/ks LED0 TOS-BY-B0 Seg Seg Seg Seg C Grid. KEY SCN Board - -

38 R.K C0 0 R0 U0B U0 C0 0 R.K R0 0K R0 0K C0 0 R0 K C0 0 R0 K -V R 00K R TC uf/v C0 R TC uf/v C0 -V -V L0 L0 OK -V OK DET XS0 P.0mm C0 uf C uf C uf C uf(dns) TC0 00uF/V C0 (NC) R.K R.K TC uf/v C (NC) R.K R.K TC uf/v H_L R R(NC) R R(NC) OUT IN- IN+ VDD OUT IN- IN+ U0 TD0 R.K R0.K R 0K R 0K C 0 C 0 H_R C (NC) C (NC) JK0 PHONEJCK R K R K R K R K TC 00uF/V XS0 P.0 V DET R.K V OK TC0 uf/v V R R 0m. C0 uf R0 K ZD0.V/0.W Q0 00D C V MIC0 TC0 000uF/0V C0 R0 K TC uf/v R0 0k R0 0k. MIC Board - -

39 -V +.V +V S+V MIC-DET OK OK +.V -V 0 CN0 P.0mm(DNS) FL+ FL- -V MIC-DET +V U0 LM C L0 0uH/ C0 L0 0uH/ BC0 ~V L0 JLB uh +-0% F0 T.L0V R K R0 0K/% R0.K/% R0 R0 R R0 K/W U0 PH TC0 uf/0v TC0 uf/00v D0 HER0 C0 0/KV C0 0/KV L0 FL+ FL- -V BC0 ~0V C0 TC0 0uF/V TC 00uF/V(DNS) TC uf/0v TC0 000uF/0V TC0 000uF/0V D0 HER0 TC0 0uF/V R.K R0.K(DNS) R0 0K /W D0 HER0 ZD0.V/0.W D0 HER0 D HER0 D HER0(DNS) +.V TC0 00uF/V D0 N00 D0 N00 D0 N00 D0 N00 C0 C -V +V ZD0 0V/0.W VDD D S D D D S U0 VIPER R.K BCN0 ~0V(DNS) L0 0uH/ TC0 000uF/0V(DNS) S+V To Mpeg Board To Microphone Board 0 T0 BCK--S L0 0uH/ TC0 000uF/0V TC 000uF/0V D HER0 C0 BC0 ~0V (DNS) BC0 ~0V D0 HER0 TC 000uF/0V CN0 P.0mm LED+V LED+V R0 (DNS) R K(DNS).V R0 K JP0 0 CN0 P.0mm R C (DNS) C (DNS) Q0 0D BCN0 SW-SPST(DNS) C BCN0 ~0V F0 T.L0V R0 (DNS) R RK(DNS) C (DNS) R K(DNS) C (DNS). POWER Board - -