Comparison of Circuit Topologies for Active Power Decoupling toward High Power Density

Transcription

1 Comparison of Circuit Topologies for Actie ower Decouplg toward High ower Density Jun-ichi toh, Tomokazu Sakuraba, Keisuke Kusaka, Hiroki Watanabe and Keita Furukawa Department of Electrical Engeerg Nagaoka Uniersity of Technology, NUT Niigata, Japan Abstract This paper discusses how to achiee high power density with high efficiency for sgle-phase AC connected erter with actie or passie power decouplg circuit. An erter connected to a sgle-phase grid requires a power decouplg deice to compensate power pulsation with twice the grid frequency. As the alternatie to an electrolytic capacitor connected to DC-lk, actie buffer circuits with bi-directional chopper and a flyg capacitor conerter (FCC) with power decouplg capability hae been ealuated terms of long lifetime. n this paper, areto optimization is used to compare the character of the power decouplg circuits terms of an efficiency and a power density. The olume of capacitors the FCC with ceramic capacitors can be reduced by 54.6% compared to bulky electrolytic capacitors. As a result, when the 4-V SiC- MOSFETs are used for the FCC at 5 khz, a maximum power density of 5.3 kw/dm 3, which is.3 times higher than the power density of the passie topology, can be obtaed. Furthermore, the total power loss is reduced by.5% comparison with that of the conentional conerter. Keywords sgle-phase erter, power ripple compensation, power density design. NTRODUCTON n recent years, sgle-phase grid connected conerters hae been studied actiely as the power conersion systems (CSs) for photooltaics systems or battery energy storage systems and so on. nstantaneous power of the sgle-phase grid oscillates at twice the grid frequency whereas the put power is constant. As a result, a power ripple with twice the grid frequency occurs at the connection pot between the chopper and the erter. n order to absorb this power ripple, bulky electrolytic capacitors are used conentional circuits. Howeer, the electrolytic capacitor limits the lifetime and size reduction of the CS. As an alternatie power decouplg method, an actie power decouplg which consists of small capacitors, ductors and switchg deices has been proposed [-3]. As a result, the CS with long lifetime is expected by usg film capacitors or ceramic capacitors as the buffer capacitor. Howeer, an additional ductor and switchg deices for the buffer circuit are required to control the buffer capacitor oltage. By creasg the switchg frequency of the actie buffer circuit, the ductance can be reduced, howeer the size of the heatsk becomes larger due to crease of the switchg loss. As a result, a relationship between the ductor olume and the heatsk olume dicates the trade-off characteristics. Thus, the buffer circuit should be designed and operated at an adequate switchg frequency to maximize the power density. n [] and [3], the ceramic capacitors are applied for the power decouplg circuit order to achiee a high power density. n [], the power loss mechanism is analyzed order to improe the system efficiency of the actie buffer circuit. Howeer, past literatures hae not clearly mentioned the conditions to achiee a higher efficiency and a power density than the electrolytic capacitor. This paper clarify the conditions to achiee the higher power density and the higher efficiency by comparg among the electrolytic capacitor and the actie power decouplg topologies. First, the design flow for the passie topology usg the electrolytic capacitor and the actie buffer topology [4-5] usg the ceramic capacitor is troduced. Second, from the design flowchart and the specifications of the commercially aailable products, the power density and the efficiency of the actie power decouplg circuit are ealuated by areto optimization. Fally, the comparisons of a total loss and a total olume at the maximum power density pot are discussed order to achiee a high efficiency and a high power density.. CRCUT CONFGURATON AND DESGN METHOD A. assie ower Decouplg Circuit Fig. shows the circuit configuration of the passie power decouplg method usg an electrolytic capacitor. Table shows the circuit specifications. This paper ealuates the olume of the buffer circuit based on the ripple current the DC-lk. n order to ealuate the ripple current, a power supply with an ternal impedance R is considered to emulate the put of the boost chopper connected to V. n the passie topology, the bulky electrolytic capacitor is connected to absorb twice grid frequency. The ripple current restricts the lifetime of the electrolytic capacitor. Therefore, the electrolytic capacitor, which has the allowable ripple current higher than the calculated ripple current, is selected this paper. The current which flows to the electrolytic capacitor cludes not only the power ripple component but also the switchg frequency component from the erter. The

2 capacitor ripple current is the function of the put power factor and the modulation dex, which is a nonlear alue [6]. Then, the effectie alue of the capacitor ripple current is expressed by rms _ cap cap ( φ m) m K, (), where, m is the maximum alue of the put current, φ is the put power factor, m is the modulation dex and K cap (φ, m) is the coefficient regardg ripple current the DC-lk which is obtaed by simulation. Fig. shows the alue of K cap (φ, m) which is obtaed by the ration between the put current and the ripple current with circuit simulation as follows. n general, the put power factor of the grid-connected erter is approximately unity. The modulation dex, which expresses the ratio of the dc-lk oltage and the maximum put oltage V m, is.74 this case. Therefore, from Fig., K cap (,.74) is.56. With the frequency multipliers, the allowable ripple current is calculated by n Hz rms _ cap (), nsw K Hz K sw where, Hz is the effectie current whose frequencies are twice the grid frequency, nsw is the effectie current at the switchg frequency, K Hz and K sw are the frequency multipliers at Hz and the switchg frequency, respectiely. An electrolytic capacitor, which has the allowable ripple current higher than the result of (), should be required. B. Boost Type Actie Buffer Circuit Fig. 3 shows the circuit configuration of the boost type actie buffer circuit. The actie circuit consists of a boost chopper and a small capacitor to absorb the power ripple DC-lk. The actie buffer circuit achiees long lifetime because the film capacitors or the ceramic capacitors are used as the buffer capacitor. The prciple for the power decouplg between the DC and the AC sides is explaed as follows. Fig. 4 shows the relationship among the put power p, the put power p and the compensation power p buf the actie buffer. The put stantaneous power is shown (3) when the put current is the susoidal wae with unity power factor. Vm m p ( cosω t) (3), where, V m is the peak oltage of the sgle-phase grid and ω is the angular frequency of a grid. From (3), the twice grid frequency power ripple occurs the DC-lk. n order to absorb the power ripple, the stantaneous power p buf the actie buffer is controlled accordg to Fig.. assie power decouplg circuit. Table. System specification. arameter Rated power Output oltage Output frequency ower factor Symbol DC lk oltage 38 V nput impedance R 3.3 Modulation dex m.74 Ambient temperature T a 4 C Junction temperature T j 4 C CS 3 C/dm 3 pbuf Vm m cosω t (4), Fig. 5 shows the design flowchart order to optimized design the boost type actie buffer. First, the capacitance of the buffer capacitor is calculated based on an aerage oltage and a oltage oscillation range of the buffer capacitor. Then, the capacitor olume Vol Cbuf is determed from the commercially aailable products. The switchg deice is decided based on the maximum oltage of the buffer capacitor. n this paper, the switchg deice, which has a ratg oltage of V, is used. Second, the boost ductor is designed based on the switchg frequency f sw and the ductor ripple current. The V f cos Value 6 kw V 5 Hz. nput oltage V 5 V cos.8 cos.6 ower factor cos. cos. cos Modulation dex m Fig.. Current ripple coefficient for the calculation of the ripple current flowg to the electrolytic capacitor. The ripple current is function of the put power factor cosφ and the modulation dex m.

3 olume of the boost ductor is estimated accordg to Area roduct concept [7]. Third, the heatsk olume is calculated from the thermal resistance which depends on the conduction loss loss_cond and the switchg loss loss_sw of the switchg deices. Fally, the areto optimization is obtaed through aryg the switchg frequency order to reeal the maximum power density pot. The capacitance is decided from the relationship between the storage energy and the capacitor oltage. From the storage power (4), the stantaneous power p buf the actie buffer is represented by V c Vc c ω Cbuf Vae Δ Vae Δ (5), R i dc Vm i buf -leel erter Boost type actie buffer Fig. 3. Boost type actie buffer circuit. m SW SW p C filter Vm m i ( cos ω t) where V ae is the aerage oltage and ΔV c is the oltage oscillation range of the buffer capacitor. n the passie topology circuit with the bulky electrolytic capacitor, the power storage is achieed by the large capacitance. On the other hand, the actie buffer, the storage power is achieed through the large ΔV c [8]. This is the prciple to reduce the capacitance with actie power decouplg method. Then, the capacitance to compensate the power ripple is calculated by C c buf (6), ωvaeδvc The buffer capacitor requires the large V ae and ΔV c for reducg the capacitance. Howeer, when the buffer capacitor oltage is creased, the switchg deice with the high ratg oltage is required. n this paper, the switchg deice, which has the ratg oltage of V, is selected as the peak capacitor oltage of 8 V. The boost ductor is designed based on an allowable ripple current Δi. The ductance becomes the maximum alue when the difference between the dc-lk oltage and the buffer capacitor oltage reaches the maximum. Thus, the ductance of the boost ductor is proided by buf ΔVc Vae Vdc Vdc (7), Δi ΔV f sw c Vae The ductor olume depends on many parameters of the components. There are seeral ways to select the core for the ductor. n this paper, the boost ductor is designed by Area roduct concept usg the wdow area and the cross-sectional area [7]. Therefore, the olume of the boost ductor Vol buf is calculated by Vol 3 4 buf max buf K K B (8), u maxj put f a i V i i Fig. 4. Sgle-phase power ripple compensation. Start where, K is the olume coefficient dependg on the shape of cores, max is the maximum current flowg to the ductor, K u is the fill factor of the wdow, B max is the maximum flux density of the core, and J is the current density of the wire. The switchg deices require a coolg system such as heatsks and fans. n general, the coolg system is designed based on the thermal resistance. CS (coolg system performance dex) is troduced to estimate the olume of coolg system [9]. CS means the coolg performance per unit olume of the coolg system. The coolg system is miaturized when CS become higher. The olume of the coolg system Vol heatsk is proided by Vol heatsk Decision V ae, V c, V ae_, Calculation and c, Vol Cbuf from Fig. 8 Selection Switchg deice Switchg frequency f sw khz~ khz Calculation buf and, Vol buf by Eq. (8) Calculation Conduction loss and Switchg loss, Vol heatsk by Eq. (9) Calculation total olumevol total by Eq. (33) Calculation ower density power, Efficiency by Eq. (3), (34) End Fig. 5. Designg flow for actie buffer circuit. Rth( f a )CS (9), where, R th(f-a) is the thermal resistance of the coolg system f sw

4 which is gien by R i dc R T T (), ( ) j a th( f a ) Rth( j c ) Rth( c f ) loss where, T j is the junction temperature of the switchg deice, T a is the ambient temperature, R th (j-c) is the junction-to-case thermal resistance and R th (c-f) is the case-to-f thermal resistance. The total loss loss, which is composed of the conduction loss loss_cond and the switchg loss loss_sw from the switchg deices, is calculated by loss (), loss _ cond _ buffer loss _ sw _ buffer where, loss_cond and loss_sw are gien by loss _ sw_ buffer loss _ cond _ buffer E dcd md T T i r on _ buffer dt ( eon eoff ) f sw T T i dt c (), (3), respectiely, where, T is the period of the grid, r on is the onresistance of the switchg deice, f sw is the switchg frequency of the actie buffer, e on and e off are the turn-on and turn-off energy per switchg referred from a datasheet, respectiely, E dcd and md are the oltage and the current under the measurement condition of the switchg loss described the datasheet. The buffer capacitor oltage c and the boost ductor current i are expressed by c ΔVc Vae s( ω t) (4), V d i ae c Cbuf V dt (5), dc respectiely. From (3), the crease the switchg frequency leads to the crease the switchg loss. The coolg performance can be improed by fans to mimize the heatsks. Howeer, the system lifetime is limited by these fans. Thus, this paper, the coolg system is designed on the assumption that the natural coolg is applied. The small filter capacitor is necessary order to absorb the ripple current at the switchg frequency. The impedance of the filter capacitor should be sufficiently small agast the ternal impedance R. Thus, is designed by C f πf R (6), sw_ where f sw_ is the switchg frequency of the erter. C. Buck Type Actie Buffer Circuit Fig. 6 shows the circuit configuration of the buck type actie buffer circuit. n this circuit, the capacitor oltage is lower than the DC-lk oltage. The buck type actie buffer can still be designed through the flowchart Fig. 5. The buffer capacitor is designed by (6). Howeer, the DC lk oltage limits the peak oltage of the buffer capacitor. As a result, the buffer capacitance has to be larger than the one of the boost type actie buffer. The ductance of the smoothg ductor reaches the maximum alue when the capacitor oltage is a half of the put oltage. Thus, the ductance is designed by V dc buf (7), 4Δi fsw where, i is the current which flows to the smoothg ductor which is proided by i SW SW dc Cbuf cos( ω t) (8), dt V The olume of the smoothg ductor is estimated by Area roduct of (8). The loss generated by the switchg deices is calculated by substitutg (8) to (), () and (3). ae D. Flyg Capacitor Conerter Fig. 7 shows the circuit configuration of a flyg capacitor conerter (FCC) with a capability of the power decouplg []. This circuit consists of a flyg capacitor c, a boost ductor and four switches. The power ripple is absorbed by the flyg capacitor whose oltage oscillates at twice the grid frequency. This circuit has no additional ductor for a buffer oltage control. The duty ratio is decided from the sum of the duties of a current control for the FCC, a power decouplg control and a nonterference control. Therefore, the duties for S and S are obtaed by V d { cos( ωt) } (9), V dc buf i -leel erter Buck type actie buffer Fig. 6. Buck type actie buffer circuit. C filter i V V dc d cos( ω t ) (), Vdc V _ ae respectiely. Note that the S3 and S4 are complementary to S and S, respectiely. When the boost ratio is larger than, an

5 ductance of the boost ductor the worst case is calculated by S [( V V ) d ( V ) d ] dc max, (), fswδi where Δi is the allowable current ripple and f sw is the switchg frequency of the FCC. The olume of the boost ductor is estimated by Area roduct of (8). The oltage of the flyg capacitor is gien by V i S S3 c -leel erter C filter i Δ V _ ae s( ωt) (), where, V ae_ is the aerage oltage and Δ is the oltage oscillation range of the flyg capacitor. Therefore, the capacitance of the flyg capacitor is calculated from (6). The conduction loss and the switchg loss caused by switchg deices are calculated by loss _ sw _ FCC loss _ cond _ FCC E dcd md T T i r on _ FCC ( eon eoff ) f sw T dt T i Sn dt (3), (4), respectiely, where r on_fcc is the on-resistance of switchg deices. The maximum oltage applied for each switch Sn is expressed by S S 4 Vdc (5), S S 3 (6), respectiely. Based on the designg flowchart of Fig. 5, the areto front of the FCC is obtaed.. BOOST CHOER DESGN Fig. 8 shows the circuit configuration of an oerall CSs which is consisted of a boost chopper, a buffer circuit, a grid terconnected erter and a ilter. The FCC comes the boost chopper and the buffer circuit. n order to compare between the olumes of the FCC and the conentional topology, the olume design of the boost chopper is necessary. The ductance of a boost ductor is determed by V V V dc cho (7), Δ i f sw Vdc where, Δi is the put current ripple, which is 3% of the rated put current this paper. The total loss of the switchg deices is expressed by loss _ chopper loss _ cond _ chopper (8), loss _ swi _ chopper where, the conduction loss loss_cond_chopper is calculated by loss _ cond _ chopper r on _ chopper Δi 3 (9), and loss_swi_chopper is the total switchg loss by Sp and Sn whose the switchg losses are obtaed by [ e ( i Δi ) e ( i Δi )] loss _ sw _ sp f swvdc on off (3), Edcd md [ e ( i Δ i ) e ( i Δi )] loss _ sw _ sn f swvdc on off (3), Edcd md respectiely. S4 Capacitor for power decouplg Fig. 7. Flyg capacitor conerter applied for the power decouplg. V Sp cho Sn Buffer circuit -leel erter C filter Boost chopper Fig. 8. Circuit configuration of an oerall CSs. V. EFFCENCY AND OWER DENSTY EVAUATON A. Comparison areto front of buffer circuit n the passie topology circuit, the electrolytic capacitor connected to the DC-lk is selected based on (). The allowable ripple current becomes 8.7 A on the assumption that K Hz. and K sw.4. Thus, the electrolytic capacitor, which has the allowable ripple current larger than 8.7 A, is selected. When the ratg oltage of the electrolytic capacitor is fixed, the olume of the electrolytic capacitor becomes smaller by connectg the capacitors with small allowable ripple i

6 current parallel []. n this paper, 8 electrolytic capacitors, which hae the allowable ripple current of A per one capacitor, are connected parallel with a ripple current marg of 5%. As a result, the total capacitance is 54 μf. Fig. 9 shows a relationship between the capacitance and the total olume when the ceramic capacitors are connected parallel. n the actie buffer, the ceramic capacitor is used as the buffer capacitor term of the high energy density. The DC bias characteristic, which is the decrease the capacitance of the ceramic capacitor by DC bias, has been considered Fig. 9. Comparg to the electrolytic capacitor, the ceramic capacitor has the higher ratio between the allowable ripple current and the capacitance. Therefore, when the requirement of the capacitance for the power decouplg is satisfied, the allowable ripple current is sufficient for the ceramic capacitor. Specifically, when the aerage oltage V ae and the oltage amplitude ΔV c are 6 V and 4 V respectiely, the capacitance is 79.6 μf. The olumes of capacitors of GRM series and KC series (Murata Manufacturg Co., td.) are.3 dm 3 and.44 dm 3 respectiely the total capacitance of 79.6 μf. Howeer, the required numbers of the ceramic capacitor are 36 and 344 respectiely, which are not realistic. On the other hand, when a ceramic capacitor of the EVS series (Murata Manufacturg Co., td.) is applied, the total olume and the required number are. dm 3 and μf. Therefore, the EVS series capacitor (Murata Manufacturg Co., td.) is used this paper. Table shows the selected components. Fig. shows the areto front of the power density ρ power and the efficiency η with the switchg frequency f sw as a ariable. The power density is calculated by (9) from the total olume of (). The efficiency η is proided by (). total ρ power buf Vol total Vol Vol Vol Vol Vol η Cbuf sw ( ) loss loss _ Cbuf loss _ Cf heatsk (3), (33), (34), where, Vol Cbuf and Vol sw are the olumes of the buffer capacitor and the package of the switchg deice. The power density reaches the maximum alue, when SiC-MOSFET is used the boost type actie buffer at 3 khz. Specifically, the maximum power density of 7. kw/dm 3 are achieed with the efficiency of 99.5%. On the other hand, the power density of 8.8 kw/dm 3 and the efficiency of 99.8% are achieed the passie topology. The power density of the passie topology is.4 times higher than the maximum power density of the actie buffer. B. Volume Comparison between Boost Type and Buck Type Actie Buffer Fig. shows the relationship between the rated power and the total olume of the boost and the buck type actie buffer. n Fig. 9. Relationship between capacitor olume and capacitance. Table. Selected components. Circuit assie buffer Boost type actie buffer Step down type actie buffer Boost chopper Flyg capacitor conerter art C SW SW SW SW Sp Sn S S S3 S4 c Markg Nippon Chemi-Con EKMZ45VSN8M3S Murata Manufacturg EVS39SG36MS9 SiC-MOSFET, SCH8KE Fuji Electric GBT, FGW3NHD Fuji Electric Si-MOSFET, FMH3N6S Murata Manufacturg EVS39SG36MS9 SCTAF SiC-MOSFET, SCTAF SiC-MOSFET, SCTAF SiC-MOSFET, SCTMUF Murata Manufacturg EVS39SG36MS9 Murata Manufacturg KC355WD7E5MH Maximum ration 45 V,. Arms 8 F 4 V 3 F V 4 A V 3 A 6 V( series connection) 3 A 4 V 3 F 65 V 9 A 65 V 9 A 65 V 9 A 4 V A 4 V 3 F 45 V F Fig., the frequency alue expresses the maximum power density pot each rated power. n the region of less than 3 kw, the olume of the buck type actie buffer is smaller than that of the boost type actie buffer, especially 4% smaller at kw. Fig. (a) shows the olume ratio of components at the maximum power density pot when the put power is kw. n the boost type actie buffer, the capacitance of the buffer capacitor can be reduced by higher capacitor oltage, howeer, the series connection numbers creases to satisfy the ratg oltage. As a result, the olume of the buffer capacitor is 67% of that of the buck type actie buffer. Fig. (b) shows the olume ratio of components at the maximum power density pot 6 kw. n the buck type actie buffer, the coolg system olume accounts for 64% of the total and it is 44% agast that of the boost type actie buffer. Because the buffer capacitor oltage is lower than DC-lk oltage, the high effectie current of the boost ductor leads to the large conduction loss. The creases of the heatsk olume

7 is more critical than that of the boost type actie buffer. Therefore, the region of more than 3 kw, the total olume of the buck type actie buffer is larger than that of the boost type actie buffer khz f sw creases. SiC-MOSFET 3 khz assie C. Comparison areto front of FCC Fig. 3(a) presents the operation waeforms which is operated by a -kw prototype of the FCC with the power decouplg control. Accordg to Fig. 3(a), the DC-lk oltage fluctuates at twice the grid frequency. On the other hand, from Fig. 3(b), a flyg capacitor oltage whose amplitude and aerage are V peak-peak and V respectiely, oscillates at twice the grid frequency. As a results, the DC-lk oltage becomes the constant. This experimental waeforms show that the sgle-phase power ripple can be compensated by the flyg capacitor. Fig. 4 shows the areto front of the FCC and the boost chopper with the buffer circuits. The switchg deices with a rated oltage of 65 V and 4 V are selected for the FCC Table and the deratg current which is 5 times of the rated put current is considered. The maximum oltages of the flyg capacitor are set to 34 V and 5 V for each switchg deice. Accordg to the Fig. 4, the power density approaches the maximum alue, when SiC-MOSFET with a rated oltage of 4 V is used the FCC at 5 khz. A maximum power density of 5.3 kw/dm 3 is achieed with efficiency of 98.9%. On the other hand, the power density of 4. kw/dm 3 and the efficiency of 98.8% are achiees the passie topology. Therefore, the maximum power density of the FCC is.3 times higher than the power density of the passie topology. D. Volume Comparison Fig. 5 shows the olume ratio of components at the maximum power density pot. The component olumes are normalized with the total olume of the passie topology as %. n the FCC with 4-V SiC-MOSFET, the olume of the flyg capacitor is reduced by 54.6% of that of the electrolytic capacitor. As a result, the oerall olume is 78.8% comparison with the one of the passie topology. When the flyg capacitor oltage is set to 5 V and the switchg deice with the rated oltage of 4 V is applied to the FCC, the flyg capacitor is twice the olume of the one with the rated oltage of 65 V. Howeer, the olumes of the boost ductor and the coolg system are reduced to 58.3% and 46.%, respectiely. As a result, the total olume of FCC with the switchg deices of the 4-V rated oltage is 57.5% of that of FCC with a rated oltage of 65 V. E. oss Comparison Fig. 6 shows the power loss ratio at the maximum power density pot. The loss caused by the boost ductor is ignored. The loss is normalized with the total loss of the passie topology. When the switchg deice with a rated oltage of 65 V is used for the FCC, the total power loss is %. On the other hand, the conduction loss of the switchg deices of 4-V rated oltage is reduced to 56.3% comparison with that of the 65-V rated oltage deice. As a result, the total power loss of the FCC usg the switchg deice with the Si-MOSFET khz 99 GBT 5 khz SiC-MOSFET khz 98.5 Boost type actie buffer Step down type actie buffer ower density [kw/dm 3 ] Fig.. areto front of the passie and the actie buffer circuits CS3 C/dm 3 (Natural coolg) Buck type actie buffer (solid le) khz Boost type actie buffer 5 khz (dashed le) 3 khz.3 4 khz 3 khz. 5 khz 35 khz 4 khz 35 khz. 4 khz 5 khz Rated power [kw] Fig.. Relationship between the rated power and the olume of the boost and buck type actie buffer at the maximum power density pots. Volume [dm 3 ] Rated power6kw (a) kw Switchg deice Heatsk buf Boost type actie buffer Buck type actie buffer (3 khz) ( khz) (b) 6 kw Fig.. Volume comparison of the actie buffer circuits.

8 rated oltage of 4 V is 89.5% compared to that of the conentional topology. V. CONCUSON This paper discussed a comparison of circuit topologies for an actie power decouplg of sgle-phase erter terms of efficiency and power density. n particular, the olume of capacitors is reduced by 54.6% a FCC with ceramic capacitors compared to bulky electrolytic capacitors. As a result, when a SiC-MOSFET of the 4-V rated oltage is applied for the FCC at 5 khz, the maximum power density is 5.3 kw/dm 3 which is.3 times higher than the power density of the electrolytic capacitor. Furthermore, the total power loss is reduced to 89.5% comparison with that of the conentional conerter. Therefore, the flyg capacitor conerter can achiee the highest power density and the highest efficiency the discussed topologies this paper. REFERENCES [] S. Q, Y. ei, C. Barth, W. iu, R. C. N. ilawa-odgurski : A High- Efficiency High Energy Density Buffer Architecture for ower ulsation Decouplg Grid-nterfaced Conerters, EEE ECCE 5, pp (5) [] Chia-Tse ee, Yen-Mg Chen, i-chung Chen, o-tai Cheng : Efficiency mproement of a DC/AC Conerter with the ower Decouplg Capability, EEE AEC, pp () [3] C. B. Barth,. Moon, Y. ei, S. Q, R. C. N. ilawa-odgurski: Experimental Ealuation of Capacitors for ower Bufferg Sgle- hase ower Conerters, ECCE 5, pp (5) [4] H. Hu, S. Harb, N. Kutkut,. Batarseh, Z. J. Shen : ower Decouplg Techniques for Micro-erters V Systems a Reiew, Energy Conersion Congress and Exposition, pp , pp. -6 () [5] Y. Xue,. Chang, S. B. Kjaer, Bau, J. Bordonau, T. Shimizu : Topologies of Sgle-phase nerters for Small Distributed ower Generators: An Oeriew, EEE Transactions on ower Electronics, Vol.9, No.5, pp (4) [6] Y. Kashihara, J. toh : arameter design of a Fie-eel nerter for V systems, CE - ECCE Asia, No. ThB3-, pp () [7] Wm. T. Mclyman : Transformer and ductor design handbook, Marcel Dekker nc., (4) [8] S. Fan, Y. Xue, K. Zhang : "A Noel Actie ower Decouplg Method for Sgle-hase hotooltaic or Energy Storage Applications", EEE ECCE, pp () [9] Uwe DROFENK, Gerold AMER and Johann W. KOAR : Theoretical Conerter ower Density imits for Forced Conection Coolg, roceedgs of the nternational CM Europe Conference, pp (5) [] T. Nakanishi and J. toh, Capacitor olume ealuation based on ripple current Modular Multileel Conerter, nternational Conference on ower Electronics, No. 9, pp. 85-8(5) [] H.Watanabe, K. Kusaka, K. Furukawa, J. toh: "DC to Sgle-phase AC Voltage Source nerter with ower Decouplg Circuit based on Flyg Capacitor Topologu for V System", AEC6, pp (6) nput current [A/di] nerter DC oltage [/di] Flyg capacitor oltage [V/di] Output current [A/di] ms/di 4 ms/di nput current [A/di] nerter DC oltage [/di] Flyg capacitor oltage [V/di] Output current [A/di] (a) with power decouplg (b) with power decouplg Fig. 3. Operation waeforms of the flyg capacitor conerter khz f sw creases. 5 khz (4V SiC-MOSFET) 3 khz Boost type khz Buck type khz khz (65V SiC-MOSFET) Flyg capacitor conerter 97.5 Chopper and actie buffer Chopper and electrolytic capacitor (passie topology) ower density [kw/dm 3 ] Fig. 4. areto front of the FCC and the boost chopper with the buffer circuits. Volume [%] oss [%] %74.5 W Fig. 5. Volume comparison the maximum power density pots Fig. 6. oss comparison the maximum power density pots.