DIGITAL TO ANALOG CONVERTERS

Transcription

1 C.Sauriol Rev. /8/ DAC Exercise Page II DIGITAL TO ANALOG CONVERTERS NO. Design a DAC that provides a 5,V t 5,V usg a DAC8: assume TTL puts. N. Design an amplifier/attenuator with digital ga control usg a DAC. The ga should range from to v/v. Use LF37 op amps and maximise the bandwidth. Also make the put resistance very large (R > MΩ). NO.3,, V V V C 3K K 7.5K 5 BIN IN PUT Ccom V LC Vc c V ee c om I DAC8 MS B I K K, K C V K V A) Determe the DC voltage range at the op amp put. B) Determe the maximum AC put amplitude that will either clip the put or clip the reference current, whichever comes first. Expla why reference current cannot go negative. C) Determe the mimum values of C and C if the frequency of V spans a range of 5 Hz to khz. Also determe an appropriate C com value and expla its function. D) Determe the AC ga of the circuit as a function of the bary put and plot the gabin characteristic showg all relevant values. E) If V =.V and BIN =,. what is V?

2 C.Sauriol Rev. /8/ DAC Exercise Page II No. PROGRAMMABLE DC POWER SUPPLY UNR EGU LATED INP UT VOLTAGE REGULATOR LM37 REGULATED OUTPUT V, V V, Ccom Io ut V LC Vcc Vee com DAC8,,5V V, 5 BIN INPUT Io ut NOTE: the,5v drop across the resistor is the ternal voltage reference of the LM37 regulator that appears across the regulator put p and the ustment p. The V at the DAC put should be a precision reference voltage. The mimum load current needed to garantee operation of the LM37 is specified as worst case. A) Design the circuit for,5v to 9,375V range B) Draw the tranfer characteristic showg all relevant parameters. No.5 PROGRAMMABLE DC POWER SUPPLY LM37 UNREGULATED I NP UT, 6 6 LM37 O/P L O A D I L 6 6 V V 75 pf VLC Vc c Ve e co m I DAC8 5 BINARY INPUT I

3 C.Sauriol Rev. /8/ DAC Exercise Page II3 No 5 A) Determe the put voltage range and the resolution of V o. B) Which resistor should we trim order to null the put when it should be zero? Expla. C) Modify the circuit order to obta a mimum O/P of V and a resolution of mv. D) Determe the maximum op amp O/P current. Modify the circuit to reduce this maximum current to 5 and still garantee a mimum load current of for the LM37. No.6 RESISTOR TOLERANCE TEST CIRCUIT,, V V Ccom 9K 9,K BIN# V io VLC V cc V ee com RE F RE F DAC8 5 BIN#3 CALIBRATION I I R U T V x or V RUT 5V P R E C IS IO N ERENCE V V 3 Vdd GND RE F DAC 3 BIN# UPPER LIMIT R F 6 O O V io V Y 5 V io3 K V LF3 V 5V K B o V 3 Vdd GND DAC 3 BIN# LOWER LIMIT R F 6 O O V io V Z 5 V io K V LF3 V K B RUT: resistor under test LF3 puts: V and 5V The above circuit is used for automated testg of resistors. BIN# selects the the 9.K resistor for the to K range and the 9K resistor for the to K range. BIN#3 is used to calibrate V of the DAC8 to exactly 9.V with RUT=K or K for the K or K ranges respectively usg a calibration RUT. The two LF3's form a wdow comparator used to pass or reject the resistor if tolerance is not met. 3

4 C.Sauriol Rev. /8/ DAC Exercise Page II A) Determe the typical calibration value of BIN#3. B) Assumg we are testg % resistors, determe the resistance versus BIN# and BIN# characteristics for the two ranges and label with all relevant parameters. What is the mimum resistance step that can be resolved each range? C) The LF3 have a maximum V io of ± mv at 5 o C and let us assume that the op amps have the same maximum V io. The cumulative error on the LF3 detection levels will be: V det = ±V io (comp)±v io (op amp)hysteresis What is V det maximum and what % error does it represent resistance wise? What is the mimum % tolerance test that can be achieved given the above answer? No.7 PROGRAMMABLE PW and SW FUNCTION GENERATOR A) Design the Schmitt trigger for ±7,5V trigger pots. B) Design the DAC circuits to provide a PW and SW range (square wave put) of µs to for BIN#x = to 55. C) If the LF37 have a mimum slew rate of 7 V/µs, is the o amp fast enough to handle the triangular wave put? NOTE: The logic controller switches BIN# and BIN# to proper values to obta the desired PW and SW at V o. I C should be zero when I C is activated and viceversa. D) Draw the PW and SW (versus BIN#x) characteristic showg relevant figures.

5 C.Sauriol Rev. /8/ DAC Exercise Page II5 No.8 PROGRAMMABLE TRACKING POWER SUPPLY LM37 UNREGULATED VE INPUT, LM37 VE O/P L O A D I L 6 6 VLC Vcc Vee com DAC8 V V B INA RY INPUT 5 75 pf Io u t Io u t VE O/P 75 UNREGULATED VE INP UT 75, LM337 L O A I L D A) Determe the two put voltage ranges and the resolution. B) Modify the circuit order to provide a range of V to 6,V at the ve put. C) How would modify the circuit order to reduce the current drawn from the op amps while matag the mimum load required for the LM37 and the LM337 regulators? 5

6 C.Sauriol Rev. /8/ DAC Exercise Page II6 SOLUTIONS No. V o = 5,V to 5,V V o 5,V V o ( 5,)= 55 V o V o = mv V o = 5,V to 5,8V mv crements. 5.V 5.8V Calculation of I : I o = I =, I =, 6

7 C.Sauriol Rev. /8/ DAC Exercise Page II7 No. k 38k V V Vdd 3 GND RF 6 pf Vo V LF 37 V DAC 3 O O LF37 BINARY INPUT The DAC provides a ga of to (95/96) and the first stage is a nonvertg amplifier with a ga of V/V. Therefore the overall ga is: V O = BIN V The put resistance of the DAC varies anywhere from K to K see data sheets. The put amplifier/buffer will prevent loadg of the signal source. The typical GBW of the LF37 is MHz, therefore the put amplifier has a BW = β v GBW =,9 MHz. Usg a pf compensation cap for the second LF37, the typical cutoff frequency is ab,5 MHz accordg to the DAC datasheets (see figure 3 of data sheets). Therefore the overall cutoff frequency or bandwidth will be ab,9 MHz. No.3 A) V OPA () = V to 39 mv for BIN = to 55 B) V SAT = ±V m for LF37 at R L = K, therefore I (AC) = V P /K =,6 P max for BIN = 55 and I (AC) =,6m *56/55 =,6 x which is impossible because I (DC) =,5, thefore I (AC) =,5 P max which corresponds to V =,5 P * K =5V P. C) In order to not attenuate signals at 5 Hz, let F LO = 5 Hz = (π*k*c ) = (π*k*c ), therefore C = 3,3 and C =,33. 6 db down db/dec *LOG(*BIN/56) 3,6 db down TYPICAL BANDWIDTH 5 Hz MHz MHz db/dec C com = pf is given datasheets for MHz BW of DAC8 if C com is creased, BW of DAC8 will decrease. LF37 has β V = because DAC8 put is a current put with high resistance, therefore BW = GBW of op amp. 7

8 C.Sauriol Rev. /8/ DAC Exercise Page II8 D) A V = BIN 8 A V = /56 A V = 7.8mV/V E) V =,65V No. V V K V VLC Vcc V ee com DAC8 5. V 75 pf Io ut Io ut A UNREG. I/P A V, ASSUM E K.. x 5. x LM m.5v 5. V 5V 6.35 MIN.5V I L L O A D O/P BIN INPUT = V 58 5.K.9 V A K V VLC Vcc V ee com V DAC pf 5V Io ut Io ut UNREG. I/P V.9 5 V, K.8. x 3.5 x LM mi n.5 v 5. 8.V 5V.3 MAX 9.375V L O A D I L O/P BIN IN PUT = 55 8

9 C.Sauriol Rev. /8/ DAC Exercise Page II9 No.5 A) V o = to,5v V o = 8,83 mv B) On your own! C) V o m = V V o max = V mv * 55 = 6,V V,5V,5V RE,5V I fix RF,5V I fix,5v V BIN = A I DAC,5V RE I fix V RF,85V,5V 6,V I DAC BIN =55,83 From the above circuit, we have I FIX R F =,5 I FIX R E, 5 = R F =, and,85v =,83m,5 R F =,83m R F,5 R F R E,85V = (,83m R F,5,) R F = 359,5 and R E = 5 359,5 = 698 R E R E 9

10 C.Sauriol Rev. /8/ DAC Exercise Page II UNREGULATED INP UT.5V LM37, ua LM37. x.9 m.5v 5. V 6.66 V to 6.V L O A D I L O/P V VLC Vc c Vee c om RE F DAC8 V 75 pf I to.8.5v to.85v 3.3 x to 5. x A 5 BINARY INPUT I D) Look at above circuit. No.6 A) B) TRANSFER CHARACTERISTIC V RUT = I BIN 3 56 R UT BIN 3 = V RUT 56 I R UT 9 56 BIN 3 = ( / 9,K) K = 9,66 BIN 3 = typical, same for all ranges. R = K/3688,7 =,7Ω R = K/3688,7 = 7,Ω K R FS,K,K RESISTANCE BIN# 3 X ,7 36 BIN I / P BIN#

11 C.Sauriol Rev. /8/ DAC Exercise Page II V RUT ± V io3 = V Y V RUT ± V io3 = K 5 K V 5 B 5K = V Y.5 or 5 96 V Y ( or.55mv) V.5 Y =.5( V RUT ± V io3 ).5( or.55mv ) V Y = BIN ± V oo.5 V RUT ± V io3 ( or.55mv) ( ) BIN =.5 V ± V ± V RUT io3 oo or. 55mV.5 ( to 9.V)± mv ± mv or.55mv BIN = ( to 9.59V) (5,5mV to,55mv) BIN = BIN =.3m,.5 ideal,,3 max ( ) ( ) to ( m, ideal, 369.6max) %error = R UT R UT %error = %error = R UT R UT = R UT,R FS R FS = (.3m or,3max) BIN (.3m or,3 max ) % m,.7% max = ( ).6% m,.7% max,r FS ( ) For lower resistor values the % error creases because the DC offsets are higher % wise relative to the lower voltages V RUT beg detected. To improve the accuracy one should use better op amps and better voltage comparators with lower DC offset voltages (V io <,5 mv) this would reduce the error on the detection level to : HYST/ =,55mV/ = ±.75mV or BIN =(±,75mV/V * = ±,5 = ±,5 R FS No.7 A) Schmitt trigger design: Use standard design procedure. I assumed V o =,5V and V o =,3V for the itial design steps. V o 7,5V 7,5V % RESISTORS,6K,K V LM39 V V K Vo V o,5v,3v 9,K PRECISION ERENCE V 8K, B) V o t = I C C I C = C V o t V = nf =,5 f or BIN = to 55 us

12 C.Sauriol Rev. /8/ DAC Exercise Page II,559 P R RB P3 V VLC PRECISION ERENCE pf V V V Vcc Vee com DAC8 5 BI N# I NPUT I I R3 TO,5 I c TO,5 I c I c nf C LF37 Vo,559 P R RB BI N# I NPUT 5 DAC8 VLC Vcc Vee com V V I I V,5 TO,5 pf RP =RP = V /.559 = 66Ω, use Ω pot set to Ω and 65Ω % resistor RP = V /.5 = 6667Ω, use Ω pot set to Ω and 6567Ω % resistor C) V o / t max = V/ µs = KV/s or, V/µs << SR = 3 V/µs typical for LF37 therefore the op amp is fast enough. D) V o t V o t SW = = I C C V o PW = I BIN C 56 PW = 56 C V o I 55 BIN = I C C V,5 I BIN o SW = 56 C 56 C V o I ( 55 BIN ) ( ) I I BIN 56 = C BIN PW or SW PW or SW (s) step size (s).39e.79e 3.95E7.9E E7 3.9E.3E7.99E.73E7 5 6.E E3.333E3 53.8E.667E3 5.56E.8E 55 SW = 56 C V o I ( 55 BIN ) PW = 56 C V o I ( 55 BIN ) From the circuit diagram we can develop the above two equations for SW and PW and plot them on a graph as shown below. Notice that the characteristic is not lear which means that the steps (not shown) will not be constant.

13 DAC Exercise PW or SW CHARACTERISTIC.E OUTPUT PW OR SW (S).E.E3.E BINARY INPUT No.8 A) V o = to ±,66V and V o = 59,66 mv B) and D) See no 5, same modifications. 3