Tackling the Little Box Challenge - New circuit architectures to achieve a 216 W/in 3 power density 2 kw inverter

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Basil Blankenship
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1 Tackling the Little Box Challenge - New circuit architectures to achieve a 6 W/in 3 power density kw inverter Robert Pilawa-Podgurski, Yutian Lei, Shibin Qin, Chris Barth, Wen-Chuen Liu, Andrew Stillwell, Intae Moon, Derek Chou, Thomas Foulkes, Zitao Liao, Zichao Ye Pilawa Research Group University of Illinois Urbana-Champaign IEEE PELS Webinar, May 5, 06

2 Outline Competition background Technical challenges Twice line frequency ripple compensation Conventional approaches Series-stacked buffer architecture Experimental measurements AC waveform generation Conventional approaches Flying-capacitor multi-level converter background Integrated switching cell development Experimental results Performance evaluation and comparison Lessons learned and future research directions

Current state-of-the-art: 95% efficiency, 400 in 3.

3 Google/IEEE Little Box Challenge kw, single-phase 40 V, 60 Hz AC Example usage: solar inverter, electric car charger, grid storage integration Current state-of-the-art: 95% efficiency, 400 in 3. Target goal: >95% efficiency, 0x smaller (40 in 3 ), must run for 00 hours $M prize to winning entry 3

4 To Participate or not Participate? Why not participate? We had no prior inverter experience Winning solution likely one that sacrifices reliability (e.g., 0 hour operation) Rules more suitable for industry -year timeline to develop inverter from scratch Rigorous testing protocol -> robustness required FCC Class B (including radiated!) Most people told us that Kolar s team at ETH will likely win anyway Why participate? Compete against the best teams in the world Students will learn valuable skills EMI, packaging, thermal, etc. A chance to compare our new research ideas against a common benchmark 4

5 Our Goal Develop a radically different solution make significant research contribution to the field of power electronics. May not win competition, but will have long-term impact 5

6 Original Team Chris Barth Integration Mechanical Thermal Capacitor evaluation Yutian Lei Inverter design Inverter control Shibin Qin Twice-linefrequency buffering System control $30k funding through Google Academic Grant 6

7 Key Technical Challenges E store = P dc πf line 7

8 Conventional Solution -Passive Filtering Capacitor as energy storage E store = P dc πf line = CV max CV min = C V max + V min V max V min nominal bus voltage bus voltage ripple 8

9 Active Filtering Ripple Port Converter π P ave Advantages Capacitor ripple decoupled from bus ripple Increased energy utilization of capacitor Smaller overall size Disadvantages High buffer converter power rating High voltage stress Low switching frequency, large inductor(s) Overall efficiency reduced: η buf = η dc-ac = 95% η total = 9.4% Krein et al., Minimum energy and capacitor requirement for single-phase inverters and rectifiers using a ripple port, IEEE TPELS, Nov, 0 Hu et al., A single-stage micro-inverter without using electrolytic capacitors, IEEE TPELS, June, 03 9

10 Stacked Switched-Capacitor Buffer Advantages No inductor Potentially higher efficiency (slow switching action) Reduced switch rating possible Disadvantages Large bus ripple Lower energy utilization of capacitors Increased circuit complexity Gate drivers, etc. Chen et al, "Stacked Switched Capacitor Energy Buffer Architecture," TPELS 03 0

11 Series-Stacked Buffer Architecture Series-Stacked Buffer

12 Series-Stacked Buffer Converter A series-connected buffer converter Reduced voltage stress (C blocks majority of voltage) Enable low voltage transistors - > Buffer converter size reduction Partial power processing (extreme efficiencies possible) Low power rating of buffer converter Size reduction Qin et al., A High-Efficiency High Energy Density Buffer Architecture for Power Pulsation Decoupling in Grid-Interfaced Converters, ECCE 05

$constant Buffer converter processes fraction (7% here) of overall power -> greatly improved efficiency$

13 Circuit Architecture - Overview i buf controlled to provide difference between i s and i inv v c + v ab constant Buffer converter processes fraction (7% here) of overall power -> greatly improved efficiency 3

14 Control Challenge: Voltage Balancing Buffer converter introduces loss C will slowly discharge, unless compensated Must provide additional charge to C Can recharge C through external means - undesirable 4

15 Control Challenge: Voltage Balancing Load step Enable compensation Buffer converter power =i buf v ab = i buf (v bus v C ) i buf pure AC, v C pure AC v bus DC + small AC (ripple) Qin et al., Architecture and control of an high energy density buffer for power pulsation decoupling in grid-interfaced applications, COMPEL 05 [Best paper award] 5

Capacitance reduced with applied voltage High energy density

16 Hardware Implementation Capacitor Choices Metal film Very low loss Constant capacitance Low energy density Ceramic Low loss Capacitance reduced with applied voltage High energy density Electrolytic High loss High constant capacitance RMS current limited Poor reliablity 6

17 Experimental Verification of Energy Storage Experimental test setup is configured to measure energy storage over wide voltage swing. Voltage swing and bias are independently adjustable. Capacitor test fixture 7

18 Experimental Results Experimental waveforms: Film capacitor with constant capacitance Ceramic capacitor with varying capacitance 8

19 Experimental Results Measured energy density for a range of capacitors and voltage ratings. RMS current limited C. Barth, I. Moon, Y. Lei, S. Qin and R.C.N. Pilawa-Podgurski Experimental Evaluation of Capacitors for Power Buffering in Single-Phase Power Converters, IEEE Energy Conversion Congress and Exposition, Montreal, Canada, 05 9

20 Experimental Results Quality factor normalizes energy stored by loss. 0

21 Experimental Results Film (PP), 300V, 60uF X7T, 450 V,. uf X6S, 450V,. uf C. Barth, I. Moon, Y. Lei, S. Qin and R.C.N. Pilawa-Podgurski Experimental Evaluation of Capacitors for Power Buffering in Single-Phase Power Converters, IEEE Energy Conversion Congress and Exposition, Montreal, Canada, 05

22 Hardware Prototypes TI LMG W/inch^3 ~80 W/inch^3

0mm auxiliary supply Way of measurement Volume Power density 58.

23 Hardware Prototype Energy Density Design requirement: - kva (PF = 0.7~) V ~ 450V bus voltage, - 0 A peak to peak current 98.0mm auxiliary supply Way of measurement Volume Power density 58.3mm sensing circuitry Rectangular box 4.88 inch^3 40 W/inch^3 4.0mm C microcontroller GaN full bridge passive component.0 inch^3 995 W/inch^3 C inductor 99% efficiency across load range C C 3 C bus auxiliary supply 3

24 Final Hardware Prototype Isolator ADuM50 Current sensing: LT999 Voltage sensing: LT990 EPC 06C / LMG V switch TDK X6S capacitors TI Delfino F8377D 4

25 Experiment - Steady State Operation 5

26 Experiment - Transient Operation 5% load to 50% load 00% load to 75% load 6

27 Experiment - Efficiency Digital power meter, integral function to ensure accuracy Same setup that was used to characterize capacitors Efficiency measurement excludes about 3 W control and gate driving power 7

28 Key Technical Challenges E store = P dc πf line 8

29 Inverter Conventional Topology Conventional Inverter H-bridge (likely dual interleaved) 650 V GaN transistors High switch stress High dv/dt Large inductor Localized hot spots 9

Multi-Level Flying-Capacitor Converter Inductor ripple frequency: f sw (N ) Reduced ripple voltage amplitude: V DC (N ) Reduced switch voltage stress: V

30 Multi-Level Flying-Capacitor Converter Inductor ripple frequency: f sw (N ) Reduced ripple voltage amplitude: V DC (N ) Reduced switch voltage stress: V DC (N ) Heat spreading Inductor reduced by (N ) T. Meynard and H. Foch, Multi-level conversion: high voltage choppers and voltage-source inverters, PESC 9 30

31 Multi-level Operation S 3a S a S a C C V sw V sw V in V in V in + V in V in

32 Multi-level Operation S 3a S a S a C C V sw V sw V in V in V in + V in V in

33 Multi-level Operation S 3a S a S a C C V sw V sw V in V in V in + V in V in

34 Multi-level Operation S 3a S a S a C C V sw V sw V in V in V in + V in V in

35 Multi-level Operation S 3a S a S a C C V sw V sw V in V in V in + V in V in

36 Multi-level Operation S 3a S a S a C C V sw V sw V in V in V in + V in V in

37 Multi-level Operation S 3a S a S a C C V sw V sw V in V in V in + V in V in

38 Multi-level Operation S 3a S a S a C C V sw V sw V in S 3a S a S a 3 V V in sw 0 0

39 Multi-level Operation S 3a S a S a C C V sw V sw V in S 3a S a S a 3 V V in sw 0 0 0

40 Multi-level Operation S 3a S a S a C C V sw V sw V in S 3a S a S a 3 V V in sw 0 0

41 Multi-level Operation S 3a S a S a C C V sw V sw V in S 3a S a S a 3 V V in sw 0 0 0

42 Multi-level Operation S 3a S a S a C C V sw V sw V in S 3a S a S a 3 V V in sw 0 0

43 Multi-level Operation S 3a S a S a C C V sw V sw V in S 3a S a S a 3 V V in sw 0 0 0

Multi-level Operation S 3a S a S a C C V sw V sw 0 0 0 0 0 0 0 + V in 0 0 + 0 0

44 Multi-level Operation S 3a S a S a C C V sw V sw V in S 3a S a pulse in each period S a 3 V V in sw 3 pulses in each switching period

Our Proposed DC-AC Conversion Stage Advantages Low

capacitor charging and discharging at switching

45 Our Proposed DC-AC Conversion Stage Advantages Low voltage switch: V DC /(N-), 450 V -> 75 V Alternates capacitor charging and discharging at switching frequency (compare to line frequency of MMC) Reduction in output filter size T. Meynard and H. Foch, Multi-level conversion: high voltage choppers and voltage-source inverters, PESC 9 45

46 Implementation Challenges Few experimentally demonstrated examples of > 5 level flying capacitor multi-level inverter, and none switching in the 00 s of khz at kw levels. Challenges Capacitor voltage balancing Approach: natural balancing with phase-shifted PWM Gate driving complexity Approach: Half-bridge gate drivers (LM53) and integrated isolated dcdc converter (ADUM50) Parasitic inductance Fast turn-on needed to reduce the V-I overlap loss during switching High dv/dt causes V ds ringing 46

47 Implementation Challenges 47

48 Parasitic Loop Inductance 48

49 Integrated Switching Cell 49

50 Digital Control Control objective: Generate correct amplitude Switch only minimum inductance loops Maintain capacitor voltage balance 50

51 Prototype # 80 W/in 3, 98% efficient 000+ total entries July 3, 05, 00+ submitted final report 8 finalists selected to October, 05 NREL testing 5

52 Growing the Team 5

53 Shrinking the Hardware 53

54 kw Hardware Prototype Y. Lei, C. Barth, S. Qin, W.-C. Liu, I. Moon, A. Stillwell, D. Chou, T. Foulkes, Z. Ye, Z. Liao and R.C.N. Pilawa-Podgurski A kw, Single-Phase, 7-Level, GaN Inverter with an Active Energy Buffer Achieving 6 W/in^3 Power Density and 97.6% Peak Efficiency, IEEE Applied Power Electronics Conference, Long Beach, CA, 06 54

55 Experimental Results 0.3% THD 55

56 Resulting Performance 97.6% efficiency 6 W/in^3 Commercial off-the-shelf components No electrolytic buffer capacitors All student-team $30k budget (not including night and weekend work!) Innovation in both inverter and buffer converter Our nd iteration Plenty of room for improvements EMI filtering inductors 56

NREL Testing October st, 05 @ NREL Finalist symposium 8 teams

Check all specifications Ripple, EMI, temperature, etc Load

57 NREL Testing October st, NREL Finalist symposium 8 teams invited (3 no-shows) Drop-off inverters for extensive testing Check all specifications Ripple, EMI, temperature, etc Load steps (extent unknown to teams) 00 hour continuous operation 57

58 Performance Comparison (Best Estimate) Excellent technical details/comparison by Prof. Johann Kolar at CIPS 06 Keynote: CIPS_6_Keynote_Presentation_FINAL_as_published_09036.pdf 58

59 Selected Teams (efficiencies at kw) 59

60 NREL Testing Details Difficult to exactly replicate testing scenarios 60

61 Research Impact Demonstrated the feasibility of multi-level flying capacitor power converters At kw-scale Using GaN technology With 70 khz effective switching frequency Achieved high efficiency and high power density through a new series-stacked active buffer Much work remains to be done for industry adoption Gate driver, isolated power supplies, level shifting Robustness, integration Approach likely to be relevant in applications where power density is a key requirement Laid the foundation for several promising future research areas 6

62 Lessons Learned Teams: Tempting to try to squeeze in too much innovation Timeline very challenging Great opportunity to learn from other teams Fantastic technical discussions Common bonding experience Reliability was overlooked by many teams Organizers: Difficult to set specs correctly the first time Many good teams left out from finalist selection Should consider allowing participants to test inverter at testing location IEEE: Significant value in having a common benchmark to compare approaches 6

63 Acknowledgments Google Texas Instruments NASA TDK Grainger CEME at UIUC 63

64 The Team Questions? 64

65 Backup Slides 65

66 Estimated Power Loss Breakdown 66

67 Full Specifications 67

THE power transfer capability is one of the most fundamental

THE power transfer capability is one of the most fundamental 4172 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 9, SEPTEMBER 2012 Letters Power Characterization of Isolated Bidirectional Dual-Active-Bridge DC DC Converter With Dual-Phase-Shift Control Biao