Regulated DC-DC Converter

Transcription

1 Regulated DC-DC Converter Zabir Ahmed Lecturer, BUET Jewel Mohajan Lecturer, BUET M A Awal Graduate Research Assistant NSF FREEDM Systems Center NC State University Former Lecturer, BUET 1

2 Problem Statement For a solar home system that has a nominal output voltage of 12V, you are to design an cell phone charging station that can directly charge through USB ports. Input Voltage Range 9V-14V Output Voltage 5.2V Output Voltage Ripple ±0.1V Maximum Load 2A, 10.4W 2

3 Steps For simplicity of design, the simplest non-isolated converter, i.e. BUCK topology is selected. The design procedure is discussed in detail. The power stage of the converter is simulated with ideal components. Closed-loop compensator/regulator is designed. Evaluation of compensator with non-ideal components and for varying input voltage range. 3

4 Power Stage Design Steps Passive components, i.e. L & C, selection Active and passive switch, i.e. MOSFET, diode selection Typically, steady state analysis is enough to determine the size of storage or filter elements and also the switch requirements. 4

5 Steady State Analysis Source: Erickson, Robert W and Dragan Maksimovic. Fundamentals Of Power Electronics. Norwell, Mass.: Kluwer Academic, Print. 5

6 Steady State Analysis 0 t DT s DT s t T s v L = V g v t i C = i L (t) v t /R v L = v t i C = i L (t) v t /R Source: Erickson, Robert W and Dragan Maksimovic. Fundamentals Of Power Electronics. Norwell, Mass.: Kluwer Academic, Print. 6

7 Steady State Analysis Small Ripple Approximation In a well-designed converter, the output voltage ripple is small. Hence, the waveforms can be easily determined by ignoring the ripple Figure: Output voltage of Buck converter Small Ripple Approximation: Though i L (t) and v t both has ripples, if the ripple is small, we assume that they can be approximated as constant quantities at a specific steady state operating condition. Let, i L (t) I, v t V. Source: Erickson, Robert W and Dragan Maksimovic. Fundamentals Of Power Electronics. Norwell, Mass.: Kluwer Academic, Print. 7

8 Steady State Analysis 0 t DT s DT s t T s v L = V g v t i C = i L (t) v t /R v L = v t i C = i L (t) v t /R Using small ripple approximation v L = V g V i C = I V/R v L = V i C = I V/R Source: Erickson, Robert W and Dragan Maksimovic. Fundamentals Of Power Electronics. Norwell, Mass.: Kluwer Academic, Print. 8

9 Inductor Current Ripple Calculation L 2 i L DT s = V g V L 2 i L (1 D)T s = V i L = V 1 D T s 2L Source: Erickson, Robert W and Dragan Maksimovic. Fundamentals Of Power Electronics. Norwell, Mass.: Kluwer Academic, Print. 9

10 Steady State Analysis Inductor Voltage Second Balance: Over a switching period, T s, the average voltage across the inductor is zero. Therefore, 1 T s [ V g V DT s + ( V)(1 D)T s ] = 0 Which gives, V = DV g Source: Erickson, Robert W and Dragan Maksimovic. Fundamentals Of Power Electronics. Norwell, Mass.: Kluwer Academic, Print. 10

11 Output Voltage Ripple Calculation DC portion of i L t flows to the load, i. e. I = V/R. The ac part or the ripple in i L t mostly flows through the capacitor, i. e. i L t = I + i C t. [Hint: superposition theorem] The positive portion of i C t charges the capacitor, i.e. causes the positive slope of the voltage across the capacitor. Capacitor Charge Balance: For the output voltage to be DC(very small ripple), over a switching period, T s, The average current through the capacitor must be zero, i.e. avg(i C ) = 0 Source: Erickson, Robert W and Dragan Maksimovic. Fundamentals Of Power Electronics. Norwell, Mass.: Kluwer Academic, Print. 11

12 Output Voltage Ripple Calculation If the total charge injected by the positive portion of i C (t) (shaded region) is denoted as q, q = i C (i C > 0)dt Inductor Voltage Second Since q = C 2 v, C 2 v = 1 2 T Balance is a prerequisite s 2 i for applying Capacitor L Charge Balance v = T s 8C i L Source: Erickson, Robert W and Dragan Maksimovic. Fundamentals Of Power Electronics. Norwell, Mass.: Kluwer Academic, Print. 12

13 Passive Component(L & C) Selection i L = V 1 D T s 2L v = T s 8C i L The problem statement restricts the maximum ripple voltage across the output capacitor. Output voltage ripple depends on the switching frequency, f s (= 1 T s ), capacitor value, C, and the ripple current i L. The designer has two degree of freedom while choosing the capacitor value. The same ripple magnitude can be achieved with various different combination of i L and T s. However, i L is itself a function of switching frequency f s (= 1 T s ). Choice of f s, and maximum allowable inductor ripple current, i L, which in turn determines the inductor value, is subject to a system level optimization that depends on optimization goal, e.g. efficiency, power density, cost etc. The optimization is done by considering the inductor core material(loss and dc bias characteristics), switch losses etc. This sort of optimization is an active research topic till date. For simplicity, we start with a typical value of i L =10% of I max and we also choose f s = 150KHz. 13

14 Passive Component(L & C) Selection i L = V 1 D T s 2L v = T s 8C i L Note that i L changes with D which is a function of input and output voltage. With fixed output voltage, for varying input voltage level the duty ratio D varies. Now, max( i L )=10% of I max or, V 1 D min T s 2L min = 10% of I max ; where, D min = V V g,max = or, L min = 54.48µH The voltage ripple equation with maximum ripple of 0.1V gives, C min = 1.67µF. 14

15 Voltage Stress on Switches MOSFET ON MOSFET OFF V D = V g V MOSFET = V g Both the diode and the MOSFET has to block a maximum of V g when they are OFF. 15

16 Switch Current MOSFET ON MOSFET OFF i MOSFET,max = i L,max = I max + i L i D,max = i L,max = I max + i L Both the diode and the MOSFET has to carry a maximum of I max + i L. Now, I max = V R min and R min = V2 P max. 16

17 Switch Selection Maximum blocking voltage is V g,max P max V Maximum switch current + i L Note, V g,max = 14V, P max = 10.4W, V = 5.2V i L depends on designer s choice of switching frequency and inductor value. Once blocking voltage and peak current is determined, a safety margin is preferred. For conservative design, you may have a safety margin of 50%, e.g. for required maximum blocking voltage of 14V, you would choose a switch with blocking capacity of at least % = 21V. Conduction and switching loss calculation is required to determine the required heat dissipation capacity of the switches as well as appropriate cooling arrangement(heat sink, liquid or forced air cooling etc.). 17

18 Pulse Width Modulation Sawtooth carrier PWM is the most intuitive among various PWM techniques. Sawtooth Carrier D Gate Pulse 18

19 Simulation of Unregulated Converter All components are ideal 19

20 Simulation of Unregulated Converter Inductor Current Output Voltage Can you think of any wrong assumption that we made while calculating the ripple magnitudes which would explain the slight deviation of the output voltage from our intended range 5.1V to 5.3V? 20

21 Why Regulator? Fixed output voltage for varying input voltage. In reality, all components have non-idealities, e.g. MOSFET ON resistance, diode forward drop, inductor winding resistance, capacitor series resistance and inductance etc. Most non-idealities vary as a function of the operating condition. Duty ratio, D, has to be adjusted on runtime to compensate for all above mentioned variations 21

22 What Happens When Duty Ratio is Varied Infinitesimally? For f s = 150KHz, T s = 6.67µs. Assume that the infinitesimal variation in duty ratio(in fig. shown in red) is introduced at a much slower rate compared to the switching carrier (blue). Effectively the duty ratio, d t, can be considered to be constant over each duty cycle, however the variation is happening at a mush slower rate. If the variation is slow enough, the system dynamics can be studied with all quantities, e.g. i L t, v t, i C t averaged over each duty cycle, T s. 22

23 What Happens When Duty Ratio is Varied Infinitesimally? 0 t DT s DT s t T s v L = V g v t i C = i L (t) v t /R v L = v t i C = i L (t) v t /R Let the average quantities be < i L t > Ts, < v L t > Ts etc. The average quantities are calculated as, < v L t > Ts = 1 T s [d t T s {< V g v t > Ts } + {1 d t }T s {< v t > Ts }] For convenience, from here onwards, all quantities, e.g. i L, v etc. will denote time varying quantities averaged over a switching period, T s. 23

24 Transfer Function Analysis + v x - v x = 1 T s dt s V g + 1 d T s 0 = dv g Applying KVL, v x = L di L dt + v or, dv g = L di L dt + v Combining two equations, dv g = L d dt or, dv g = LC d2 v dv C + v dt R Applying KCL, i L = C dv dt + v R + L dv + v dt 2 R dt Now, around an operating point for small variation in d, we can take Laplace + v transform of the equation, d(s)v g = LCs 2 + L s + 1 v(s) R 24

25 Transfer Function Analysis d(s)v g = LCs 2 + L R s + 1 v(s), or v(s) d(s) = V g LCs 2 + L R s+1 =G vd(s) d V g LCs 2 + L R s + 1 v 25

26 Regulator/Compensator Design From the system dynamic model/transfer function, a closed-loop controller has to be designed. To make sure that the compensator dynamics is slow enough compared to the switching operation (variation in d is slower compared to T s ), a cross over frequency lower than f s /10 is a conservative design and recommended for new designers. It can be shown that for a second order system, a phase margin of around 52 o gives a critically damped response. A gain margin of at least 6dB is recommended. f c f s 10, ϕ m 52 o, G m 6dB 26

27 Simple PI Compensator Uncompensated loop gain, G vd s = v(s) d(s) = V g LCs 2 + L R s+1 27

28 Simple PI Compensator Compensated loop gain, G vd s H s ; where, H s = K p + K i s K p = 0.1, K i =

29 Simple PI Compensator Compensated loop gain, G vd s H s ; Here, ϕ m = 60.1 o, f c = 14.5KHz Here, the high frequency asymptote of the phase response plot is at 180 o. In reality, controller delay(due to time required for A\D conversion and calculation in microcontroller/dsp) will cause the phase response reach beyond 180 o. However, the gain margin is more than enough for stable operation. 29

30 PI Compensator Implementation Compensator Plant The limiter block after the compensator is used to make sure that the control input, d, does not go beyond the carrier range(0v-1v). This is particularly important if using an anti-windup arrangement for the integrator. 30

31 PI Compensator Response Input Voltage Output Voltage At t=0.1s, the input voltage jumps from 9V to 14V The compensated system exhibits a damped response 31