ORGANIC THIN-FILM transistors (OTFTs) have attracted

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1 3382 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 12, DECEMBER 2012 Structure-Dependent Contact Barrier Effects in Bottom-Contact Organic Thin-Film Transistors Linrun Feng, Xiaoli Xu, and Xiaojun Guo, Member, IEEE Abstract This paper investigates and compares the structure-dependent contact barrier effects on the electrical performance of two bottom-contact (BC) structure (staggered and inverted coplanar) organic thin-film transistors (OTFTs) by numerical simulations. The drain saturation current (I dsat ) of the staggered device is found to be more sensitive to the variation of the source/drain (S/D) electrode thickness than that of the inverted coplanar one. The inverted coplanar device shows stronger dependence of I dsat on the contact barrier than the staggered device, and the dependence is also much more affected by the step coverage profile of the semiconductor layer on top of the S/D electrodes. For the inverted coplanar structure OTFTs, a steeper step coverage profile and a lower contact barrier can help to achieve better tolerance of I dsat to the variations of the contact barrier and step profile, respectively. The gate structure (self-aligned or fully covered) does not show any influence. The study forms a clear understanding of the device-structure-dependent carrier transport mechanisms in BC OTFTs and could also provide important guidelines for optimal device structure design and related process development for BC OTFTs. Index Terms Contact barrier, inverted coplanar, organic thinfilm transistor (OTFT), Schottky contact, staggered. I. INTRODUCTION ORGANIC THIN-FILM transistors (OTFTs) have attracted considerable attention owing to their potential applications in low-cost and flexible large-area electronics, such as radio-frequency identification tags [1], sensors [2], and backplanes for electrophoretic and organic light-emitting diode displays [3], [4]. In the last decade, great efforts have been paid to develop high-carrier-mobility chemically and physically stable organic semiconductor materials. In the mean time, it has also been well proved that the device structure can significantly affect the OTFT s electrical performance [5], [6]. Generally, the top-contact (TC) structure OTFTs can form better contacts between the metal electrode and the semiconductor layer than the bottom-contact (BC) ones to provide more efficient charge injection [7]. However, BC structures are still preferred for Manuscript received June 4, 2012; accepted September 11, Date of publication October 2, 2012; date of current version November 16, This work was supported in part by the Program for Professor of Special Appointment (Eastern Scholar) at Shanghai Institutions of Higher Learning, by the Program for New Century Excellent Talents in University, and by the NSFC under Grants and The review of this paper was arranged by Editor A. C. Arias. The authors are with the Department of Electronic Engineering, Shanghai Jiao Tong University, Shanghai , China ( lr.feng@sjtu.edu.cn; xuxiaoliyou@sjtu.edu.cn; x.guo@sjtu.edu.cn). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TED circuit integration of OTFTs because of the process difficulty of making source/drain (S/D) metal electrodes on top of the organic semiconductor layer with precise patterning [8], [9]. With respect to the relative locations of the gate electrode and the S/D electrodes, BC OTFTs can be realized in two configurations: the staggered configuration (top gate) in which the S/D and gate electrodes are formed on opposite sides of the semiconducting layer and the inverted coplanar configuration (bottom gate) in which the S/D and gate electrodes are formed on the same side of the semiconducting layer. Both staggered and inverted coplanar BC OTFTs have been widely employed in applications of display backplanes and integrated circuits depending on process integration preferences [10], [11]. Based on the BC structures, surface modifications of metal contacts with thiol self-assembled monolayers can be used for obtaining lowresistive and preferably ohmic metal/semiconductor contacts as well as good-quality semiconductor films on top of the S/D electrodes for higher driving current and better uniformity of electrical characteristics [12]. Considering the importance of device geometry design affecting the electrical performance of OTFTs, there have been extensive investigations on the structure-dependent parasitic contact effects in inverted staggered (bottom-gate TC) and inverted coplanar (bottom-gate BC) structure OTFTs by using numerical device simulations to exclude the process-induced influence [13]. It was concluded that the inverted staggered structure has a lower contact resistance than the inverted coplanar structure for a larger effective area for carriers injection at the source electrode. The contact resistance in the inverted staggered structure OTFT was also found to be less dependent on the contact barrier than that in the inverted coplanar one, which is consistent with the experimental work by Gundlach et al. [14]. However, there is still a lack of clear understanding of contact barrier effects in the staggered OTFT compared to the inverted coplanar one, although these two BC structures are more widely used for complicated circuit integration in practical applications. This paper will focus on the investigations and comparisons of the structure-dependent contact barrier effects in the BC OTFT structures, considering the difference between the staggered and inverted coplanar structures, the influence of the gate structures (self-aligned and fully covered), and the effects of the step coverage profile of the organic semiconductor film on top of the S/D electrodes. Two-dimensional numerical simulations will be used in the study to exclude the influence of processinduced semiconductor dielectric interface difference between the two BC structures and thus make a distinction between the effects of the process and the structure /$ IEEE

2 FENG et al.: STRUCTURE-DEPENDENT CONTACT BARRIER EFFECTS IN BC OTFTs 3383 Fig. 1. OTFT device structures used in the study. (a) Self-aligned-gate inverted coplanar structure. (b) Self-aligned-gate staggered structure. (c) Fully covered gate inverted coplanar structure. (d) Fully covered gate staggered structure. For all structures, the gate insulator layer is of 300-nm effective silicon oxide thickness (t ox), and a dielectric layer (thickness of 1 μm and relative dielectric constant of 3.9) on top is defined in the simulations to match the real condition where the devices are integrated in circuit applications. II. SIMULATION SETUP To investigate the structure-dependent contact barrier effects in the BC OTFTs, 2-D numerical simulations were performed using the commercial software Atlas vended by Silvaco [15]. Although originally developed for silicon and inorganic devices, Atlas allows user-defined semiconductor materials and has been proved to be a useful tool for studying the device physics of OTFTs [16] [18]. The simulated device geometries for both staggered and inverted coplanar BC OTFTs are shown in Fig. 1, with a channel length (L ch ) of 30 μm, an S/D electrode length (L sd ) of 30 μm, an S/D electrode thickness (t sd ) of 100 nm, a channel thickness (t ch ) of 50 nm, a gate insulator effective silicon oxide thickness (t ox ) of 300 nm, and a gate insulator dielectric constant of 3.9. The channel width is 1 μm. The fully covered gate structure is commonly used in OTFTs for process convenience. However, the self-aligned-gate structure is demanded in practical circuit applications to reduce the parasitic capacitance. In this paper, both structures will be studied and compared, as shown in Fig. 1. For the self-aligned-gate device structure, the gate length (L g ) is set to be 30 μm with no overlap to the S/D electrodes, while for the fully covered gate structure, L g is set to be 90 μm with a 30-μm overlap to both the source and drain electrodes. The thickness of the gate electrode (t g ) is 100 nm. This work modeled the step coverage profile by defining a certain thickness (d l ) of the lateral semiconductor region at the edge of the electrodes, as indicated in Fig. 1. Unless specified, the value of d l was set to be 500 nm. Although this model cannot completely replicate the actual case of the step coverage caused by different processes (spin coating, evaporation, spraying, and others), this approximation is enough for the qualitative study in the work. The usual values of pentacene (energy gap of 2.5 ev, ionization potential of 5 ev, and dielectric constant of 4.0) have been used for the organic semiconductors [19]. The field-dependent hole mobility is described by the Poole Frenkel model, which can be expressed as μ = μ 0 e E/E0 (1) Fig. 2. Simulated output characteristics (I ds V ds )oftheotfts(schottky barrier heights (Φ b ) of 0 and 0.3 ev) with V gs = 4, 6, and 8 V. (a) Inverted coplanar structure. (b) Staggered structure. The S/D electrode thickness is 100 nm. where μ 0, the low-field mobility, is set to be cm 2 /V s, E is the electrical field, and E 0 is a characteristic parameter equal to V/cm. The effective density of states (N V ) is set to be cm 3. Simulations based on these models and parameters have been proved to be able to get the results well fitting with the experimental data [19]. Neither bulk semiconductor trap states nor interfacial trap states have been included in the simulations, since the intention of this study is to compare the simulated ON-state driving current results of two BC OTFTs, which are not affected by the trap states. In the simulations, the formed Schottky barrier Φ b at the metal/semiconductor interface for hole injection is modified by changing the metal workfunction based on the following equation: Φ b = χ + E g q Φ m (2) where χ is the electron affinity of the semiconductor material, E g is the bandgap, q is the unit quantity of electricity, and Φ m is the workfunction of the metal electrode [15]. The barrier height of the metal/semiconductor interface is changed between 0 and 0.4 ev in order to account for different injection situations [20]. III. RESULTS AND DISCUSSIONS A. Staggered Versus Inverted Coplanar Fig. 2 shows the simulated I ds V ds characteristics of the staggered and inverted coplanar BC OTFTs of a self-alignedgate structure. The S/D contact barrier height Φ b varies as 0 and 0.3 ev. It is clearly seen that the drain saturation current (I dsat ) in the inverted coplanar OTFTs is more sensitive to the change of the barrier height from 0 to 0.3 ev. To further investigate the contact barrier effects, the extracted I dsat from the simulated I ds V ds characteristics at bias voltages of V gs = 8 V and V ds = 25 V is plotted in Fig. 3(a) as a function of the barrier height for both staggered and inverted coplanar self-alignedgate BC OTFTs of different S/D electrode thicknesses (0 and 100 nm). The results for the S/D electrodes of zero thickness

3 3384 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 12, DECEMBER 2012 Fig. 3. Simulated drain saturation current (I dsat ) of the self-aligned-gate structure OTFTs at bias voltages of V gs = 8 VandV ds = 25 V (d l = 500 nm). (a)i dsat as a function of the contact barrier height (Φ b ) for the staggered and inverted coplanar structure devices of 0- and 100-nm electrode thicknesses. (b) I dsat as a function of the S/D electrode thickness for the inverted coplanar structure devices with and without the capped dielectric layer on top of the channel (Φ b = 0.3 ev). Fig. 5. Simulated electric field distribution (at bias voltages of V gs = 8 V and V ds = 25 V) across the source contact region near the top surface of the source electrode for the two structure OTFTs. In the work, all the extracted electric field values are the vector sum of both vertical and horizontal components. Fig. 4. Illustration of current conduction procedures through OTFT devices [(1) charge injection through the source contact metal/semiconductor interface, (2) charge transport from the interface into the channel region, (3) charge transport in the channel, and (4) charge collection at the drain electrode]. (a) Inverted coplanar structure. (b) Staggered structure. (commonly adopted in previously reported simulation works [13]) are given in the same plot for comparisons. The extracted I dsat as a function of the S/D electrode thickness for both structure devices with Φ b = 0.3 ev is also shown in Fig. 3(b) to clearly compare the dependences of I dsat on the electrode thickness variations for different device structures. As shown in Fig. 3(a), as the contact barrier height increases, the I dsat s of both staggered and inverted coplanar structures decrease slowly at first, and after the contact barrier height reaches a characteristic value (about 0.15 ev in this case), the I dsat s of the inverted coplanar OTFTs start to drop rapidly while the I dsat s of the staggered structure devices still decrease slowly with the increase of the contact barrier height. The characteristic value of the barrier height (0.15 ev) is lower than 0.3 ev in [13], mainly because the transport of carriers becomes more contact barrier limited without considering traps in this semiconductor layer, and thus, I dsat is more sensitive to the increase of Φ b. To explain the observed phenomena, a detailed analysis of the different barrier effects in staggered and inverted coplanar OTFTs is given as follows. As illustrated in Fig. 4, the current conduction through an OTFT is composed of four procedures: 1) charge injection via the source contact metal/semiconductor interface; 2) charge transport from the interface into the channel region; 3) charge transport in the channel; and 4) charge collection at the drain electrode. In the saturation regime with a high drain bias, the effect of 4) can be neglected. Therefore, considering that the same gate dielectric layer and semiconductor/dielectric interface are assumed in the simulations to exclude the process influence, the differences between the staggered and inverted coplanar structures are procedures 1) and 2). Fig. 5 shows a comparison of the extracted electric field distributions across the source contact region near the top surface of the source electrode for both staggered and inverted coplanar structures with Φ b of 0 and 0.3 ev (at bias voltages of V gs = 8 V and V ds = 25 V). In the work, all the extracted electric field values are the vector sum of both vertical and horizontal components. The inverted coplanar device owns much higher electric field near the source end region than the staggered one, and the carriers can thus be swept more quickly from the metal/semiconductor interface to the channel region, since the carrier velocity v is a function of the local electrical field defined by v = E μ(e) (3) where E is the local electric field and μ(e) is the electricalfield-dependent mobility and can generally be described by the Poole Frenkel mobility model as stated in Section II. Therefore, for the inverted coplanar structure devices, as Φ b increases, the current conduction in the device becomes more and more limited by the contact barrier due to the high local electrical field. This can explain the results in Fig. 3(a), where, when Φ b is larger than 0.15 ev, the operation of the inverted coplanar structure enters into the contact-barrier-limited regime, so I dsat drops rapidly with further increase of Φ b.in the staggered structure, the current conduction is more limited by the slow charge transport in the low-electric-field region at the source end and thus shows much less dependence on the variations of Φ b, as shown in Fig. 3(a). From Fig. 3(a), it can also be seen that the staggered structure OTFTs with S/D electrodes of zero thickness, which are physically the same to the inverted staggered one, show higher saturation current than the inverted coplanar ones, and the saturation current of the staggered structure devices is less sensitive to the change of Φ b. However, with S/D electrodes of nonzero thickness, the staggered devices own lower I dsat than the inverted coplanar devices at relatively lower contact barrier,

4 FENG et al.: STRUCTURE-DEPENDENT CONTACT BARRIER EFFECTS IN BC OTFTs 3385 Fig. 6. (a) Simulated electric field distribution across the region near the metal/semiconductor interface at the source end of the staggered structure OTFTs with different source electrode thicknesses (100 and 0 nm). (b) Simulated contours of the hole current density in the source contact region for the staggered structure OTFTs with different source electrode thicknesses of (I) 100 and (II) 0 nm. (V gs = 8 V,V ds = 25 V, and the source contact barrier height Φ b = 0.3 ev.) which is contrary to the results for the zero-s/d-electrodethickness devices. As more clearly shown in Fig. 3(b), this is because the I dsat of the staggered structure decreases with the increase of the S/D electrode thickness, while the I dsat of the inverted coplanar structure with the capped dielectric layer does not present any obvious changes. Interestingly, for the inverted coplanar structure without the capped dielectric layer, an obvious increase of I dsat is obtained with thinner S/D electrodes. To explain the reduction of I dsat with the increase of the S/D electrode thickness for the staggered structure, the electric field strength at the top electrode surface across the contact region and the contours of the hole current density in this region with S/D electrodes of 0- and 100-nm thicknesses are extracted, as shown in Fig. 6. It is obviously observed in Fig. 6(a) that the increase of the S/D electrode thickness reduces the local electrical field strength around the source end region, which, in turn, deteriorates the charge injection and transport efficiency in this region. As shown in Fig. 6(b), for the staggered structure devices with thick S/D electrodes, certain injected charges are accumulated at the top right corner of the contact region with the effect of the gate-induced vertical electrical field, which are difficult to transport to the channel region due to the slow diffusion process, while for the devices with zerothickness electrodes, the injected charges can be efficiently Fig. 7. (a) Simulated contours of the hole current density in the source contact region for the inverted coplanar structure OTFTs of different configurations: 100-nm-thick S/D electrodes (I) with and (II) without the capped dielectric layer and 0-nm-thick S/D electrodes (III) with and (IV) without the capped dielectric layer (V gs = 8 VandV ds = 25 V). (b) Simulated I ds V ds characteristics for the inverted coplanar structure OTFTs with and without the capped dielectric layer on top of the channel. (The source contact barrier height Φ b = 0.3 ev.) swept to the channel region with the gate- and drain-induced electrical fields. The combination of the aforementioned two effects causes the reduction of I dsat in the staggered structure devices with thicker S/D electrodes. For the inverted coplanar structure devices, the presence of a dielectric layer on top of the channel was found to affect the dependence of I dsat on the electrode thickness variations. In Fig. 3(b), the simulated I dsat values as a function of the S/D electrode thickness for both structures with and without the capped dielectric layer are compared, clearly showing that, without the capped dielectric layer on top of the channel, I dsat becomes much more sensitive to the electrode thickness variations, which is consistent with the results in [13]. As discussed in [21], for the inverted coplanar structure devices operated in the saturation regime, a fringing capacitance could be formed between the drain electrode and the back of the channel for an additional part of the current. In this work, the presence of the dielectric layer on top of the channel will increase the fringing capacitance between the drain electrode and the source contact region of the channel, and the draininduced additional fringing electrical field will enhance the charge injection into and through the contact region. Fig. 7(a) shows a comparison of the extracted hole current densities in the contact region for the devices with and without the capped dielectric layer. For the devices without the capped dielectric layer, since the charge injection is mainly through the

5 3386 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 12, DECEMBER 2012 edge of the electrode, the decrease of the electrode thickness will reduce the effective charge injection area and thus cause a current reduction. With the capped dielectric layer, when the source electrode becomes thinner, the drain-fringing-fieldinduced additional injected charges will be easier to be swept to the channel region by the gate-induced vertical electrical field, which can somehow counteract the influence of reducing the electrode thickness. This can explain why the apparent drain saturation current of the devices with the capped dielectric layer is much less dependent on the variations of the electrode thickness, as shown in Fig. 3(b), and also presents higher values, as shown in Fig. 7(b). The slightly less saturated I ds V ds curves in the saturation regime of the devices with the capped dielectric layer compared to those without the capped dielectric layer can also be attributed to the enhanced influence of the drain bias on the charge injection and transport. In summary for this part, the inverted coplanar devices own a higher electrical field for more efficient charge transport at the source end region compared to that of the staggered device, which makes the current conduction in the inverted coplanar structure devices be more contact barrier limited, particularly when the contact barrier is relatively high. Therefore, the simulated I dsat s of the inverted coplanar structure devices present to be more contact barrier dependent than those of the staggered structure devices in the range of relatively high contact barriers. On the other hand, the reduction of the I dsat of the staggered structure device with the increase of the S/D electrode thickness can be attributed to two reasons: 1) The local electrical field strength around the source end region is reduced, which, in turn, deteriorates the charge injection and transport efficiency, and 2) part of the injected charges accumulated at the top right corner of the contact region with the effect of the gate-induced vertical electrical field become more difficult to transport to the channel region for the slow diffusion process. For the inverted coplanar structure devices, the capped dielectric layer on top of the channel is found to be able to affect the device performance by enhancing the effects of the fringing electric field from the drain electrode on the source contact region. With the capped dielectric layer, the extracted I dsat increases and becomes much less dependent on the variations of the S/D electrode thickness. B. Self-Aligned Gate Versus Fully Covered Gate For circuit integration, the self-aligned-gate structure is preferred for lower parasitic capacitances to achieve high speed and low dynamic power consumption. However, fully covered gate OTFT structures are popularly used in low-performance applications, attributed to simpler processes and better tolerance to misalignment. Therefore, after taking the self-alignedgate structure in the aforementioned analysis, this part will look into the effects of the gate structures on the contact barrier effects. For the inverted coplanar structure, there is no physical difference of the dc electrical properties between the selfaligned-gate and fully covered gate structures. The following will mainly discuss the case for the staggered structure. Fig. 8(a) shows a comparison of the contact-barrierdependent I dsat s between the self-aligned-gate and fully cov- Fig. 8. (a) Comparison of the contact-barrier-dependent drain saturation currents (at bias voltages of V gs = 8 VandV ds = 25 V) between the self-aligned-gate and fully covered gate OTFTs (staggered structure) with S/D electrodes of 0- and 100-nm thicknesses. (b) Hole current density distribution (V gs = 8 V,V ds = 25 V, and Φ b = 0 ev) in the staggered OTFTs of (I) the self-aligned-gate structure with 100-nm electrode thickness, (II) the fully covered gate structure with 100-nm electrode thickness, (III) the self-alignedgate structure with zero electrode thickness, and (IV) the fully covered gate structure with zero electrode thickness. ered gate OTFTs with 0- and 100-nm-thick S/D electrodes, which shows no difference between the two different gate structures. For the fully covered gate structure, even if the effective carrier injection area could be increased by the gate-induced vertical electrical field, the transport of the injected carriers would be limited by the low-local-electrical-field region at the source end. Therefore, as shown in Fig. 8(b), there is almost no difference in the hole current density distribution in the channel, and as a result, the I dsat s and the contact barrier effects on I dsat between the self-aligned-gate and fully covered gate structures are nearly the same. C. Effects of the Step Coverage Profile In actual devices, the S/D electrodes are usually of a thickness ranging from tens to hundreds of nanometers, which results in a certain step coverage profile when the semiconductor film is deposited on top of the electrodes. The profile depends on the material s physical properties, the surface states, and the deposition processes (evaporation, spin casting, spraying, etc.). In this work, the step coverage profile is modeled by defining a lateral thickness value d l as indicated in Fig. 1. The simulated

6 FENG et al.: STRUCTURE-DEPENDENT CONTACT BARRIER EFFECTS IN BC OTFTs 3387 Fig. 9. Drain saturation current (at bias voltages of V gs = 8 V and V ds = 25 V) as a function of Φ b at different d l s (50, 150, and 500 nm) with 100-nm-thick S/D electrodes. I dsat as a function of Φ b at different d l s for both staggered and inverted coplanar structure devices with 100-nm-thick S/D electrodes is shown in Fig. 9. The lateral thickness of the step coverage varies as 50, 150, and 500 nm. It can be seen that, for staggered OTFTs, as d l increases, I dsat decreases, but the rate of the current reduction with the increase of the contact barrier is not much affected. That means that the carrier transport in the staggered structure OTFT is still dominated by the lowelectrical-field source end region with different d l s. For inverted coplanar structure OTFTs, in a low-φ b regime ( ev), I dsat is little sensitive to the variations of both the step coverage profile and the contact barrier height. As Φ b keeps increasing, I dsat becomes more and more sensitive to the variations of the step coverage profile. On the other hand, the results in Fig. 9 also indicate that the decrease of d l can induce much less sensitivity of I dsat to the change of Φ b. The difference in apparent I dsat is determined by the following procedures: 1) charge injection via the source contact metal/semiconductor interface and 2) charge transport from the interface into the channel region. To explain the mentioned phenomena, the simulated current density contours at the source contact region of the channel for the inverted coplanar structure OTFTs of different Φ b s (0 and 0.3 ev) and d l s (50 and 500 nm) are shown in Fig. 10. At a low-enough Φ b, I dsat is dominated by 2), being mainly contributed by the carriers injected via the region close to the channel/dielectric interface, as shown in Fig. 10(I) and (III). Therefore, I dsat shows little dependence on the variations of both Φ b and d l. After Φ b increases to a certain value, I dsat becomes contact barrier limited, and thus, I dsat becomes more sensitive to the change of Φ b. The carriers injected relatively far away from the channel/dielectric interface also start to contribute to a considerable part of the current, as shown in Fig. 10(II). With the increase of d l causing a change of the local 2-D electrical field distribution, some of those injected carriers transport to the top right corner of the source contact region, as shown in Fig. 10(IV), resulting in the reduction of I dsat. It can be concluded for this part that, as d l increases, the I dsat of the inverted coplanar structure OTFT becomes more sensitive to the variation of Φ b, which, on the other hand, also means that a steeper step coverage profile will help to achieve better tolerance of I dsat to Φ b variations in the inverted coplanar structure OTFTs. For the staggered structure OTFT, Fig. 10. Simulated hole current density contours (at bias voltages of V gs = 8 VandV ds = 25 V) of the inverted coplanar structure OTFTs at the source end region of the channel: (I) d l = 50 nm and Φ b = 0eV, (II) d l = 50 nm and Φ b = 0.3 ev, (III) d l = 500 nm and Φ b = 0eV,and (IV) d l = 500 nm and Φ b = 0.3 ev. the change of I dsat with Φ b is not much affected by the variation of the step coverage profile, and the increase of d l only slightly decreases I dsat. IV. CONCLUSION The contact barrier effects on the electrical performance of two BC structure (staggered and inverted coplanar) OTFTs have been comparatively studied by 2-D numerical simulations. The different gate structures, S/D electrode thicknesses, and step coverage profile variations formed by deposition of organic semiconductor films on top of the S/D electrodes were taken into consideration in this study. It is found that the different gate structures (self-aligned and fully covered) do not affect the contact barrier effects on the driving current of both structure OTFTs. When the contact barrier height increases beyond a certain value (0.15 ev in this study), the drain saturation current of the inverted coplanar structure OTFT drops rapidly with the further increase of the contact barrier with the rate being dependent on the step coverage profile. Different from that of the inverted coplanar structure, the drain saturation current of the staggered structure OTFT is much less influenced by the contact barrier height. Although the variation of the step coverage profile slightly affects the drain saturation current, its effects on the contact barrier dependence of the electrical performance are negligible. It is also found that the drain saturation current of the staggered structure OTFT is much more sensitive to the variation of the S/D electrode thickness than that of the inverted coplanar structure OTFT. The related physical mechanisms have been discussed. It can be concluded that, at low-enough contact barriers, both BC device structures show little dependence on the variations of the contact barrier height, while the inverted coplanar devices are much more tolerant to process-induced variations including the electrode thickness and the step coverage profile. These findings could provide important guidelines for device structure optimal design and process development for OTFTs in practical circuit integration applications.

7 3388 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 12, DECEMBER 2012 ACKNOWLEDGMENT The authors would like to thank the reviewers for their insightful and constructive comments that help improve this paper. REFERENCES [1] E. Cantatore, T. C. T. Geuns, G. H. Gelinck, E. van Veenendaal, A. F. A. Gruijthuijsen, L. Schrijnemakers, S. Drews, and D. M. de Leeuw, A MHz RFID system based on organic transponders, IEEE J. Solid-State Circuits, vol. 42, no. 1, pp , Jan [2] Y. Noguchi, T. Sekitani, and T. Someya, Organic-transistor-based flexible pressure sensors using ink-jet-printed electrodes and gate dielectric layers, Appl. Phys. Lett., vol. 89, no. 25, pp , Dec [3] H. Edzer, A. Huitema, G. H. Gelinck, P. J. G. Van Lieshout, E. Van Veenendaal, and F. J. Touwslager, Flexible electronic-paper active-matrix displays, J. SID, vol. 14, no. 8, pp , Aug [4] L. Zhou, A. Wanga, S.-C. Wu, J. Sun, S. Park, and T. N. Jackson, Allorganic active matrix flexible display, Appl. Phys. Lett., vol. 88, no. 8, pp , Feb [5] Y. Roichman and N. Tessler, Structures of polymer field-effect transistor: Experimental and numerical analyses, Appl. Phys. Lett., vol. 80, no. 1, pp , Jan [6] Y. Ishikawa, Y. Wade, and T. Toyabe, Origin of characteristics differences between top and bottom contact organic thin film transistors, J. Appl. Phys., vol. 107, no. 5, pp , Mar [7] I. G. Hill, Numerical simulations of contact resistance in organic thinfilm transistors, Appl. Phys. Lett., vol. 87, no. 16, pp , Oct [8] J. Yuan, J. Zhang, J. Wang, X. Yan, D. Yan, and W. Xu, Bottom-contact organic field-effect transistors having low-dielectric layer under source and drain electrodes, Appl. Phys. Lett., vol. 82, no. 22, pp , Jun [9] M. Mizukami, N. Hirohata, T. Iseki, K. Ohtawara, T. Tada, S. Yagyu, T. Abe, T. Suzuki, Y. Fujisaki, Y. Inoue, S. Tokito, and T. Kurita, Flexible AM OLED panel driven by bottom-contact OTFTs, IEEE Electron Dev. Lett., vol. 27, no. 4, pp , Apr [10] E. Huitema, G. Gelinck, P. V. Lieshout, E. V. Veenendaal, and F. Touwslager, Flexible electronic-paper active-matrix displays, J. SID, vol. 13, no. 3, pp , Mar [11] S. E. Burns, K. Reynolds, W. Reeves, M. Banach, T. Brown, K. Chalmers, N. Cousins, M. Etchells, C. Hayton, K. Jacobs, A. Menon, S. Siddique, P. Too, C. Ramsdale, J. Watts, P. Cain, T. Von Werne, J. Mills, C. Curling, H. Sirringhaus, K. Amundson, and M. D. McCreary, A scalable manufacturing process for flexible active-matrix e-paper displays, J. SID, vol. 13, no. 7, pp , Jul [12] H. Ma, H. L. Yip, F. Huang, and K. Y. Jen, Interface engineering for organic electronics, Adv. Funct. Mater., vol. 20, no. 9, pp , May [13] C. H. Shim, F. Maruoka, and R. Hattori, Structural analysis on organic thin-film transistor with device simulation, IEEE Trans. Electron Devices, vol. 57, no. 1, pp , Jan [14] D. J. Gundlach, L. Zhou, J. A. Nichols, T. N. Jackson, P. V. Necliudov, and M. S. Shur, An experimental study of contact effects in organic thin film transistors, J. Appl. Phys.,vol.100,no.2,pp , Jul [15] ATLAS User s Manual, Silvaco Int. Inc., Santa Clara, CA, [16] T. J. Richards and H. Sirringhaus, Analysis of the contact resistance in staggered, top-gate organic field-effect transistors, J. Appl. Phys., vol. 102, no. 9, pp , Nov [17] D. Gupta, M. Katiyar, and D. Gupta, An analysis of the difference in behavior of top and bottom contact organic thin film transistors using device simulation, Org. Electron., vol.10,no.5,pp ,Aug [18] S. Cherian, D. Carrie, M. David, L. LaRussa, W. Xia, and N. Armstrong, Effects of field dependent mobility and contact barriers on liquid crystalline phthalocyanine organic transistors, J. Appl. Phys., vol. 96, no. 10, pp , Nov [19] A. Bolognesi, M. Berliocchi, M. Manenti, A. Di Carlo, P. Lugli, K. Lmimouni, and C. Dufour, Effects of grain boundaries, fielddependent mobility, and interface trap states on the electrical characteristics of pentacene TFT, IEEE Electron Device Lett., vol. 51, no. 12, pp , Dec [20] A. Bolognesi, A. D. Carlo, and P. Lugli, Influence of carrier mobility and contact barrier height on the electrical characteristics of organic transistors, Appl. Phys. Lett., vol. 81, no. 24, pp , Dec [21] O. Marinov, M. J. Deen, J. A. J. Tejada, and B. Iniguez, Impact of the fringing capacitance at the back of thin-film transistors, Org. Electron., vol. 12, no. 6, pp , Jun Linrun Feng received the B.E. degree from Huazhong University of Science and Technology, Wuhan, China, in He is currently working toward the Ph.D. degree at Shanghai Jiao Tong University, Shanghai, China. Xiaoli Xu received the B.E. and M.S. degrees from Nanjing University of Science and Technology, Nanjing, China. She is currently working toward the Ph.D. degree at Shanghai Jiao Tong University, Shanghai, China. Xiaojun Guo (M 07) received the Ph.D. degree from the University of Surrey, Guildford, U.K., in He is currently a Professor with the Department of Electronic Engineering, Shanghai Jiao Tong University, Shanghai, China.