= 25 o C unless other wise noted Symbol Parameter N-Channel P-Channel Units. Drain-Source Voltage V. Gate-Source Voltage 8-8 V I D

Size: px

Start display at page:

Download "= 25 o C unless other wise noted Symbol Parameter N-Channel P-Channel Units. Drain-Source Voltage V. Gate-Source Voltage 8-8 V I D"

Derick Cobb
5 years ago
Views:

November 998 FG63C ual N & P Channel igital FET General escription These dual N & P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell

1 November 998 FG63C ual N & P Channel igital FET General escription These dual N & P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, MOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETS. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with different bias resistor values. Features N-Ch., V, R S(ON) =. =. V, R S(ON) =. =.7 V. P-Ch -., -V, R S(ON) = = -.V, R S(ON) = 3 = -.7V. Very small package outline SC7-6. Very low level gate drive requirements allowing direct operation in 3 V circuits ((th) <. V). Gate-Source Zener for ES ruggedness (>6kV Human Body Model). SC7-6 SOT-3 SuperSOT TM -6 SOT-8 SO-8 SOIC- G S. 6 SC7-6 pin G S 3 bsolute Maximum Ratings T = o C unless other wise noted Symbol Parameter N-Channel P-Channel Units V SS rain-source Voltage - V S Gate-Source Voltage 8-8 V I rain Current - Continuous Pulsed.6 -. P Maximum Power issipation (Note ).3 W,T STG Operating and Storage Temperature Ranger - to C ES Electrostatic ischarge Rating MIL-ST-883 Human Body Model (pf / Ohm) THERML CHRCTERISTICS 6 kv R θj Thermal Resistance, Junction-to-mbient (Note ) C/W 998 Fairchild Semiconductor Corporation FG63C Rev.

2 Electrical Characteristics (T = O C unless otherwise noted ) Symbol Parameter Conditions Type Min Typ Max Units OFF CHRCTERISTICS BV SS rain-source Breakdown Voltage = V, I = µ N-Ch V = V, I = - µ P-Ch - BV SS / Breakdown Voltage Temp. Coefficient I = µ, Referenced to o C N-Ch mv/ o C I = - µ, Referenced to o C P-Ch -9 I SS Zero Gate Voltage rain Current V S = V, = V, N-Ch µ = C I SS Zero Gate Voltage rain Current V S =- V, = V, P-Ch - µ = C - I S Gate - Body Leakage Current = 8 V, V S = V N-Ch n = -8 V, V S = V P-Ch - n ON CHRCTERISTICS (Note ) (th) Gate Threshold Voltage V S =, I = µ N-Ch.6.8. V V S =, I = - µ P-Ch (th) / Gate Threshold Voltage Temp. Coefficient I = µ, Referenced to o C N-Ch -. mv/ o C I = - µ, Referenced to o C P-Ch. R S(ON) Static rain-source On-Resistance =. V, I =. N-Ch.6 Ω =.3 7 =.7 V, I = = -. V, I = -. P-Ch 7.3 = 7 = -.7 V, I = I (ON) On-State rain Current =. V, V S = V N-Ch. = -. V, V S = - V P-Ch -. g FS Forward Transconductance V S = V, I =. N-Ch. S V S = - V, I = -. P-Ch. YNMIC CHRCTERISTICS C iss Input Capacitance N-Channel N-Ch 9. pf V S = V, = V, P-Ch C oss Output Capacitance f =. MHz N-Ch 6 P-Channel P-Ch 7 C rss Reverse Transfer Capacitance V S = - V, = V, N-Ch.3 f =. MHz P-Ch. FG63C Rev.

3 Electrical Characteristics (continued) SWITCHING CHRCTERISTICS (Note ) Symbol Parameter Conditions Type Min Typ Max Units t (on) Turn - On elay Time N-Channel N-Ch ns V = V, I =., P-Ch t r Turn - On Rise Time =. V, R GEN = Ω N-Ch. ns P-Ch 8 6 t (off) Turn - Off elay Time P-Channel N-Ch 8 ns V = - V, I = -., P-Ch 9 8 t f Turn - Off Fall Time = -. V, R GEN = Ω N-Ch 3. 7 ns P-Ch Q g Total Gate Charge N-Channel N-Ch.9. nc V S = V, I =., P-Ch..3 Q gs Gate-Source Charge =. V N-Ch. nc P- Channel P-Ch. Q gd Gate-rain Charge V S = - V, I = -., N-Ch.3 nc RIN-SOURCE IOE CHRCTERISTICS N MXIMUM RTIN = -. V P-Ch. I S Maximum Continuous rain-source iode Forward Current N-Ch. P-Ch -. V S rain-source iode Forward Voltage = V, I S =. (Note ) N-Ch.8. V = V, I S = -. (Note ) P-Ch Notes:. R θj is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R θjc is guaranteed by design while R θc is determined by the user's board design. R θj = O C/W on minimum mounting pad on FR- board in still air.. Pulse Test: Pulse Width < 3µs, uty Cycle <.%. FG63C Rev.

4 S Typical Electrical Characteristics: N-Channel I, RIN-SOURCE CURRENT () =.V 3.V 3.V.7V.V.V R S(ON), NORMLIZE RIN-SOURCE ON-RESISTNCE V =.V.7V 3.V 3.V.V.V.V 3 V S, RIN-SOURCE VOLTGE (V)...3. I, RIN CURRENT () Figure. On-Region Characteristics. Figure. On-Resistance Variation with rain Current and Gate Voltage. R S(ON), NORMLIZE RIN-SOURCE ON-RESISTNCE I =. =.V T, JUNCTION TEMPERTURE ( C) J R S(ON), ON-RESISTNCE(OHM) 6 8 T = 3 V,GTE TO SOURCE VOLTGE (V) I =. Figure 3. On-Resistance Variation with Temperature. Figure. On-Resistance Variation with Gate-to-Source Voltage. I, RIN CURRENT ().... V = V S T = - C J I, REVERSE RIN CURRENT ().... = V T = J - C... 3, GTE TO SOURCE VOLTGE (V) V S, BOY IOE FORWR VOLTGE (V) Figure. Transfer Characteristics. Figure 6. Body iode Forward Voltage Variation with Source Current and Temperature. FG63C.Rev

5 Typical Electrical Characteristics: N-Channel (continued) V, GTE-SOURCE VOLTGE (V) 6 3 I =. V S = V V Q g, GTE CHRGE (nc) CPCITNCE (pf) f = MHz = V..3 3 V S, RIN TO SOURCE VOLTGE (V) C iss C oss C rss Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics. I, RIN CURRENT ().3..3 RS(ON) LIMIT =.V SINGLE PULSE R θj = C/W T =...8 C s s V S, RIN-SOURCE VOLTGE (V) ms ms POWER (W) SINGLE PULSE TIME (SEC) SINGLE PULSE R θj= C/W T = Figure 9. Maximum Safe Operating rea. Figure. Single Pulse Maximum Power issipation. FG63C.Rev

6 S Typical Electrical Characteristics: P-Channel -I, RIN-SOURCE CURRENT ().... = -.V -3.V -3.V -.7V -.V 3 -V S, RIN-SOURCE VOLTGE (V) -.V Figure. On-Region Characteristics. R S(ON), NORMLIZE RIN-SOURCE ON-RESISTNCE.. = -.V -.V -.7V -3.V I, RIN CURRENT () -3.V -.V -.V Figure. On-Resistance Variation with rain Current and Gate Voltage. R S(ON), NORMLIZE RIN-SOURCE ON-RESISTNCE I = -. = -.V , JUNCTION TEMPERTURE ( C) Figure 3. On-Resistance Variation with Temperature. R S(ON), ON-RESISTNCE (OHM) T = V, GTE TO SOURCE VOLTGE (V) I = -.7 T = Figure. On-Resistance Variation with Gate-to-Source Voltage. -I, RIN CURRENT () V S = -.V T = - C -I, REVERSE RIN CURRENT ().3... = V T = - C 3 -V, GTE TO SOURCE VOLTGE (V) V, BOY IOE FORWR VOLTGE (V) S Figure. Transfer Characteristics. Figure 6. Body iode Forward Voltage Variation with Source Current and Temperature. FG63C.Rev

7 Typical Electrical Characteristics: P-Channel (continued) -, GTE-SOURCE VOLTGE (V) 8 I = -. 6 V = -V S -V -V Q g, GTE CHRGE (nc) CPCITNCE (pf) 3 C rss f = MHz = V.... -V, RIN TO SOURCE VOLTGE (V) S C iss C oss Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics. -I, RIN CURRENT ().3..3 RS(ON) LIMIT = -.V SINGLE PULSE R θj= See Note b T =. 3 C s s ms - V S, RIN-SOURCE VOLTGE (V) ms POWER (W) SINGLE PULSE TIME (SEC) SINGLE PULSE R θj= C/W T = Figure 9. Maximum Safe Operating rea. Figure. Single Pulse Maximum Power issipation. FG63C.Rev

8 Typical Thermal Characteristics: N & P-Channel (continued) r(t), NORMLIZE EFFECTIVE TRNSIENT THERML RESISTNCE = Single Pulse..... t, TIME (sec) Figure. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in note. Transient thermalresponse will change depending on the circuit board design. P(pk) R θj (t) = r(t) * R θj R θj = C/W t t - T = P * R θj (t) uty Cycle, = t / t FG63C.Rev

9 TREMRKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ISCLIMER CEx CoolFET CROSSVOLT E CMOS TM FCT FCT Quiet Series FST FSTr GTO HiSeC ISOPLNR MICROWIRE POP PowerTrench QFET QS Quiet Series SuperSOT -3 SuperSOT -6 SuperSOT -8 TinyLogic UHC VCX FIRCHIL SEMICONUCTOR RESERVES THE RIGHT TO MKE CHNGES WITHOUT FURTHER NOTICE TO NY PROUCTS HEREIN TO IMPROVE RELIBILITY, FUNCTION OR ESIGN. FIRCHIL OES NOT SSUME NY LIBILITY RISING OUT OF THE PPLICTION OR USE OF NY PROUCT OR CIRCUIT ESCRIBE HEREIN; NEITHER OES IT CONVEY NY LICENSE UNER ITS PTENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FIRCHIL S PROUCTS RE NOT UTHORIZE FOR USE S CRITICL COMPONENTS IN LIFE SUPPORT EVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN PPROVL OF FIRCHIL SEMICONUCTOR CORPORTION. s used herein:. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. PROUCT STTUS EFINITIONS efinition of Terms. critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. atasheet Identification Product Status efinition dvance Information Preliminary No Identification Needed Formative or In esign First Production Full Production This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.

FDC6301N Dual N-Channel, Digital FET

FDC6301N Dual N-Channel, Digital FET September FC6N ual N-Channel, igital FET General escription These dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchild 's proprietary, high cell density, MOS