Characteristic Value Units Drain-to-Source Voltage. 28 Continuous Drain Current (T C =100 )

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1 dvanced Power MOSFET IRFW/I50 FETURES n valanche Rugged Technology n Rugged Gate Oxide Technology n Lower Input Capacitance n Improved Gate Charge n Extended Safe Operating rea n 75 Operating Temperature n Lower Leakage Current : 0 μ = 00 n Lower R DS(ON) : 0.0 Ω (Typ.) bsolute Maximum Ratings BS = 00 R DS(on) = 0.05 Ω I D = 8 D -PK I -PK. Gate. Drain. Source S I D I DM E S I R E R dv/dt P D T J, T STG T L Characteristic alue Units Drain-to-Source oltage 00 Continuous Drain Current (T C =5 ) 8 Continuous Drain Current (T C =00 ) 9.8 Drain Current-Pulsed Gate-to-Source oltage Single Pulsed valanche Energy valanche Current Repetitive valanche Energy Peak Diode Recovery dv/dt Total Power Dissipation (T =5 ) * Total Power Dissipation (T C =5 ) Linear Derating Factor Operating Junction and Storage Temperature Range 0 ± to +75 mj mj /ns W W W/ Maximum Lead Temp. for Soldering 00 Purposes, /8? from case for 5-seconds Thermal Resistance Characteristic Typ. Max. Units R θjc Junction-to-Case. R θj Junction-to-mbient * 0 /W R θj Junction-to-mbient 6.5 * When mounted on the minimum pad size recommended (PCB Mount). Rev. B 00 Fairchild Semiconductor Corporation

2 IRFW/I50 N-CHNNEL Electrical Characteristics (T C =5 unless otherwise specified) Characteristic Min. Typ. Max. Units Test Condition BS Drain-Source Breakdown oltage 00 =0,I D =50μ ΔB/ΔT J Breakdown oltage Temp. Coeff. 0. / I D =50μ See Fig 7 (th) Gate Threshold oltage.0.0 =5,I D =50μ I GSS Gate-Source Leakage, Forward Gate-Source Leakage, Reverse n =0 =-0 I DSS Drain-to-Source Leakage Current 0 00 μ =00 =80,T C =50 R DS(on) Static Drain-Source On-State Resistance 0.05 Ω =0,I D = g FS Forward Transconductance.56 S =0,I D = C iss C oss C rss Input Capacitance Output Capacitance Reverse Transfer Capacitance pf =0, =5,f =MHz See Fig 5 t d(on) t r t d(off) t f Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time ns =50,I D =8, R G =9.Ω See Fig 5 Q g Total Gate Charge =80, =0, Q gs Gate-Source Charge 0.8 nc I D =8 Q gd Gate-Drain( 밠 iller? Charge 7.9 See Fig 6 & Fig 5 Source-Drain Diode Ratings and Characteristics Characteristic Min. Typ. Max. Units Test Condition I S I SM Continuous Source Current Pulsed-Source Current 8 0 Integral reverse pn-diode in the MOSFET SD Diode Forward oltage.5 T J =5,I S =8, =0 t rr Reverse Recovery Time ns T J =5,I F =8 Q rr Reverse Recovery Charge 0.6 μc di F /dt=00/μs Notes ; Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature L=mH, I S =8, =5, R G =7Ω, Starting T J =5 I SD 8, di/dt 00/μs, BS, Starting T J =5 Pulse Test : Pulse Width = 50μs, Duty Cycle % 5 Essentially Independent of Operating Temperature

3 N-CHNNEL IRFW/I Top : Bottom :.5 Fig. Output Characteristics. 50 µs Pulse Test. T C = 5 o C , Drain-Source oltage [] o C Fig. Transfer Characteristics 75 o C - 55 o C. = 0. = µs Pulse Test , Gate-Source oltage [] 0.08 Fig. On-Resistance vs. Drain Current 0 Fig. Source-Drain Diode Forward oltage R DS(on), [ Ω] Drain-Source On-Resistance = 0 = Note : T J = 5 o C I DR, Reverse Drain Current [] 0 75 o C 5 o C. = µs Pulse Test SD, Source-Drain oltage [] Capacitance [pf] Fig 5. Capacitance vs. Drain-Source oltage C iss C iss = C gs + C gd ( C ds = shorted ) C oss = C ds + C gd C rss = C gd C oss C rss , Drain-Source oltage []. = 0. f = MHz, Gate-Source oltage [] 0 5 Fig 6. Gate Charge vs. Gate-Source oltage = 50 = 80 = 0 I D = Q G, Total Gate Charge [nc]

4 IRFW/I50 N-CHNNEL. Fig 7. Breakdown oltage vs. Temperature.0 Fig 8. On-Resistance vs. Temperature BS, (Normalized) Drain-Source Breakdown oltage = 0. I D = 50 µ R DS(on), (Normalized) Drain-Source On-Resistance = 0. I D = T J, Junction Temperature [ o C] T J, Junction Temperature [ o C] Fig 9. Max. Safe Operating rea Operation in This rea is Limited by R DS(on) 00 µs ms 0 ms DC 0 0. T C = 5 o C. T J = 75 o C. Single Pulse , Drain-Source oltage [] 0 µs Fig 0. Max. Drain Current vs. Case Temperature T c, Case Temperature [ o C] Fig. Thermal Response Z θjc (t), Thermal Response D= single pulse. Z θ JC (t)=. o C/W Max.. Duty Factor, D=t /t. T JM -T C =P DM *Z θ JC (t) P DM t t t, Square Wave Pulse Duration [sec]

5 N-CHNNEL IRFW/I50 Fig. Gate Charge Test Circuit & Waveform * Current Regulator 50KΩ 00nF 00nF Same Type as 0 Q g Q gs Q gd m Current Sampling (I G ) Resistor R R Current Sampling (I D ) Resistor Charge Fig. Resistive Switching Test Circuit & Waveforms R L in out ( 0.5 rated ) out 90% R G 0 in 0% t d(on) t r t d(off) tf t on t off Fig. Unclamped Inductive Switching Test Circuit & Waveforms L L E S = L L I S BS BS ary t p to obtain required peak I D ID BS I S R G C I D (t) 0 (t) t p t p Time 5

6 IRFW/I50 N-CHNNEL Fig 5. Peak Diode Recovery dv/dt Test Circuit & Waveforms + I S L Driver RG Same Type as dv/dt controlled by 밨 G I S controlled by Duty Factor 밆? ( Driver ) Gate Pulse Width D = Gate Pulse Period 0 I S ( ) I FM, Body Diode Forward Current di/dt I RM ( ) Body Diode Reverse Current Body Diode Recovery dv/dt f Body Diode Forward oltage Drop 6

7 TRDEMRKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. CEx Bottomless CoolFET CROSSOLT DenseTrench DOME EcoSPRK E CMOS TM EnSigna TM FCT FCT Quiet Series STR*POWER is used under license DISCLIMER FIRCHILD SEMICONDUCTOR RESERES THE RIGHT TO MKE CHNGES WITHOUT FURTHER NOTICE TO NY PRODUCTS HEREIN TO IMPROE RELIBILITY, FUNCTION OR DESIGN. FIRCHILD DOES NOT SSUME NY LIBILITY RISING OUT OF THE PPLICTION OR USE OF NY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONEY NY LICENSE UNDER ITS PTENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FIRCHILD S PRODUCTS RE NOT UTHORIZED FOR USE S CRITICL COMPONENTS IN LIFE SUPPORT DEICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN PPROL OF FIRCHILD SEMICONDUCTOR CORPORTION. s used herein:. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. PRODUCT STTUS DEFINITIONS Definition of Terms FST FSTr FRFET GlobalOptoisolator GTO HiSeC ISOPLNR LittleFET MicroFET MicroPak MICROWIRE OPTOLOGIC OPTOPLNR PCMN POP Power7 PowerTrench QFET QS QT Optoelectronics Quiet Series SILENT SWITCHER SMRT STRT STR*POWER Stealth SuperSOT - SuperSOT -6 SuperSOT -8 SyncFET TinyLogic TruTranslation UHC UltraFET. critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Datasheet Identification Product Status Definition CX dvance Information Preliminary No Identification Needed Formative or In Design First Production Full Production This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H

Dual N & P-Channel Enhancement Mode Field Effect Transistor. Features R DS(ON) = V GS = 4.5 V G2 6 Q1(N) TA=25 o C unless otherwise noted

Dual N & P-Channel Enhancement Mode Field Effect Transistor May General Description These dual N & P-Channel Enhancement Mode Field Effect Transistors are produced using Fairchild s proprietary, high cell