Appendix A: Logic Gates and Boolean Algebra Used in the Book

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1 ppendix : Logic Gates and oolean lgebra Used in the ook This appendix provides a brief set of notes on oolean algebra laws and their use. It is assumed that the reader already has knowledge of these laws. The appendix is provided as a reference only for the oolean algebra used in this book.. SI GTE SYMOLS USED IN THE OOK WITH OOLEN EQUTIONS UK Logic Symbols US Logic Symbols + OR Gate +. ND Gate. / NOT Gate / NOR Gate + = /( + ) + = /( + ) NND Gate. = /(. ). = /(. ) uffer uffered uffered Figure. asic logic gates. FSM-based Digital Design using Verilog HDL Peter Minns and Ian Elliott # 28 John Wiley Sons, Ltd. ISN:

2 338 ppendix.2 THE EXLUSIVE OR ND EXLUSIVE NOR The exclusive OR and exclusive NOR (Figure.2) are well used in logic systems. UK Logic Gate Symbol = ^ Exclusive OR US Logic Gate Symbol ^ This gate is made up from ND/OR/NOT gates from the oolean equation F =. / + /. F /F /F is the Exclusive NOR = /( ^ ) /( ^ ) UK Exclusive NOR US Exclusive NOR Exclusive NOR provides comparison between bits and. Figure.2 Exclusive OR and exclusive NOR symbols..3 LWS OF OOLEN LGER These are presented in terms of the oolean logic equation and gate circuit.

3 Laws of oolean lgebra asic OR Rules + = + = + = + / = / / / Figure.3 oolean algebra basic OR rules..3.2 asic ND Rules. =. =. =. / = / / / Figure.4 oolean algebra basic ND rules.

4 34 ppendix.3.3 ssociative and ommutative Laws ssociative Laws: ( + + ) = + ( + ) = (.. ) =. (. ) =.. ommutative Laws: + = +. =. These two rules indicate that the order of the literal variables (,, and ) can be regrouped (associative rule) and changed (commutative rule). Figure.5 ssociative and commutative laws..3.4 Distributive Laws Distributive Laws: F =. ( + ) = Figure.6 Distributive laws.

5 Laws of oolean lgebra uxiliary Law for Static Hazard Removal The auxiliary law (Figure.7) is particularly significant and much used in this book. uxiliary Law: Special ase of onsensus Theorem + ( ) = ( + ) ( + ) and ( + ) ( + ) = + ( ) The right hand side shows a circuit reduction. However, a more interesting example + (/ ) = ( + /) ( + ) = ( + ) = + This illustrates a reduction and also the elimination of a static hazard since if = ( + /) ( + ) = ( + /). Try x + (/x z) =? nd /p + (q p) =? Figure.7 uxiliary law Proof of uxiliary Rule The answer to the first question in Figure.7 is as follows Y ¼ x þ =x z ¼ðxþ =xþðxþzþ ¼ x x þ x z þ =x x þ =x z ¼ x þ x z þ þ =x z ¼ x ðþzþþ=xz ¼ x þ =x z: The answer to the second question in Figure.7, =p þðq pþ ¼?, is, of course, =p þ q. Note that the auxiliary (ux) rule is just a special case of the consensus theorem.

6 342 ppendix.3.6 onsensus Theorem onsider the equation Y ¼ x þ =x w z: In the equation, if w ¼ z ¼, then Y ¼ x þ =x ¼ x þ =x; which is. However, it is possible under some conditions of gate delay that a logic glitch can occur (this is known as a static hazard). To avoid this, a cover term can be added, made up from the literals w and z, to make Y stay at logic : Thus, when w and z are both : Y ¼ x þ =x w z þ w z: Y ¼ x þ =x þ ; thus covering the potential terms x þ =x and preventing the glitch. Now consider the equation Now add a cover term thus: Y ¼ x þ =xw: Y ¼ x þ =xw þ w ¼ x þ wð=x þ Þ ¼ x þ w: So applying the consensus theorem to Y ¼ x þ =xw results in Y ¼ x þ w as obtained using the auxiliary rule. In effect the ux rule is just a special case of the consensus theorem; that is, it is an auxiliary to the consensus theorem. nother example (using the ux rule): since Y ¼ =x þ x z ¼ =x þ z; =x þ x z ¼ð=xþxÞð=xþzÞ ¼ ð=xþzþ ¼ =x þ z:

7 In the following two examples the term to be removed is crossed out thus /R. Therefore: P ¼ q r þ q =r s ¼ q:ðr þ =r sþ ¼ q ðr þ =r sþ ¼ q ðr þ sþ ¼ q r þ q s Y ¼ s t =x þ s t x z ¼ s : t : ð=x þ x zþ ¼ s t ð=x þ zþ: Y ¼ s t =x þ s t z: Laws of oolean lgebra 343 Note that the reduction here is in the number of inputs. This might be relevant in some cases, but when implementing with PLD devices it may not be so relevant owing to the large number of inputs available in the ND gate array of the PLD. Remember, however, that the application of the ux rule eliminates a static hazard and, hence, a potential glitch: in the case of P, the term r þ =r; in the case of Y; =x þ x..3.7 The Effect of Signal Delay in Logic Gates In hapters 3, 4 and 9, it was shown that signal delay can affect the behaviour of a circuit. The basic effect of signal delay is clearly illustrated in Figure.8, where the points on the two input signals and / where an output change can occur are seen for each gate type. In the case of ND (or NND) gates, it is the point at which the two overlapping signals are both at logic. Inthe case of OR(or NOR) gates, it is the point at whichthe two overlapping signals are both at logic. The effect is to produce an unwanted glitch at the gate output. These so-called glitches can result in maloperation in an FSM. They can occur in a logic system where two signals (they do not need to be the same signals inverted, as shown in Figure.8) change state at the same time. This could be a change of two state variables; for example, when unit distance coding is not used in a state diagram. This kind of behaviour can manifest itself within a logic block where two signal changes occur, due to the delays through the logic gates. Further work on this type of behaviour can be found in most textbooks on advanced digital design. These are not discussed any further, as they are beyond the scope of this book..3.8 De Morgan s Theorem De Morgan s theorem (Figure.9) is used significantly, particularly in hapter 9.

8 344 ppendix / / / / / Figure.8 Effect of delayed signals on gate outputs. De Morgan s Theorem: very often used. /(.. ) = / + / + / /(++) /+/+/ /( + + ) = /. /. / /( + + ) /. /. / Figure.9 De Morgan s theorem.

9 Examples of pplying the Laws of oolean lgebra 345 De-Morgan s rules are often used to convertfrom NND, =(a b), to NOR, =a þ =b, and from NOR, =(a þ b), to NND, =a =b..4 EXMPLES OF PPLYING THE LWS OF OOLEN LGER.4. Example: onverting ND OR to NND Z ¼ x y þ =x =y: Use the De Morgan rule: /( þ Þ ¼= =, where and can be any product term. So, in the following example, is replaced by x y,and is replaced by /x =y: Z ¼ ==Z ¼ ==ðx y þ =x =yþ ¼ =ð=ðx yþ=ð=x =yþþ:.4.2 Example: onverting ND OR to NOR Use the De Morgan rule: /( Þ ¼= þ =, where and can be any product term. So, in the following example, is replaced by x y and is replaced by /x =y: Z ¼ x y þ =x =y ¼ ==Z ¼ ==ðx y þ =x =yþ ¼ ==ð==ðx yþþ==ð=x =yþþ ¼ ==ð=ð=x þ =yþþ=ðxþyþþ:.4.3 Logical djacency Rule This ruleisused inthe Karnaugh map method ofoolean algebra minimization and works on the idea that b þ =b ¼ ; so, in the equation thus eliminating the literal c (in this case). F ¼ b c þ b =c ¼ b ðcþ =cþ ¼ b ¼ b;

10 346 ppendix The following example makes use of the Logical adjacency rule: X ¼ a =b c þ a b c ¼ a cð=b þ bþ ¼ a c ¼ a c: In the next example, the rule is applied twice: Q ¼ =a =b =c þ =a =b c þ a b =c þ a =b =c ¼ =a =b ð=c þ cþþa =c ðb þ =bþ ¼ =a =b þ a =c: The logical adjacency rule is used in most of thework on synchronous FSM design, and also in establishing correct operation in asynchronous (event) FSM design in hapter 9. oththe ux ruleand the logical adjacency rules are often usedin the reduction ofthe flip-flop D, and T equations. That is, a typical equation from a state diagram could be d ¼ = st þ þ = sp ¼ st þ þ sp: This is obtained from d ¼ ð=st þ Þþðþ =spþ ¼ ðst þ ÞþðþspÞ ¼ st þ þ þ sp: Now: þ ¼ : Therefore: d ¼ st þ þ sp:.5 SUMMRY This appendix has looked briefly at the basic laws of oolean algebra and discussed some of the oolean techniques used in this book. It provides a reference source for those readers who have not used oolean algebra for some time. Further information can be found in most books on digital logic.

CHAPTER 3 LOGIC GATES & BOOLEAN ALGEBRA

CHAPTER 3 LOGIC GATES & BOOLEAN ALGEBRA CHPTER 3 LOGIC GTES & OOLEN LGER C H P T E R O U T C O M E S Upon completion of this chapter, student should be able to: 1. Describe the basic logic gates operation 2. Construct the truth table for basic