LOW POWER SCHOTTKY. MODE SELECT TRUTH TABLE GUARANTEED OPERATING RANGES ORDERING INFORMATION
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1 Te SN74S76A offers individua,, Cock Puse, Direct Set and Direct Cear inputs. Tese dua fip-fops are designed so tat wen te cock goes IG, te inputs are enabed and data wi be accepted. Te ogic eve of te and inputs wi perform according to te Trut Tabe as ong as minimum set-up times are observed. Input data is transferred to te outputs on te IG-to-OW cock transitions. ODE SEECT TRUT TABE OPERATING INPUTS OUTPUTS ODE S D C D Set Reset (Cear) *Undetermined Togge oad 0 (Reset) oad (Set) od * Bot outputs wi be IG wie bot S D and C D are OW, but te output states are unpredictabe if S D and C D go IG simutaneousy., = IG Votage eve, I = OW Votage eve = Immateria, () = ower case etters indicate te state of te referenced input i, () = (or output) one setup time prior to te IG to OW cock transition OW POWER SCOTTY PASTIC N SUFFI CASE 648 SOIC D SUFFI CASE 75B GUARANTEED OPERATING RANGES Symbo Parameter in Typ ax Unit V CC Suppy Votage V T A Operating Ambient Temperature Range C I O Output Current ig 0.4 ma I O Output Current ow 8.0 ma ORDERING INFORATION Device Package Sipping SN74S76AN Pin DIP 2000 Units/Box SN74S76AD Pin 2500/Tape & Ree Semiconductor Components Industries, C, 999 December, 999 Rev. 6 Pubication Order Number: SN74S76A/D
2 SN74S76A OGIC DIAGRA 2 OGIC SYBO 7 S D 5 2 S D CP 6 CP CEAR (C D ) COC (CP) SET (S D ) 4 C D V CC = PIN 5 GND = PIN 3 DC CARACTERISTICS OVER OPERATING TEPERATURE RANGE (uness oterwise specified) imits Symbo Parameter in Typ ax Unit Test Conditions V I Input IG Votage 2.0 V 9 C D Guaranteed Input IG Votage for A Inputs 0 V I Input OW Votage 0.8 V Guaranteed Input OW Votage for A Inputs V I Input Camp Diode Votage V V CC = IN, I IN = 8 ma V O V O Output IG Votage Output OW Votage V V CC = IN, I O = A, V IN = V I or V I per Trut Tabe V I O = 4.0 ma V CC = V CC IN, V IN =V I or V I V I O = 8.0 ma per Trut Tabe I I Input IG Current, Cear Cock, Cear Cock µa V CC = A, V IN = 2.7 V ma V CC = A, V IN = 7.0 V I I Input OW Current, Cear, Cock ma V CC = A, V IN = 0.4 V I OS Sort Circuit Current (Note ) ma V CC = A I CC Power Suppy Current 6.0 ma V CC = A Note : Not more tan one output soud be sorted at a time, nor for more tan second. AC CARACTERISTICS (T A = 25 C, V CC = 5.0 V) imits Symbo Parameter in Typ ax Unit Test Conditions f A aximum Cock Freuency z V 50V t 5 20 ns CC = 5.0 P Cock, Cear, Set to Output C = 5 pf t P 5 20 ns AC SETUP REUIREENTS (T A = 25 C) imits Symbo Parameter in Typ ax Unit Test Conditions t W Cock Puse Widt ig 20 ns t W Cear Set Puse Widt 25 ns t s Setup Time 20 ns V CC =50V 5.0 t od Time 0 ns 2
3 SN74S76A PACAGE DIENSIONS N SUFFI PASTIC PACAGE CASE ISSUE R A 8 G F 9 D P B S C 0.25 (0.00) T SEATING T PANE A NOTES:. DIENSIONING AND TOERANCING PER ANSI Y4.5, CONTROING DIENSION: INC. 3. DIENSION TO CENTER OF EADS WEN FORED PARAE. 4. DIENSION B DOES NOT INCUDE OD FAS. 5. ROUNDED CORNERS OPTIONA. INCES IIETERS DI IN A IN A A B C D F G 0.00 BSC 2.54 BSC BSC.27 BSC S D SUFFI PASTIC SOIC PACAGE CASE 75B 05 ISSUE T SEATING PANE 9 8 G A B D P 0.25 (0.00) T B S A S P 8 P 0.25 (0.00) B S C R 45 F NOTES:. DIENSIONING AND TOERANCING PER ANSI Y4.5, CONTROING DIENSION: IIETER. 3. DIENSIONS A AND B DO NOT INCUDE OD PROTRUSION. 4. AIU OD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIENSION D DOES NOT INCUDE DABAR PROTRUSION. AOWABE DABAR PROTRUSION SA BE 0.27 (0.005) TOTA IN ECESS OF TE D DIENSION AT AIU ATERIA CONDITION. IIETERS INCES DI IN A IN A A B C D F G.27 BSC BSC P R
4 SN74S76A ON Semiconductor and are trademarks of Semiconductor Components Industries, C (SCIC). SCIC reserves te rigt to make canges witout furter notice to any products erein. SCIC makes no warranty, representation or guarantee regarding te suitabiity of its products for any particuar purpose, nor does SCIC assume any iabiity arising out of te appication or use of any product or circuit, and specificay discaims any and a iabiity, incuding witout imitation specia, conseuentia or incidenta damages. Typica parameters wic may be provided in SCIC data seets and/or specifications can and do vary in different appications and actua performance may vary over time. A operating parameters, incuding Typicas must be vaidated for eac customer appication by customer s tecnica experts. SCIC does not convey any icense under its patent rigts nor te rigts of oters. SCIC products are not designed, intended, or autorized for use as components in systems intended for surgica impant into te body, or oter appications intended to support or sustain ife, or for any oter appication in wic te faiure of te SCIC product coud create a situation were persona injury or deat may occur. Soud Buyer purcase or use SCIC products for any suc unintended or unautorized appication, Buyer sa indemnify and od SCIC and its officers, empoyees, subsidiaries, affiiates, and distributors armess against a caims, costs, damages, and expenses, and reasonabe attorney fees arising out of, directy or indirecty, any caim of persona injury or deat associated wit suc unintended or unautorized use, even if suc caim aeges tat SCIC was negigent regarding te design or manufacture of te part. SCIC is an Eua Opportunity/Affirmative Action Empoyer. PUBICATION ORDERING INFORATION Nort America iterature Fufiment: iterature Distribution Center for ON Semiconductor P.O. Box 53, Denver, Coorado 8027 USA Pone: or To Free USA/Canada Fax: or To Free USA/Canada Emai: ONit@ibbertco.com N. American Tecnica Support: To Free USA/Canada EUROPE: DC for ON Semiconductor European Support German Pone: (+) ( F 2:30pm to 5:00pm unic Time) Emai: ONit german@ibbertco.com Frenc Pone: (+) ( F 2:30pm to 5:00pm Tououse Time) Emai: ONit frenc@ibbertco.com Engis Pone: (+) ( F :30pm to 5:00pm U Time) Emai: ONit@ibbertco.com ASIA/PACIFIC: DC for ON Semiconductor Asia Support Pone: (Tue Fri 9:00am to :00pm, ong ong Time) To Free from ong ong Emai: ONit asia@ibbertco.com APAN: ON Semiconductor, apan Customer Focus Center 4 32 Nisi Gotanda, Sinagawa ku, Tokyo, apan Pone: Emai: r453@onsemi.com Fax Response ine: To Free USA/Canada ON Semiconductor Website: For additiona information, pease contact your oca Saes Representative. 4 SN74S76A/D
5 Tis dataseet as been downoaded from: Dataseets for eectronic components.
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Octal -Type atch with 3-State Output The MC74CT373A is an advanced high speed CMOS octal latch with 3 state output fabricated with silicon gate CMOS technology. It achieves high speed operation similar
The MC10107 is a triple 2 input exclusive OR/NOR gate. P D = 40 mw typ/gate (No Load) t pd = 2.8 ns typ t r, t f = 2.
The MC10107 is a triple input exclusive OR/NOR gate. P D = 0 mw typ/gate (No Load) t pd =. ns typ t r, t f =. ns typ (0% 0%) LOGIC DIAGRAM MARKING DIAGRAMS CDIP 16 L SUFFIX CASE 60 16 1 MC10107L AWLYYWW
MARKING DIAGRAMS ORDERING INFORMATION VHC139 AWLYYWW SOIC 16 D SUFFIX CASE 751B VHC 139 AWLYWW TSSOP 16 DT SUFFIX CASE 948F
The MC74HC139 is an advanced high speed CMOS 2 to 4 decoder/ demultiplexer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while
High Performance Silicon Gate CMOS
High Performance Silicon Gate CMOS The MC74HCT14A may be used as a level converter for interfacing TTL or NMOS outputs to high speed CMOS inputs. The HCT14A is identical in pinout to the LS14. The HCT14A
MARKING DIAGRAMS LOGIC DIAGRAM DIP PIN ASSIGNMENT TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620 MC10161L AWLYYWW
The MC10161 is designed to decode a three bit input word to a one of eight line output. The selected output will be low while all other outputs will be high. The enable inputs, when either or both are
MC14175B. MARKING DIAGRAMS. MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.) ORDERING INFORMATION PDIP 16 P SUFFIX CASE 648
The MC14175B quad type D flip flop is cotructed with MOS P channel and N channel enhancement mode devices in a single monolithic structure. Each of the four flip flops is positive edge triggered by a common
MARKING DIAGRAMS LOGIC DIAGRAM DIP PIN ASSIGNMENT ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620 MC10138L AWLYYWW
The MC101 is a four bit counter capable of divide by two, five, or ten functions. It is composed of four set reset master slave flip flops. Clock inputs trigger on the positive going edge of the clock
SN74LS373, SN74LS374. Octal Transparent Latch with 3 State Outputs; Octal D Type Flip Flop with 3 State Output LOW POWER SCHOTTKY
Octal Transparent Latch with 3 State Outputs; Octal Type Flip Flop with 3 State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops
MARKING DIAGRAMS ORDERING INFORMATION Figure 1. Pin Assignment VHCT139A AWLYYWW SOIC 16 D SUFFIX CASE 751B VHCT139A AWLYWW
The MC74HCT139A is an advanced high speed CMOS 2 to 4 decoder/ demultiplexer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL devices
MC74AC00, MC74ACT00. Quad 2 Input NAND Gate. High Performance Silicon Gate CMOS
Quad 2Input NAND Gate ighperformance SiliconGate CMOS Features Output Drive Capability: 24 ma Operating oltage Range: 2 to 6 AC00; to ACT00 ow Input Current:.0 A igh Noise Immunity Characteristic of CMOS
MC74AC138, MC74ACT of 8 Decoder/Demultiplexer
1 of 8 Decoder/Demultiplexer The MC74AC138/74ACT138 is a high speed 1 of 8 decoder/demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple
MC74AC132, MC74ACT132. Quad 2 Input NAND Schmitt Trigger
MC74AC32, MC74ACT32 Quad 2 Input NAND Schmitt Trigger The MC74AC/74ACT32 contains four 2 input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter free
74LVC373A. Low-Voltage CMOS Octal Transparent Latch. With 5 V Tolerant Inputs and Outputs (3 State, Non Inverting)
74VC373A ow-voltage CMOS Octal Traparent atch With 5 V Tolerant Inputs and Outputs (3 State, Non Inverting) The 74VC373A is a high performance, non inverting octal traparent latch operating from a 1.2
MC74LCX573. Low-Voltage CMOS Octal Transparent Latch Flow Through Pinout. With 5 V Tolerant Inputs and Outputs (3 State, Non Inverting)
ow-oltage CMOS Octal Traparent atch Flow Through Pinout With 5 Tolerant Inputs and Outputs (3 State, Non Inverting) The is a high performance, non inverting octal traparent latch operating from a 2.3 to
MC Bit Magnitude Comparator
Bit Magnitude Comparator The MC0 is a high speed expandable bit comparator for comparing the magnitude of two binary words. Two outputs are provided: and. A = B can be obtained by NORing the two outputs
MC74AC109, MC74ACT109. Dual JK Positive Edge Triggered Flip Flop
MC9, MC9 Dual JK Positive EdgeTriggered FlipFlop The MC9/9 coists of two highspeed completely independent traition clocked JK flipflops. The clocking operation is independent of rise and fall times of
NTB5426N, NTP5426N, NVB5426N. Power MOSFET 120 Amps, 60 Volts N-Channel D 2 PAK, TO-220
NTB56N, NTP56N, NVB56N Power OSET Amps, 6 Volts N-Channel D PAK, TO- eatures ow R DS(on) High Current Capability Avalanche Energy Specified AEC Q Qualified NVB56N These Devices are Pb ree and are RoHS
MARKING DIAGRAMS DIP PIN ASSIGNMENT ORDERING INFORMATION FUNCTION TABLE CDIP 16 L SUFFIX CASE 620 MC10136L AWLYYWW
The MC16 is a high speed synchronous counter that can count up, count down, preset, or stop count at frequencies exceeding 1 MHz. The flexibility of this device allows the designer to use one basic counter
V N (8) V N (7) V N (6) GND (5)
4-Channel Low Capacitance Dual-Voltage ESD Protection Array Features Three Channels of Low Voltage ESD Protection One Channel of High Voltage ESD Protection Provides ESD Protection to IEC61000 4 2 Level
MC74AC259, MC74ACT Bit Addressable Latch
8 Bit Addressable Latch The MC74AC259/74ACT259 is a high speed 8 bit addressable latch designed for general purpose storage applicatio in digital systems. It is a multifunctional device capable of storing
SN54/74LS147 SN54/74LS148 SN54/74LS LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS
10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The SN54/ 74LS147 and the SN54/ 74LS148 are Priority Encoders. They provide priority decoding of the inputs to eure that only the highest order
74AC00, 74ACT00 Quad 2-Input NAND Gate
74AC00, 74ACT00 Quad 2-Input NAND Gate Features I CC reduced by 50% Outputs source/sink 24mA ACT00 has TTL-compatible inputs Ordering Information Order Number Package Number General Description The AC00/ACT00
NLX1G99. Configurable Multifunction Gate
NX1G99 Configurable Multifunction Gate The NX1G99 MiniGate is an advanced high speed CMOS multifunction gate with a 3 state output. With the output enable input () at igh, the output is disabled and is
NCV8445. Self Protected High Side Driver with Temperature Shutdown and Current Limit
Self Protected igh Side Driver with Shutdown and Current imit The NCV844 is a fully protected igh Side driver that can be used to switch a wide variety of loads, such as bulbs, solenoids and other acuators.