SN74LS259MEL. 8 Bit Addressable Latch LOW POWER SCHOTTKY

Transcription

1 8 Bit Addressable atch The SN74S259 is a high-speed 8-Bit Addressable atch designed for general purpose storage applicatio in digital systems. It is a multifunctional device capable of storing single line data in eight addressable latches, and also a 1-of-8 decoder and demultiplexer with active IG outputs. The device also incorporates an active OW common Clear for resetting all latches, as well as, an active OW nable. Serial-to-Parallel Conversion ight Bits of Storage With Output of ach Bit Available Random (Addressable) ata ntry Active igh emultiplexing or ecoding Capability asily xpandable Common Clear GUARANT OPRATING RANGS Symbol Parameter Min Typ Max Unit V CC Supply Voltage V T A Operating Ambient Temperature Range C 16 OW POWR SCOTTKY 1 PASTIC N SUFFIX CAS 648 I O Output Current igh 0.4 ma I O Output Current ow 8.0 ma 16 1 SOIC SUFFIX CAS 751B 16 1 SOIAJ M SUFFIX CAS 966 ORRING INFORMATION evice Package Shipping SN74S259N 16 Pin IP 2000 Units/Box SN74S259 SOIC Units/Rail SN74S259R2 SOIC /Tape & Reel SN74S259M SOIAJ 16 See Note 1 SN74S259M SOIAJ 16 See Note 1 1. For ordering information on the IAJ version of the SOIC package, please contact your local ON Semiconductor representative. Semiconductor Components Industries, C, 2006 July, 2006 Rev. 8 1 Publication Order Number: SN74S259/

2 CONNCTION IAGRAM IP (TOP VIW) V CC C Q 7 Q 6 Q 5 Q A o A 1 A 2 Q 0 Q 1 Q 2 Q 3 GN OAING (Note a) PIN NAMS IG OW A 0, A 1, A 2 C Q 0 Q 7 Address Inputs ata Input nable (Active OW) Input Clear (Active OW) Input Parallel atch Outputs 0.5 U U U U.. 10 U U U U U.. 5 U.. NOTS: Мa) 1 TT Unit oad (U..) = 40 A IG/1.6 ma OW. 2

3 OGIC IAGRAM A 0 A 1 A 2 C V CC = PIN 16 GN = PIN 8 = PIN NUMBRS Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 FUNCTIONA SCRIPTION The SN74S259 has four modes of operation as shown in the mode selection table. In the addressable latch mode, data on the ata line () is written into the addressed latch.the addressed latch will follow the data input with all non-addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous state and are unaffected by the ata or Address inputs. In the one-of-eight decoding or demultiplexing mode, the addressed output will follow the state of the input with all other inputs in the OW state. In the clear mode all outputs are OW and unaffected by the address and data inputs. When operating the SN74S259 as an addressable latch, changing more then one bit of the address could impose a traient wrong address. Therefore, this should only be done while in the memory mode. The truth table below summarizes the operatio. C MO MO SCTION Addressable atch Memory Active IG ight-channel emultiplexer Clear X = on t Care Condition = OW Voltage evel = IG Voltage evel Q N 1 = Previous Output State TRUT TAB PRSNT OUTPUT STATS C A 0 A 1 A 2 Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 MO X X X X Clear emultiplex X X X X Q N 1 Memory I I Q N 1 Q N 1 Q N 1 Addressable Q N 1 Q N 1 atch Q N 1 Q N 1 Q N 1 Q N 1 Q N 1 Q N 1 Q N 1 Q N 1 3

4 C CARACTRISTICS OVR OPRATING TMPRATUR RANG (unless otherwise specified) Symbol Parameter imits Min Typ Max V I Input IG Voltage 2.0 V Unit Test Conditio Guaranteed Input IG Voltage for All Inputs V I Input OW Voltage 0.8 V Guaranteed Input OW Voltage for All Inputs V IK Input Clamp iode Voltage V V CC = MIN, I IN = 18 ma V O Output IG Voltage V V CC = MIN, I O = MAX, V IN = V I or V I per Truth Table V O I I Output OW Voltage Input IG Current V I O = 4.0 ma V CC = V CC MIN, V IN = V I or V I V I O = 8.0 ma per Truth Table 20 μa V CC = MAX, V IN = 2.7 V 0.1 ma V CC = MAX, V IN = 7.0 V I I Input OW Current 0.4 ma V CC = MAX, V IN = 0.4 V I OS Short Circuit Current (Note 2) ma V CC = MAX I CC Power Supply Current 36 ma V CC = MAX 2. Not more than one output should be shorted at a time, nor for more than 1 second. AC CARACTRISTICS (T A = 25 C, V CC = 5.0 V) imits Symbol Parameter Min Typ Max Unit Test Conditio t P Turn-Off elay, nable to Output Turn-On elay, nable to Output t P t P Turn-Off elay, ata to Output Turn-On elay, ata to Output Turn-Off elay, Address to Output Turn-On elay, Address to Output C = 15 pf Turn-On elay, Clear to Output AC ST-UP RQUIRMNTS (T A = 25 C, V CC = 5.0 V) imits Symbol Parameter Min Typ Max Unit t s Input Setup Time 20 t W Pulse Width, Clear or nable 15 t h old Time, ata 5.0 t h old Time, Address 20 4

5 AC WAVFORMS t w t w t P Q t P Q OTR CONITIONS: =, C =, A = STAB OTR CONITIONS: C =, A = STAB Figure 2. Turn-on and Turn-off elays, ata to Output Figure 1. Turn-on and Turn-off elays, nable To Output and nable Pulse Width A 1 A 1 t s () t h () t s () t h () t P Q 1 Q Q= Q= OTR CONITIONS: =, C =, = OTR CONITIONS: C =, A = STAB Figure 3. Turn-on and Turn-off elays, Address to Output Figure 4. Setup and old Time, ata to nable C A STAB ARSS t s Q OTR CONITIONS: = Figure 5. Turn-on elay, Clear to Output OTR CONITIONS: C = Figure 6. Setup Time, Address to nable (See Notes 1 and 2) NOTS: 1. The Address to nable Setup Time is the time before the IG-to-OW nable traition that the Address must be stable so that the correct latch is addressed and the other latches are not affected. 2. The shaded areas indicate when the inputs are permitted to change for predictable output performance. 5

6 PACKAG IMNSIONS N SUFFIX PASTIC PACKAG CAS ISSU R 16 A 1 8 G F 9 16 P B S C K 0.25 (0.010) M T SATING T PAN A M J M NOTS: 1. IMNSIONING AN TORANCING PR ANSI Y14.5M, CONTROING IMNSION: INC. 3. IMNSION TO CNTR OF AS WN FORM PARA. 4. IMNSION B OS NOT INCU MO FAS. 5. ROUN CORNRS OPTIONA. INCS MIIMTRS IM MIN MAX MIN MAX A B C F G BSC 2.54 BSC BSC 1.27 BSC J K M S

7 PACKAG IMNSIONS SUFFIX PASTIC SOIC PACKAG CAS 751B 05 ISSU J T SATING PAN G A K B 16 P 0.25 (0.010) M T B S A S P 8 P 0.25 (0.010) M B S C M R X 45 J F NOTS: 1. IMNSIONING AN TORANCING PR ANSI Y14.5M, CONTROING IMNSION: MIIMTR. 3. IMNSIONS A AN B O NOT INCU MO PROTRUSION. 4. MAXIMUM MO PROTRUSION 0.15 (0.006) PR SI. 5. IMNSION OS NOT INCU AMBAR PROTRUSION. AOWAB AMBAR PROTRUSION SA B (0.005) TOTA IN XCSS OF T IMNSION AT MAXIMUM MATRIA CONITION. MIIMTRS INCS IM MIN MAX MIN MAX A B C F G 1.27 BSC BSC J K M P R

8 PACKAG IMNSIONS M SUFFIX SOIAJ PACKAG CAS ISSU O e Z b A A (0.005) M 0.10 (0.004) 8 VIW P M Q 1 TAI P c NOTS: 1. IMNSIONING AN TORANCING PR ANSI Y14.5M, CONTROING IMNSION: MIIMTR. 3. IMNSIONS AN O NOT INCU MO FAS OR PROTRUSIONS AN AR MASUR AT T PARTING IN. MO FAS OR PROTRUSIONS SA NOT XC 0.15 (0.006) PR SI. 4. TRMINA NUMBRS AR SOWN FOR RFRNC ONY. 5. T A WIT IMNSION (b) OS NOT INCU AMBAR PROTRUSION. AOWAB AMBAR PROTRUSION SA B 0.08 (0.003) TOTA IN XCSS OF T A WIT IMNSION AT MAXIMUM MATRIA CONITION. AMBAR CANNOT B OCAT ON T OWR RAIUS OR T FOOT. MINIMUM SPAC BTWN PROTRUSIONS AN AJACNT A TO B 0.46 ( 0.018). MIIMTRS INCS IM MIN MAX MIN MAX A A b c e 1.27 BSC BSC M Q Z ON Semiconductor and are registered trademarks of Semiconductor Components Industries, C (SCIC). SCIC reserves the right to make changes without further notice to any products herein. SCIC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCIC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SCIC data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCIC does not convey any licee under its patent rights nor the rights of others. SCIC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SCIC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCIC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCIC and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCIC was negligent regarding the design or manufacture of the part. SCIC is an qual Opportunity/Affirmative Action mployer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBICATION ORRING INFORMATION ITRATUR FUFIMNT: iterature istribution Center for ON Semiconductor P.O. Box 5163, enver, Colorado USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada mail: orderlit@oemi.com N. American Technical Support: Toll Free USA/Canada urope, Middle ast and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order iterature: For additional information, please contact your local Sales Representative SN74S259/