MC74VHCT373A. Octal D-Type Latch with 3-State Output

Transcription

1 Octal -Type atch with 3-State Output The MC74CT373A is an advanced high speed CMOS octal latch with 3 state output fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. This 8 bit type latch is controlled by a latch enable input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The CT inputs are compatible with TT levels. This device can be used as a level converter for interfacing 3.3 to 5.0, because it has full 5.0 CMOS level output swings. The CT373A input and output (when disabled) structures provide protection when voltages between 0 and 5.5 are applied, regardless of the supply voltage. These input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot insertion, etc. Features igh Speed: t P = 7.7 ns (Typ) at CC = 5.0 ow Power issipation: I CC = 4 A (Max) at T A = 5 C TT Compatible Inputs: I = 0.8 ; I =.0 Power own Protection Provided on Inputs and Outputs Balanced Propagation elays esigned for 4.5 to 5.5 Operating Range ow Noise: OP =.6 (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300 ma ES Performance: uman Body Model > 00 ; Machine Model > 0 Chip Complexity: 96 FETs or 49 Equivalent Gates These evices are Pb Free and are RoS Compliant SOIC WB SUFFIX W CASE 75 TSSOP SUFFIX T CASE 948E MARKING IAGRAMS CT373A AWYYWWG CT 373A AYW A = Assembly ocation W, = Wafer ot YY, Y = Year WW, W = Work Week G or = Pb Free Package (Note: Microdot may be in either location) FUNCTION TAB INPUTS OUTPUT OE X X X No Change Z ORERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. Semiconductor Components Industries, C, May, Rev. 5 Publication Order Number: MC74CT373A/

2 ATA INPUTS OE NONINERTING OUTPUTS OE GN CC Figure. ogic iagram Figure. Pin Assignment MAXIMUM RATINGS SymbolÎÎ Parameter Î alue Unit CC ÎÎ C Supply oltage Î 0.5 to in ÎÎ C Input oltage Î 0.5 to + out ÎÎ C Output oltage Outputs in 3 State Î 0.5 to Î igh or ow State Î 0.5 to CC I IK ÎÎ Input iode Current Î ma I OK ÎÎ Output iode Current ( OUT < GN; OUT > CC ) Î ± ma I out ÎÎ C Output Current, per Pin Î ± 5 ma I CC ÎÎ C Supply Current, CC and GN Pins Î ± 75 ma P ÎÎ Power issipation in Still Air, SOIC Packages Î 500 mw TSSOP Package 450 T stg Storage Temperature 65 to + 50 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. erating SOIC Packages: 7 mw/ C from 65 to 5 C TSSOP Package: 6. mw/ C from 65 to 5 C C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. owever, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be constrained to the range GN ( in or out ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GN or CC ). Unused outputs must be left open. RECOMMENE OPERATING CONITIONS Symbol Parameter Min Max ÎÎ Unit CC C Supply oltage ÎÎ in C Input oltage ÎÎ out C Output oltage Outputs in 3 State ÎÎ igh or ow State 0 Î CC T A Operating Temperature 40 ÎÎ + 85 C Î Input Rise and Fall Time CC =5.0 ±0.5 0 Î ns/ t r, t f

3 Î C ECTRICA CARACTERISTICS Î CC T A = 5 C ÎÎ T A = 40 to 85 C ÎÎ SymbolÎ Parameter Test Conditions Min Typ Max Min Max ÎÎ Unit I Î Minimum igh evel Input ÎÎ 4.5 to Î oltage ÎÎ I Maximum ow evel Input Î oltage 4.5 to ÎÎ 0.8 ÎÎ O Minimum igh evel Output I O Î = 50 A Î oltage in = I or I I O Î = 8mA Î O Maximum ow evel Output I O ÎÎ = 50 A oltage in = I or I I O Î = 8mA I in Maximum Input eakage in ÎÎ = 5.5 or GN 0 to 5.5 ± 0. ±.0 Current ÎÎ A I OZ Î Maximum 3 State eakage in = I or I 5.5 ± 0.5ÎÎ ±.5 ÎÎ A Current ÎÎ out = CC or GN I CC Î Maximum uiescent Supply in = CC or GN A Current I CCT uiescent Supply Current Per Input: IN ÎÎ = ÎÎ Other Input: CC or GN ma Output eakage Current OUT = ÎÎ 5.0 ÎÎ A I OP AC ECTRICA CARACTERISTICS (Input t r = t f = 3.0ns) Î T Î A = 5 C T A = 40 to 85 C Symbol Parameter Test Conditions Min Typ Max Min Max Unit Î t P, Maximum Propagation elay, t P ÎÎ to Î CC = 5.0 ± 0.5 C = 5pF C = 50pF ÎÎ ns t P, ÎÎ Maximum Propagation elay, Î CC = 5.0 ± 0.5 C = 5pF ÎÎ t P ÎÎ to Î C = 50pF ÎÎ 0.5 ÎÎ ns t PZ, ÎÎ Output Enable Time, Î CC = 5.0 ± 0.5 C = 5pF Î ÎÎ ns t PZ OE to R = k C = 50pF Î t PZ, Output isable Time, t PZ ÎÎ CC = 5.0 ± 0.5 C = 50pF 8.8. OE to R.0.0 Î ns = k t OS ÎÎ, Output to Output Skew CC = 5.5 ± 0.5 C = 50pF t OS ÎÎ (Note ).0 ÎÎ.0 ns ÎÎ C in ÎÎ Maximum Input Capacitance Î 4 0 ÎÎ 0 ÎÎ pf C out ÎÎ Maximum Three State Output Î 6 pf Capacitance (Output in Î igh Impedance State) 5 C, CC = 5.0 C P Power issipation Capacitance (Note ) 5 pf. Parameter guaranteed by design. t OS = t Pm t Pn, t OS = t Pm t Pn.. C P is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I CC(OPR) = C P CC f in + I CC / 8 (per latch). C P is used to determine the no load dynamic power consumption; P = C P CC f in + I CC CC. 3

4 NOISE CARACTERISTICS (Input t r = t f = 3.0ns, C = 50 pf, CC = 5.0) T A = 5 C Symbol Parameter Typ Max Unit OP uiet Output Maximum ynamic O..6 O uiet Output Minimum ynamic O..6 I Minimum igh evel ynamic Input oltage.0 I Maximum ow evel ynamic Input oltage 0.8 TIMING REUIREMENTS (Input t r = t f = 3.0ns) T A = 5 C T A = 40 to 85 C Symbol Parameter Test Conditions Typ imit imit Unit t w(h) Minimum Pulse Width, CC = 5.0 ± ns t su Minimum Setup Time, to CC = 5.0 ± ns t h Minimum old Time, to CC = 5.0 ± ns ORERING INFORMATION MC74CT373AWRG evice Package Shipping SOIC WB (Pb Free) 000 / Tape & Reel MC74CT373ATRG TSSOP * 500 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BR80/. *This package is inherently Pb Free. t P.5 t P GN t w.5 t P t P GN.5 O O.5 O O Figure 3. Switching Waveform Figure 4. Switching Waveform OE.5 t PZ.5 t PZ.5 t PZ t PZ GN IG IMPEANCE O +0. O -0. IG IMPEANCE.5 t su AI t h.5 GN GN Figure 5. Switching Waveform Figure 6. Switching Waveform 4

5 TEST POINT EICE UNER TEST OUTPUT C * *Includes all probe and jig capacitance Figure 7. Test Circuit TEST POINT EICE UNER TEST OUTPUT k C * CONNECT TO CC WEN TESTING t PZ AN t PZ. CONNECT TO GN WEN TESTING t PZ AN t PZ. *Includes all probe and jig capacitance Figure 8. Test Circuit OE Figure 9. Expanded ogic iagram 5

6 PACKAGE IMENSIONS TSSOP CASE 948E 0 ISSUE C 0.5 (0.006) T 0.5 (0.006) T U X / PIN IENT U S S C 0.00 (0.004) T SEATING PANE X K REF 0.0 (0.004) M T U S S 0 A G B U J J K K ÍÍÍÍ ÍÍÍÍ SECTION N N N 0.5 (0.00) M N F ETAI E ETAI E NOTES:. IMENSIONING AN TORANCING PER ANSI Y4.5M, 98.. CONTROING IMENSION: MIIMETER. 3. IMENSION A OES NOT INCUE MO FAS, PROTRUSIONS OR GATE BURRS. MO FAS OR GATE BURRS SA NOT EXCEE 0.5 (0.006) PER SIE. 4. IMENSION B OES NOT INCUE INTERA FAS OR PROTRUSION. INTERA FAS OR PROTRUSION SA NOT EXCEE 0.5 (0.00) PER SIE. 5. IMENSION K OES NOT INCUE AMBAR PROTRUSION. AOWAB AMBAR PROTRUSION SA BE 0.08 (0.003) TOTA IN EXCESS OF TE K IMENSION AT MAXIMUM MATERIA CONITION. 6. TERMINA NUMBERS ARE SOWN FOR REFERENCE ONY. 7. IMENSION A AN B ARE TO BE ETERMINE AT ATUM PANE W. MIIMETERS INCES IM MIN MAX MIN MAX A B C F G 0.65 BSC 0.06 BSC W J J K K BSC 0.5 BSC M SOERING FOOTPRINT PITC 6X X.6 IMENSIONS: MIIMETERS 6

7 PACKAGE IMENSIONS SOIC WB W SUFFIX CASE ISSUE G 0X 0.5 M B M E A h X 45 NOTES:. IMENSIONS ARE IN MIIMETERS.. INTERPRET IMENSIONS AN TORANCES PER ASME Y4.5M, IMENSIONS AN E O NOT INCUE MO PROTRUSION. 4. MAXIMUM MO PROTRUSION 0.5 PER SIE. 5. IMENSION B OES NOT INCUE AMBAR PROTRUSION. AOWAB PROTRUSION SA BE 0.3 TOTA IN EXCESS OF B IMENSION AT MAXIMUM MATERIA CONITION. X B 0.5 M T A S 8X e 0 B B S A A T SEATING PANE C MIIMETERS IM MIN MAX A A B C E e.7 BSC h ON Semiconductor and are registered trademarks of Semiconductor Components Industries, C (SCIC). SCIC reserves the right to make changes without further notice to any products herein. SCIC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCIC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCIC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCIC does not convey any license under its patent rights nor the rights of others. SCIC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCIC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCIC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCIC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCIC was negligent regarding the design or manufacture of the part. SCIC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBICATION ORERING INFORMATION ITERATURE FUFIMENT: iterature istribution Center for ON Semiconductor P.O. Box 563, enver, Colorado 807 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order iterature: For additional information, please contact your local Sales Representative MC74CT373A/