MC74VHC574. Octal D Type Flip Flop with 3 State Output. ON Semiconductor

Transcription

1 ON Semiconductor Octal Type Flip Flop with 3 State Output The M74H574 is an advanced high speed MOS octal flip flip with 3 state output fabricated with silicon gate MOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining MOS low power dissipation. This 8 bit type flip flop is controlled by a clock input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7, allowing the interface of 5 systems to 3 systems. High Speed: f max = 180MHz (Typ) at = 5 ow Power issipation: I = 4μA (Max) at T A = 25 High Noise Immunity: NIH = NI = 28% Power own Protection Provided on Inputs Balanced Propagation elays esigned for 2 to 5.5 Operating Range ow Noise: OP = 1.2 (Max) Pin and Function ompatible with Other Standard ogic Families atchup Performance Exceeds 300mA ES Performance: HBM > 2000; Machine Model > 200 hip omplexity: 266 FETs or 66.5 Equivalent Gates These devices are available in Pb free package(s). Specifications herein apply to both standard and Pb free devices. Please see our website at for specific Pb free orderable part numbers, or contact your local ON Semiconductor sales office or representative. M74H574 W SUFFIX 20 EA SOI WIE PAKAGE ASE T SUFFIX 20 EA TSSOP PAKAGE ASE 948E 02 M SUFFIX 20 EA SOI EIAJ PAKAGE ASE ORERING INFORMATION M74HXXXW M74HXXXT M74HXXXM SOI WIE TSSOP SOI EIAJ Semiconductor omponents Industries,, 2006 March, 2006 Rev. 5 1 Publication Order Number: M74H574/

2 ATA INPUTS P NONINERTING OUTPUTS OE OE 1 GN 10 P Figure 1. OGI IAGRAM Figure 2. PIN ASSIGNMENT FUNTION TABE INPUTS OUTPUT OE P H, H, X H X X H No hange Z 2

3 Î MAXIMUM RATINGS* Symbol Parameter Î alue Î Unit Supply oltage Î 0.5 to + 7.0Î in Input oltage Î 0.5 to + 7.0Î out Output oltage Î 0.5 to + 0.5Î I IK Input iode urrent Î 20 Î ma I OK Output iode urrent Î ± 20 Î ma I out Output urrent, per Pin Î ± 25 Î ma I Supply urrent, and GN Pins Î ± 75 Î ma P Power issipation in Still Air, SOI Packages Î 500 Î mw TSSOP Package 450 Î T stg Storage Temperature 65 to Î * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. erating SOI Packages: 7 mw/ from 65 to 125 TSSOP Package: 6.1 mw/ from 65 to 125 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be constrained to the range GN ( in or out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GN or ). Unused outputs must be left open. REOMMENE OPERATING ONITIONS SymbolÎ Parameter Min Max Î Unit Î Supply oltage Î in Î Input oltage Î out Î Output oltage 0 Î T A Î Operating Temperature Î t r, t f Î Input Rise and Fall Time = 3.3 = Î ns/ EETRIA HARATERISTIS Î T A = 25 T A = 40 to 85 Symbol Parameter Test onditions Min Typ Max Min Max Unit Î IH Minimum High evel Î Input oltage Î 3.0 to x 0.7Î x 0.7Î 5.5 I Î Maximum ow evel Î Input oltage Î to Î 5.5 Î Î 0.50 x x 0.3 OH Î Minimum High evel Î in = IH or I Output oltage Î I OH = 50μA Î Î Î in = IH or I I OH = 4mA I OH = 8mAÎ Î Î 3.80 Î O Î Maximum ow evel Î in = IH or I Î 2.0 Output oltage I O = 50μA 3.0 Î 4.5 Î Î in = IH or I I O = 4mAÎ 3.0 Î I O = 8mA

4 Î EETRIA HARATERISTIS T A = 25 Î T A = 40 to 85 Symbol Î Parameter Î Test onditions Î Min Î Typ Max Min Max Unit I in Î Maximum Input Î in = 5.5 or GN Î 0 to 5.5Î ± 0.1 ± 1.0 eakage urrent Î μa I OZ Î Maximum Î in = I or IH Three State eakage out = Î 5.5 or GN urrent Î ± 0.25 Î ± 2.5 μa I Î Maximum uiescent Î in = or GN Î 5.5 Supply urrent Î Î Î Î μa Î A EETRIA HARATERISTIS (Input t r = t f = 3.0ns) Î T A = 25 T A = 40 to 85 Î Symbol Parameter Test onditions Min Typ Max Min Max Unit f max Maximum lock Frequency = 3.3 ± 0.3 Î = 15pF 80 (50% uty ycle) = 50pF 50 Î Î 65 ns 45 Î = 5.0 ± 0.5 = 15pF 130 Î Î = 50pF Î Î t PH, Maximum Propagation elay, t PH = 3.3 ± 0.3 = 15pF P to = 50pF Î Î ns = 5.0 ± 0.5 = 15pF Î = 50pF Î Î t PZ, Î Output Enable Time, = 3.3 ± 0.3 = 15pF t PZH OE to R = 1kΩ = 50pF ns Î Î = 5.0 ± 0.5 = 15pF R = 1kΩ = 50pF Î Î t PZ, Output isable Time, t PHZ Î OE to = 3.3 ± 0.3 = 50pF R = 1kΩ Î Î.0 Î 15.0 Î ns Î Î = 5.0 ± 0.5 = 50pF Î R = 1kΩ Î t OSH, Î Output to Output Skew = 3.3 ± 0.3 = 50pF t OSH (Note 1) Î 1.5 Î 1.5 ns Î Î = 5.0 ± 0.5 = 50pF (Note 1) Î Î Î Î ns in Î Maximum Input apacitance Î Î 4 10 Î 10 pf out Î Maximum Three State Output apacitance, Output in 6 Î pf High Impedance State 25, = 5.0 P Power issipation apacitance (Note 2) 28 pf 1. Parameter guaranteed by design. t OSH = t PHm t PHn, t OSH = t PHm t PHn. 2. P is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I (OPR) = P f in + I / 8 (per flip flop). P is used to determine the no load dynamic power consumption; P = P 2 f in + I. 4

5 NOISE HARATERISTIS (Input t r = t f = 3.0ns, = 50pF, = 5.0) T A = 25 Symbol Parameter Typ Max Unit OP uiet Output Maximum ynamic O O uiet Output Minimum ynamic O IH Minimum High evel ynamic Input oltage 3.5 I Maximum ow evel ynamic Input oltage 1.5 TIMING REUIREMENTS (Input t r = t f = 3.0ns) Symbol Parameter Test onditions t su Minimum Setup Time, to P = 3.3 ± 0.3 = 5.0 ± 0.5 T A = 25 T A = 40 to 85 Typ imit imit Unit ns t h Minimum Hold Time, P to = 3.3 ± 0.3 = 5.0 ± ns t w Minimum Pulse Width, P = 3.3 ± 0.3 = 5.0 ± ns P 50% t w 1/fmax t PH 50% t PH GN OE 50% t PZ 50% t PZH 50% t PZ t PHZ GN HIGH IMPEANE O +0.3 OH 0.3 HIGH IMPEANE Figure 3. Switching Waveforms AI TEST POINT P 50% t su 50% t h GN GN EIE UNER TEST OUTPUT * *Includes all probe and jig capacitance Figure 4. Figure 5. 5

6 P OE 1 Figure 6. Expanded ogic iagram TEST POINT EIE UNER TEST OUTPUT 1 kω * ONNET TO WHEN TESTING t PZ AN t PZ. ONNET TO GN WHEN TESTING t PHZ AN t PZH. INPUT *Includes all probe and jig capacitance Figure 7. Test ircuit Figure 8. INPUT EUIAENT IRUIT 6

7 OUTINE IMENSIONS W SUFFIX SOI ASE ISSUE F A H 10X 0.25 M B M E h X 45 NOTES: 1. IMENSIONS ARE IN MIIMETERS. 2. INTERPRET IMENSIONS AN TOERANES PER ASME Y14.5M, IMENSIONS AN E O NOT INUE MO PROTRUSION. 4. MAXIMUM MO PROTRUSION 0.15 PER SIE. 5. IMENSION B OES NOT INUE AMBAR PROTRUSION. AOWABE PROTRUSION SHA BE 0.13 TOTA IN EXESS OF B IMENSION AT MAXIMUM MATERIA ONITION. 20X B 0.25 M T A S 18X e B B S A A1 T SEATING PANE MIIMETERS IM MIN MAX A A B E e 1.27 BS H h T SUFFIX TSSOP ASE 948E 02 ISSUE A 0.15 (0.006) T 0.15 (0.006) T U 2X /2 PIN 1 IENT U S S (0.004) T SEATING PANE 20X K REF 0.10 (0.004) M T U S S 1 10 A G H B U J J1 N N K K1 ÍÍÍÍ ÍÍÍÍ SETION N N F ETAI E 0.25 (0.010) ETAI E M W NOTES: 1. IMENSIONING AN TOERANING PER ANSI Y14.5M, ONTROING IMENSION: MIIMETER. 3. IMENSION A OES NOT INUE MO FASH, PROTRUSIONS OR GATE BURRS. MO FASH OR GATE BURRS SHA NOT EXEE 0.15 (0.006) PER SIE. 4. IMENSION B OES NOT INUE INTEREA FASH OR PROTRUSION. INTEREA FASH OR PROTRUSION SHA NOT EXEE 0.25 (0.010) PER SIE. 5. IMENSION K OES NOT INUE AMBAR PROTRUSION. AOWABE AMBAR PROTRUSION SHA BE 0.08 (0.003) TOTA IN EXESS OF THE K IMENSION AT MAXIMUM MATERIA ONITION. 6. TERMINA NUMBERS ARE SHOWN FOR REFERENE ONY. 7. IMENSION A AN B ARE TO BE ETERMINE AT ATUM PANE W. MIIMETERS INHES IM MIN MAX MIN MAX A B F G 0.65 BS BS H J J K K BS BS M

8 OUTINE IMENSIONS M SUFFIX SOI EIAJ ASE ISSUE O e 20 E H E 1 10 Z A b A (0.005) M 0.10 (0.004) IEW P M E 1 ETAI P c NOTES: 1. IMENSIONING AN TOERANING PER ANSI Y14.5M, ONTROING IMENSION: MIIMETER. 3. IMENSIONS AN E O NOT INUE MO FASH OR PROTRUSIONS AN ARE MEASURE AT THE PARTING INE. MO FASH OR PROTRUSIONS SHA NOT EXEE 0.15 (0.006) PER SIE. 4. TERMINA NUMBERS ARE SHOWN FOR REFERENE ONY. 5. THE EA WITH IMENSION (b) OES NOT INUE AMBAR PROTRUSION. AOWABE AMBAR PROTRUSION SHA BE 0.08 (0.003) TOTA IN EXESS OF THE EA WITH IMENSION AT MAXIMUM MATERIA ONITION. AMBAR ANNOT BE OATE ON THE OWER RAIUS OR THE FOOT. MINIMUM SPAE BETWEEN PROTRUSIONS AN AJAENT EA TO BE 0.46 ( 0.018). MIIMETERS INHES IM MIN MAX MIN MAX A A b c E e 1.27 BS BS H E E M Z ON Semiconductor and are registered trademarks of Semiconductor omponents Industries, (SI). SI reserves the right to make changes without further notice to any products herein. SI makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SI assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SI data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SI does not convey any license under its patent rights nor the rights of others. SI products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SI product could create a situation where personal injury or death may occur. Should Buyer purchase or use SI products for any such unintended or unauthorized application, Buyer shall indemnify and hold SI and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SI was negligent regarding the design or manufacture of the part. SI is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBIATION ORERING INFORMATION ITERATURE FUFIMENT: iterature istribution enter for ON Semiconductor P.O. Box 61312, Phoenix, Arizona USA Phone: or Toll Free USA/anada Fax: or Toll Free USA/anada orderlit@onsemi.com N. American Technical Support: Toll Free USA/anada Japan: ON Semiconductor, Japan ustomer Focus enter Kamimeguro, Meguro ku, Tokyo, Japan Phone: ON Semiconductor Website: Order iterature: For additional information, please contact your local Sales Representative. M74H574/