The Register Set / C167
|
|
|
- Ashlynn Jennings
- 5 years ago
- Views:
Transcription
1 20 The Set This section summarizes all registers, which are implemented in the C167 and explains the description format which is used in the chapters describing the function and layout of the SFRs. For easy reference the registers are ordered according to two different keys (except for GPRs): Ordered by address, to check which register a given address references, Ordered by register name, to find the location of a specific register. Format In the respective chapters the function and the layout of the SFRs is described in a specific format which provides a number of details about the described special function register. The example below shows how to interpret these details. A word register looks like this: REG_NAME (A16 H / A8 H ) SFR/ESFR/XReg : * * * * H res. res. res. res. res. write only hw bit read only std bit hw bit bitfield bitfield w rw r rw rw rw rw Bit bit(field)name Function Explanation of bit(field)name of the functions controlled by this bit(field). A byte register looks like this: REG_NAME (A16 H / A8 H ) SFR/ESFR/XReg : - - * * H std bit hw bit bitfield bitfield rw rw rw rw Elements: REG_NAME of this register A16 / A8 Long 16-bit address / Short 8-bit address SFR/ESFR/XReg space (SFR, ESFR or External/XBUS ) (* *) * * contents after reset. 0/1: defined value, X : undefined, U unchanged (undefined ( X ) after power up). hwbit Bits that are set/cleared by hardware are marked with a shaded access box Semiconductor Group 20-1
2 20.1 CPU General Purpose s (GPRs) The GPRs form the register bank that the CPU works with. This register bank may be located anywhere within the internal RAM via the Context Pointer (CP). Due to the addressing mechanism, GPR banks can only reside within the internal RAM. All GPRs are bit-addressable. R0 (CP) + 0 F0 H CPU General Purpose (Word) R0 UUUU H R1 (CP) + 2 F1 H CPU General Purpose (Word) R1 UUUU H R2 (CP) + 4 F2 H CPU General Purpose (Word) R2 UUUU H R3 (CP) + 6 F3 H CPU General Purpose (Word) R3 UUUU H R4 (CP) + 8 F4 H CPU General Purpose (Word) R4 UUUU H R5 (CP) + 10 F5 H CPU General Purpose (Word) R5 UUUU H R6 (CP) + 12 F6 H CPU General Purpose (Word) R6 UUUU H R7 (CP) + 14 F7 H CPU General Purpose (Word) R7 UUUU H R8 (CP) + 16 F8 H CPU General Purpose (Word) R8 UUUU H R9 (CP) + 18 F9 H CPU General Purpose (Word) R9 UUUU H R10 (CP) + 20 FA H CPU General Purpose (Word) R10 UUUU H R11 (CP) + 22 FB H CPU General Purpose (Word) R11 UUUU H R12 (CP) + 24 FC H CPU General Purpose (Word) R12 UUUU H R13 (CP) + 26 FD H CPU General Purpose (Word) R13 UUUU H R14 (CP) + 28 FE H CPU General Purpose (Word) R14 UUUU H R15 (CP) + 30 FF H CPU General Purpose (Word) R15 UUUU H Semiconductor Group 20-2
3 The first 8 GPRs (R7...R0) may also be accessed bytewise. Other than with SFRs, writing to a GPR byte does not affect the other byte of the respective GPR. The respective halfs of the byte-accessible registers receive special names: RL0 (CP) + 0 F0 H CPU General Purpose (Byte) RL0 UU H RH0 (CP) + 1 F1 H CPU General Purpose (Byte) RH0 UU H RL1 (CP) + 2 F2 H CPU General Purpose (Byte) RL1 UU H RH1 (CP) + 3 F3 H CPU General Purpose (Byte) RH1 UU H RL2 (CP) + 4 F4 H CPU General Purpose (Byte) RL2 UU H RH2 (CP) + 5 F5 H CPU General Purpose (Byte) RH2 UU H RL3 (CP) + 6 F6 H CPU General Purpose (Byte) RL3 UU H RH3 (CP) + 7 F7 H CPU General Purpose (Byte) RH3 UU H RL4 (CP) + 8 F8 H CPU General Purpose (Byte) RL4 UU H RH4 (CP) + 9 F9 H CPU General Purpose (Byte) RH4 UU H RL5 (CP) + 10 FA H CPU General Purpose (Byte) RL5 UU H RH5 (CP) + 11 FB H CPU General Purpose (Byte) RH5 UU H RL6 (CP) + 12 FC H CPU General Purpose (Byte) RL6 UU H RH6 (CP) + 13 FD H CPU General Purpose (Byte) RH6 UU H RL7 (CP) + 14 FE H CPU General Purpose (Byte) RL7 UU H RH7 (CP) + 15 FF H CPU General Purpose (Byte) RH7 UU H Semiconductor Group 20-3
4 20.2 Special Function s ordered by The following table lists all SFRs which are implemented in the C167 in alphabetical order. Bit-addressable SFRs are marked with the letter b in column. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter E in column. s within on-chip X-Peripherals (CAN) are marked with the letter X in column. ADCIC b FF98 H CC H A/D Converter End of Conversion Interrupt Control ADCON b FFA0 H D0 H A/D Converter Control ADDAT FEA0 H 50 H A/D Converter Result ADDAT2 F0A0 H E 50 H A/D Converter 2 Result ADDRSEL1 FE18 H 0C H Select 1 ADDRSEL2 FE1A H 0D H Select 2 ADDRSEL3 FE1C H 0E H Select 3 ADDRSEL4 FE1E H 0F H Select 4 ADEIC b FF9A H CD H A/D Converter Overrun Error Interrupt Control BUSCON0 b FF0C H 86 H Bus Configuration 0 BUSCON1 b FF14 H 8A H Bus Configuration 1 BUSCON2 b FF16 H 8B H Bus Configuration 2 BUSCON3 b FF18 H 8C H Bus Configuration 3 BUSCON4 b FF1A H 8D H Bus Configuration 4 C1BTR EF04 H X --- CAN Bit Timing UUUU H C1CSR EF00 H X --- CAN Control / Status XX01 H C1GMS EF06 H X --- CAN Global Mask Short UFUU H C1IR EF02 H X --- CAN Interrupt XX H C1LGML EF0A H X --- CAN Lower Global Mask Long UUUU H C1LMLM EF0E H X --- CAN Lower Mask of Last Message UUUU H C1UGML EF08 H X --- CAN Upper Global Mask Long UUUU H C1UMLM EF0C H X --- CAN Upper Mask of Last Message UUUU H CAPREL FE4A H 25 H GPT2 Capture/Reload CC0 FE80 H 40 H CAPCOM 0 CC0IC b FF78 H BC H CAPCOM 0 Interrupt Control Semiconductor Group 20-4
5 CC1 FE82 H 41 H CAPCOM 1 CC1IC b FF7A H BD H CAPCOM 1 Interrupt Control CC2 FE84 H 42 H CAPCOM 2 CC2IC b FF7C H BE H CAPCOM 2 Interrupt Control CC3 FE86 H 43 H CAPCOM 3 CC3IC b FF7E H BF H CAPCOM 3 Interrupt Control CC4 FE88 H 44 H CAPCOM 4 CC4IC b FF80 H C0 H CAPCOM 4 Interrupt Control CC5 FE8A H 45 H CAPCOM 5 CC5IC b FF82 H C1 H CAPCOM 5 Interrupt Control CC6 FE8C H 46 H CAPCOM 6 CC6IC b FF84 H C2 H CAPCOM 6 Interrupt Control CC7 FE8E H 47 H CAPCOM 7 CC7IC b FF86 H C3 H CAPCOM 7 Interrupt Control CC8 FE90 H 48 H CAPCOM 8 CC8IC b FF88 H C4 H CAPCOM 8 Interrupt Control CC9 FE92 H 49 H CAPCOM 9 CC9IC b FF8A H C5 H CAPCOM 9 Interrupt Control CC10 FE94 H 4A H CAPCOM 10 CC10IC b FF8C H C6 H CAPCOM 10 Interrupt Control CC11 FE96 H 4B H CAPCOM 11 CC11IC b FF8E H C7 H CAPCOM 11 Interrupt Control CC12 FE98 H 4C H CAPCOM 12 CC12IC b FF90 H C8 H CAPCOM 12 Interrupt Control CC13 FE9A H 4D H CAPCOM 13 CC13IC b FF92 H C9 H CAPCOM 13 Interrupt Control CC14 FE9C H 4E H CAPCOM 14 CC14IC b FF94 H CA H CAPCOM 14 Interrupt Control CC15 FE9E H 4F H CAPCOM 15 CC15IC b FF96 H CB H CAPCOM 15 Interrupt Control CC16 FE60 H 30 H CAPCOM 16 CC16IC b F160 H E B0 H CAPCOM 16 Interrupt Control CC17 FE62 H 31 H CAPCOM 17 Semiconductor Group 20-5
6 CC17IC b F162 H E B1 H CAPCOM 17 Interrupt Control CC18 FE64 H 32 H CAPCOM 18 CC18IC b F164 H E B2 H CAPCOM 18 Interrupt Control CC19 FE66 H 33 H CAPCOM 19 CC19IC b F166 H E B3 H CAPCOM 19 Interrupt Control CC20 FE68 H 34 H CAPCOM 20 CC20IC b F168 H E B4 H CAPCOM 20 Interrupt Control CC21 FE6A H 35 H CAPCOM 21 CC21IC b F16A H E B5 H CAPCOM 21 Interrupt Control CC22 FE6C H 36 H CAPCOM 22 CC22IC b F16C H E B6 H CAPCOM 22 Interrupt Control CC23 FE6E H 37 H CAPCOM 23 CC23IC b F16E H E B7 H CAPCOM 23 Interrupt Control CC24 FE70 H 38 H CAPCOM 24 CC24IC b F170 H E B8 H CAPCOM 24 Interrupt Control CC25 FE72 H 39 H CAPCOM 25 CC25IC b F172 H E B9 H CAPCOM 25 Interrupt Control CC26 FE74 H 3A H CAPCOM 26 CC26IC b F174 H E BA H CAPCOM 26 Interrupt Control CC27 FE76 H 3B H CAPCOM 27 CC27IC b F176 H E BB H CAPCOM 27 Interrupt Control CC28 FE78 H 3C H CAPCOM 28 CC28IC b F178 H E BC H CAPCOM 28 Interrupt Control CC29 FE7A H 3D H CAPCOM 29 CC29IC b F184 H E C2 H CAPCOM 29 Interrupt Control CC30 FE7C H 3E H CAPCOM 30 CC30IC b F18C H E C6 H CAPCOM 30 Interrupt Control CC31 FE7E H 3F H CAPCOM 31 CC31IC b F194 H E CA H CAPCOM 31 Interrupt Control CCM0 b FF52 H A9 H CAPCOM Mode Control 0 CCM1 b FF54 H AA H CAPCOM Mode Control 1 CCM2 b FF56 H AB H CAPCOM Mode Control 2 CCM3 b FF58 H AC H CAPCOM Mode Control 3 Semiconductor Group 20-6
7 CCM4 b FF22 H 91 H CAPCOM Mode Control 4 CCM5 b FF24 H 92 H CAPCOM Mode Control 5 CCM6 b FF26 H 93 H CAPCOM Mode Control 6 CCM7 b FF28 H 94 H CAPCOM Mode Control 7 CP FE10 H 08 H CPU Context Pointer FC00 H CRIC b FF6A H B5 H GPT2 CAPREL Interrupt Control CSP FE08 H 04 H CPU Code Segment Pointer (8 bits, not directly writeable) DP0L b F100 H E 80 H P0L Direction Control 00 H DP0H b F102 H E 81 H P0H Direction Control 00 H DP1L b F104 H E 82 H P1L Direction Control 00 H DP1H b F106 H E 83 H P1H Direction Control 00 H DP2 b FFC2 H E1 H Port 2 Direction Control DP3 b FFC6 H E3 H Port 3 Direction Control DP4 b FFCA H E5 H Port 4 Direction Control 00 H DP6 b FFCE H E7 H Port 6 Direction Control 00 H DP7 b FFD2 H E9 H Port 7 Direction Control 00 H DP8 b FFD6 H EB H Port 8 Direction Control 00 H DPP0 FE00 H 00 H CPU Data Page Pointer 0 (10 bits) DPP1 FE02 H 01 H CPU Data Page Pointer 1 (10 bits) 0001 H DPP2 FE04 H 02 H CPU Data Page Pointer 2 (10 bits) 0002 H DPP3 FE06 H 03 H CPU Data Page Pointer 3 (10 bits) 0003 H EXICON b F1C0 H E E0 H External Interrupt Control LAR EFn4 H X --- CAN Lower Arbitration (msg. n) UUUU H MCFG EFn6 H X --- CAN Message Configuration (msg. n) UU H MCR EFn0 H X --- CAN Message Control (msg. n) UUUU H MDC b FF0E H 87 H CPU Multiply Divide Control MDH FE0C H 06 H CPU Multiply Divide High Word MDL FE0E H 07 H CPU Multiply Divide Low Word ODP2 b F1C2 H E E1 H Port 2 Open Drain Control ODP3 b F1C6 H E E3 H Port 3 Open Drain Control ODP6 b F1CE H E E7 H Port 6 Open Drain Control 00 H ODP7 b F1D2 H E E9 H Port 7 Open Drain Control 00 H Semiconductor Group 20-7
8 ODP8 b F1D6 H E EB H Port 8 Open Drain Control 00 H ONES b FF1E H 8F H Constant 1 s (read only) FFFF H P0L b FF00 H 80 H Port 0 Low (Lower half of PORT0) 00 H P0H b FF02 H 81 H Port 0 High (Upper half of PORT0) 00 H P1L b FF04 H 82 H Port 1 Low (Lower half of PORT1) 00 H P1H b FF06 H 83 H Port 1 High (Upper half of PORT1) 00 H P2 b FFC0 H E0 H Port 2 P3 b FFC4 H E2 H Port 3 P4 b FFC8 H E4 H Port 4 (8 bits) 00 H P5 b FFA2 H D1 H Port 5 (read only) XXXX H P6 b FFCC H E6 H Port 6 (8 bits) 00 H P7 b FFD0 H E8 H Port 7 (8 bits) 00 H P8 b FFD4 H EA H Port 8 (8 bits) 00 H PECC0 FEC0 H 60 H PEC Channel 0 Control PECC1 FEC2 H 61 H PEC Channel 1 Control PECC2 FEC4 H 62 H PEC Channel 2 Control PECC3 FEC6 H 63 H PEC Channel 3 Control PECC4 FEC8 H 64 H PEC Channel 4 Control PECC5 FECA H 65 H PEC Channel 5 Control PECC6 FECC H 66 H PEC Channel 6 Control PECC7 FECE H 67 H PEC Channel 7 Control PICON F1C4 H E E2 H Port Input Threshold Control PP0 F038 H E 1C H PWM Module Period 0 PP1 F03A H E 1D H PWM Module Period 1 PP2 F03C H E 1E H PWM Module Period 2 PP3 F03E H E 1F H PWM Module Period 3 PSW b FF10 H 88 H CPU Program Status Word PT0 F030 H E 18 H PWM Module Up/Down Counter 0 PT1 F032 H E 19 H PWM Module Up/Down Counter 1 PT2 F034 H E 1A H PWM Module Up/Down Counter 2 PT3 F036 H E 1B H PWM Module Up/Down Counter 3 PW0 FE30 H 18 H PWM Module Pulse Width 0 PW1 FE32 H 19 H PWM Module Pulse Width 1 Semiconductor Group 20-8
9 PW2 FE34 H 1A H PWM Module Pulse Width 2 PW3 FE36 H 1B H PWM Module Pulse Width 3 PWMCON0 b FF30 H 98 H PWM Module Control 0 PWMCON1 b FF32 H 99 H PWM Module Control 1 PWMIC b F17E H E BF H PWM Module Interrupt Control RP0H b F108 H E 84 H System Startup Configuration (Rd. only) XX H S0BG FEB4 H 5A H Serial Channel 0 Baud Rate Generator Reload S0CON b FFB0 H D8 H Serial Channel 0 Control S0EIC b FF70 H B8 H Serial Channel 0 Error Interrupt Control S0RBUF FEB2 H 59 H Serial Channel 0 Receive Buffer (read only) S0RIC b FF6E H B7 H Serial Channel 0 Receive Interrupt Control S0TBIC b F19C H E CE H Serial Channel 0 Transmit Buffer Interrupt Control XXXX H S0TBUF FEB0 H 58 H Serial Channel 0 Transmit Buffer S0TIC b FF6C H B6 H Serial Channel 0 Transmit Interrupt Control SP FE12 H 09 H CPU System Stack Pointer FC00 H SSCBR F0B4 H E 5A H SSC Baudrate SSCCON b FFB2 H D9 H SSC Control SSCEIC b FF76 H BB H SSC Error Interrupt Control SSCRB F0B2 H E 59 H SSC Receive Buffer (read only) XXXX H SSCRIC b FF74 H BA H SSC Receive Interrupt Control SSCTB F0B0 H E 58 H SSC Transmit Buffer (write only) SSCTIC b FF72 H B9 H SSC Transmit Interrupt Control STKOV FE14 H 0A H CPU Stack Overflow Pointer FA00 H STKUN FE16 H 0B H CPU Stack Underflow Pointer FC00 H SYSCON b FF12 H 89 H CPU System Configuration 1) 0XX0 H T0 FE50 H 28 H CAPCOM Timer 0 T01CON b FF50 H A8 H CAPCOM Timer 0 and Timer 1 Control T0IC b FF9C H CE H CAPCOM Timer 0 Interrupt Control T0REL FE54 H 2A H CAPCOM Timer 0 Reload Semiconductor Group 20-9
10 T1 FE52 H 29 H CAPCOM Timer 1 T1IC b FF9E H CF H CAPCOM Timer 1 Interrupt Control T1REL FE56 H 2B H CAPCOM Timer 1 Reload T2 FE40 H 20 H GPT1 Timer 2 T2CON b FF40 H A0 H GPT1 Timer 2 Control T2IC b FF60 H B0 H GPT1 Timer 2 Interrupt Control T3 FE42 H 21 H GPT1 Timer 3 T3CON b FF42 H A1 H GPT1 Timer 3 Control T3IC b FF62 H B1 H GPT1 Timer 3 Interrupt Control T4 FE44 H 22 H GPT1 Timer 4 T4CON b FF44 H A2 H GPT1 Timer 4 Control T4IC b FF64 H B2 H GPT1 Timer 4 Interrupt Control T5 FE46 H 23 H GPT2 Timer 5 T5CON b FF46 H A3 H GPT2 Timer 5 Control T5IC b FF66 H B3 H GPT2 Timer 5 Interrupt Control T6 FE48 H 24 H GPT2 Timer 6 T6CON b FF48 H A4 H GPT2 Timer 6 Control T6IC b FF68 H B4 H GPT2 Timer 6 Interrupt Control T7 F050 H E 28 H CAPCOM Timer 7 T78CON b FF20 H 90 H CAPCOM Timer 7 and 8 Control T7IC b F17A H E BD H CAPCOM Timer 7 Interrupt Control T7REL F054 H E 2A H CAPCOM Timer 7 Reload T8 F052 H E 29 H CAPCOM Timer 8 T8IC b F17C H E BE H CAPCOM Timer 8 Interrupt Control T8REL F056 H E 2B H CAPCOM Timer 8 Reload TFR b FFAC H D6 H Trap Flag UAR EFn2 H X --- CAN Upper Arbitration (msg. n) UUUU H WDT FEAE H 57 H Watchdog Timer (read only) WDTCON b FFAE H D7 H Watchdog Timer Control 000X 2) H XP0IC b F186 H E C3 H X-Peripheral 0 Interrupt Control XP1IC b F18E H E C7 H X-Peripheral 1 Interrupt Control XP2IC b F196 H E CB H X-Peripheral 2 Interrupt Control Semiconductor Group 20-10
11 XP3IC b F19E H E CF H X-Peripheral 3 Interrupt Control ZEROS b FF1C H 8E H Constant 0 s (read only) Note: 1) The system configuration is selected during reset. 2) Bit WDTR indicates a watchdog timer triggered reset. Semiconductor Group 20-11
12 20.3 s ordered by The following table lists all SFRs which are implemented in the C167 ordered by their physical address. Bit-addressable SFRs are marked with the letter b in column. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter E in column. s within on-chip X-Peripherals (CAN) are marked with the letter X in column. C1CSR EF00 H X --- CAN Control / Status XX01 H C1IR EF02 H X --- CAN Interrupt XX H C1BTR EF04 H X --- CAN Bit Timing UUUU H C1GMS EF06 H X --- CAN Global Mask Short UFUU H C1UGML EF08 H X --- CAN Upper Global Mask Long UUUU H C1LGML EF0A H X --- CAN Lower Global Mask Long UUUU H C1UMLM EF0C H X --- CAN Upper Mask of Last Message UUUU H C1LMLM EF0E H X --- CAN Lower Mask of Last Message UUUU H MCR EFn0 H X --- CAN Message Control (msg. n) UUUU H UAR EFn2 H X --- CAN Upper Arbitration (msg. n) UUUU H LAR EFn4 H X --- CAN Lower Arbitration (msg. n) UUUU H MCFG EFn6 H X --- CAN Message Configuration (msg. n) UU H PT0 F030 H E 18 H PWM Module Up/Down Counter 0 PT1 F032 H E 19 H PWM Module Up/Down Counter 1 PT2 F034 H E 1A H PWM Module Up/Down Counter 2 PT3 F036 H E 1B H PWM Module Up/Down Counter 3 PP0 F038 H E 1C H PWM Module Period 0 PP1 F03A H E 1D H PWM Module Period 1 PP2 F03C H E 1E H PWM Module Period 2 PP3 F03E H E 1F H PWM Module Period 3 T7 F050 H E 28 H CAPCOM Timer 7 T8 F052 H E 29 H CAPCOM Timer 8 T7REL F054 H E 2A H CAPCOM Timer 7 Reload T8REL F056 H E 2B H CAPCOM Timer 8 Reload ADDAT2 F0A0 H E 50 H A/D Converter 2 Result SSCTB F0B0 H E 58 H SSC Transmit Buffer (write only) SSCRB F0B2 H E 59 H SSC Receive Buffer (read only) XXXX H Semiconductor Group 20-12
13 SSCBR F0B4 H E 5A H SSC Baudrate DP0L b F100 H E 80 H P0L Direction Control 00 H DP0H b F102 H E 81 H P0H Direction Control 00 H DP1L b F104 H E 82 H P1L Direction Control 00 H DP1H b F106 H E 83 H P1H Direction Control 00 H RP0H b F108 H E 84 H System Startup Configuration (Rd. only) XX H CC16IC b F160 H E B0 H CAPCOM 16 Interrupt Control CC17IC b F162 H E B1 H CAPCOM 17 Interrupt Control CC18IC b F164 H E B2 H CAPCOM 18 Interrupt Control CC19IC b F166 H E B3 H CAPCOM 19 Interrupt Control CC20IC b F168 H E B4 H CAPCOM 20 Interrupt Control CC21IC b F16A H E B5 H CAPCOM 21 Interrupt Control CC22IC b F16C H E B6 H CAPCOM 22 Interrupt Control CC23IC b F16E H E B7 H CAPCOM 23 Interrupt Control CC24IC b F170 H E B8 H CAPCOM 24 Interrupt Control CC25IC b F172 H E B9 H CAPCOM 25 Interrupt Control CC26IC b F174 H E BA H CAPCOM 26 Interrupt Control CC27IC b F176 H E BB H CAPCOM 27 Interrupt Control CC28IC b F178 H E BC H CAPCOM 28 Interrupt Control T7IC b F17A H E BD H CAPCOM Timer 7 Interrupt Control T8IC b F17C H E BE H CAPCOM Timer 8 Interrupt Control PWMIC b F17E H E BF H PWM Module Interrupt Control CC29IC b F184 H E C2 H CAPCOM 29 Interrupt Control XP0IC b F186 H E C3 H X-Peripheral 0 Interrupt Control CC30IC b F18C H E C6 H CAPCOM 30 Interrupt Control XP1IC b F18E H E C7 H X-Peripheral 1 Interrupt Control CC31IC b F194 H E CA H CAPCOM 31 Interrupt Control XP2IC b F196 H E CB H X-Peripheral 2 Interrupt Control S0TBIC b F19C H E CE H Serial Channel 0 Transmit Buffer Interrupt Control XP3IC b F19E H E CF H X-Peripheral 3 Interrupt Control EXICON b F1C0 H E E0 H External Interrupt Control ODP2 b F1C2 H E E1 H Port 2 Open Drain Control Semiconductor Group 20-13
14 PICON F1C4 H E E2 H Port Input Threshold Control ODP3 b F1C6 H E E3 H Port 3 Open Drain Control ODP6 b F1CE H E E7 H Port 6 Open Drain Control 00 H ODP7 b F1D2 H E E9 H Port 7 Open Drain Control 00 H ODP8 b F1D6 H E EB H Port 8 Open Drain Control 00 H DPP0 FE00 H 00 H CPU Data Page Pointer 0 (10 bits) DPP1 FE02 H 01 H CPU Data Page Pointer 1 (10 bits) 0001 H DPP2 FE04 H 02 H CPU Data Page Pointer 2 (10 bits) 0002 H DPP3 FE06 H 03 H CPU Data Page Pointer 3 (10 bits) 0003 H CSP FE08 H 04 H CPU Code Segment Pointer (8 bits, not directly writeable) MDH FE0C H 06 H CPU Multiply Divide High Word MDL FE0E H 07 H CPU Multiply Divide Low Word CP FE10 H 08 H CPU Context Pointer FC00 H SP FE12 H 09 H CPU System Stack Pointer FC00 H STKOV FE14 H 0A H CPU Stack Overflow Pointer FA00 H STKUN FE16 H 0B H CPU Stack Underflow Pointer FC00 H ADDRSEL1 FE18 H 0C H Select 1 ADDRSEL2 FE1A H 0D H Select 2 ADDRSEL3 FE1C H 0E H Select 3 ADDRSEL4 FE1E H 0F H Select 4 PW0 FE30 H 18 H PWM Module Pulse Width 0 PW1 FE32 H 19 H PWM Module Pulse Width 1 PW2 FE34 H 1A H PWM Module Pulse Width 2 PW3 FE36 H 1B H PWM Module Pulse Width 3 T2 FE40 H 20 H GPT1 Timer 2 T3 FE42 H 21 H GPT1 Timer 3 T4 FE44 H 22 H GPT1 Timer 4 T5 FE46 H 23 H GPT2 Timer 5 T6 FE48 H 24 H GPT2 Timer 6 CAPREL FE4A H 25 H GPT2 Capture/Reload T0 FE50 H 28 H CAPCOM Timer 0 T1 FE52 H 29 H CAPCOM Timer 1 Semiconductor Group 20-14
15 T0REL FE54 H 2A H CAPCOM Timer 0 Reload T1REL FE56 H 2B H CAPCOM Timer 1 Reload CC16 FE60 H 30 H CAPCOM 16 CC17 FE62 H 31 H CAPCOM 17 CC18 FE64 H 32 H CAPCOM 18 CC19 FE66 H 33 H CAPCOM 19 CC20 FE68 H 34 H CAPCOM 20 CC21 FE6A H 35 H CAPCOM 21 CC22 FE6C H 36 H CAPCOM 22 CC23 FE6E H 37 H CAPCOM 23 CC24 FE70 H 38 H CAPCOM 24 CC25 FE72 H 39 H CAPCOM 25 CC26 FE74 H 3A H CAPCOM 26 CC27 FE76 H 3B H CAPCOM 27 CC28 FE78 H 3C H CAPCOM 28 CC29 FE7A H 3D H CAPCOM 29 CC30 FE7C H 3E H CAPCOM 30 CC31 FE7E H 3F H CAPCOM 31 CC0 FE80 H 40 H CAPCOM 0 CC1 FE82 H 41 H CAPCOM 1 CC2 FE84 H 42 H CAPCOM 2 CC3 FE86 H 43 H CAPCOM 3 CC4 FE88 H 44 H CAPCOM 4 CC5 FE8A H 45 H CAPCOM 5 CC6 FE8C H 46 H CAPCOM 6 CC7 FE8E H 47 H CAPCOM 7 CC8 FE90 H 48 H CAPCOM 8 CC9 FE92 H 49 H CAPCOM 9 CC10 FE94 H 4A H CAPCOM 10 CC11 FE96 H 4B H CAPCOM 11 CC12 FE98 H 4C H CAPCOM 12 CC13 FE9A H 4D H CAPCOM 13 CC14 FE9C H 4E H CAPCOM 14 Semiconductor Group 20-15
16 CC15 FE9E H 4F H CAPCOM 15 ADDAT FEA0 H 50 H A/D Converter Result WDT FEAE H 57 H Watchdog Timer (read only) S0TBUF FEB0 H 58 H Serial Channel 0 Transmit Buffer S0RBUF FEB2 H 59 H Serial Channel 0 Receive Buffer (read only) S0BG FEB4 H 5A H Serial Channel 0 Baud Rate Generator Reload XXXX H PECC0 FEC0 H 60 H PEC Channel 0 Control PECC1 FEC2 H 61 H PEC Channel 1 Control PECC2 FEC4 H 62 H PEC Channel 2 Control PECC3 FEC6 H 63 H PEC Channel 3 Control PECC4 FEC8 H 64 H PEC Channel 4 Control PECC5 FECA H 65 H PEC Channel 5 Control PECC6 FECC H 66 H PEC Channel 6 Control PECC7 FECE H 67 H PEC Channel 7 Control P0L b FF00 H 80 H Port 0 Low (Lower half of PORT0) 00 H P0H b FF02 H 81 H Port 0 High (Upper half of PORT0) 00 H P1L b FF04 H 82 H Port 1 Low (Lower half of PORT1) 00 H P1H b FF06 H 83 H Port 1 High (Upper half of PORT1) 00 H BUSCON0 b FF0C H 86 H Bus Configuration 0 MDC b FF0E H 87 H CPU Multiply Divide Control PSW b FF10 H 88 H CPU Program Status Word SYSCON b FF12 H 89 H CPU System Configuration 0XX0 1) H BUSCON1 b FF14 H 8A H Bus Configuration 1 BUSCON2 b FF16 H 8B H Bus Configuration 2 BUSCON3 b FF18 H 8C H Bus Configuration 3 BUSCON4 b FF1A H 8D H Bus Configuration 4 ZEROS b FF1C H 8E H Constant 0 s (read only) ONES b FF1E H 8F H Constant 1 s (read only) FFFF H T78CON b FF20 H 90 H CAPCOM Timer 7 and 8 Control CCM4 b FF22 H 91 H CAPCOM Mode Control 4 CCM5 b FF24 H 92 H CAPCOM Mode Control 5 Semiconductor Group 20-16
17 CCM6 b FF26 H 93 H CAPCOM Mode Control 6 CCM7 b FF28 H 94 H CAPCOM Mode Control 7 PWMCON0 b FF30 H 98 H PWM Module Control 0 PWMCON1 b FF32 H 99 H PWM Module Control 1 T2CON b FF40 H A0 H GPT1 Timer 2 Control T3CON b FF42 H A1 H GPT1 Timer 3 Control T4CON b FF44 H A2 H GPT1 Timer 4 Control T5CON b FF46 H A3 H GPT2 Timer 5 Control T6CON b FF48 H A4 H GPT2 Timer 6 Control T01CON b FF50 H A8 H CAPCOM Timer 0 and Timer 1 Control CCM0 b FF52 H A9 H CAPCOM Mode Control 0 CCM1 b FF54 H AA H CAPCOM Mode Control 1 CCM2 b FF56 H AB H CAPCOM Mode Control 2 CCM3 b FF58 H AC H CAPCOM Mode Control 3 T2IC b FF60 H B0 H GPT1 Timer 2 Interrupt Control T3IC b FF62 H B1 H GPT1 Timer 3 Interrupt Control T4IC b FF64 H B2 H GPT1 Timer 4 Interrupt Control T5IC b FF66 H B3 H GPT2 Timer 5 Interrupt Control T6IC b FF68 H B4 H GPT2 Timer 6 Interrupt Control CRIC b FF6A H B5 H GPT2 CAPREL Interrupt Control S0TIC b FF6C H B6 H Serial Channel 0 Transmit Interrupt Control S0RIC b FF6E H B7 H Serial Channel 0 Receive Interrupt Control S0EIC b FF70 H B8 H Serial Channel 0 Error Interrupt Control SSCTIC b FF72 H B9 H SSC Transmit Interrupt Control SSCRIC b FF74 H BA H SSC Receive Interrupt Control SSCEIC b FF76 H BB H SSC Error Interrupt Control CC0IC b FF78 H BC H CAPCOM 0 Interrupt Control CC1IC b FF7A H BD H CAPCOM 1 Interrupt Control CC2IC b FF7C H BE H CAPCOM 2 Interrupt Control CC3IC b FF7E H BF H CAPCOM 3 Interrupt Control CC4IC b FF80 H C0 H CAPCOM 4 Interrupt Control Semiconductor Group 20-17
18 CC5IC b FF82 H C1 H CAPCOM 5 Interrupt Control CC6IC b FF84 H C2 H CAPCOM 6 Interrupt Control CC7IC b FF86 H C3 H CAPCOM 7 Interrupt Control CC8IC b FF88 H C4 H CAPCOM 8 Interrupt Control CC9IC b FF8A H C5 H CAPCOM 9 Interrupt Control CC10IC b FF8C H C6 H CAPCOM 10 Interrupt Control CC11IC b FF8E H C7 H CAPCOM 11 Interrupt Control CC12IC b FF90 H C8 H CAPCOM 12 Interrupt Control CC13IC b FF92 H C9 H CAPCOM 13 Interrupt Control CC14IC b FF94 H CA H CAPCOM 14 Interrupt Control CC15IC b FF96 H CB H CAPCOM 15 Interrupt Control ADCIC b FF98 H CC H A/D Converter End of Conversion Interrupt Control ADEIC b FF9A H CD H A/D Converter Overrun Error Interrupt Control T0IC b FF9C H CE H CAPCOM Timer 0 Interrupt Control T1IC b FF9E H CF H CAPCOM Timer 1 Interrupt Control ADCON b FFA0 H D0 H A/D Converter Control P5 b FFA2 H D1 H Port 5 (read only) XXXX H TFR b FFAC H D6 H Trap Flag WDTCON b FFAE H D7 H Watchdog Timer Control 2) 000X H S0CON b FFB0 H D8 H Serial Channel 0 Control SSCCON b FFB2 H D9 H SSC Control P2 b FFC0 H E0 H Port 2 DP2 b FFC2 H E1 H Port 2 Direction Control P3 b FFC4 H E2 H Port 3 DP3 b FFC6 H E3 H Port 3 Direction Control P4 b FFC8 H E4 H Port 4 (8 bits) 00 H DP4 b FFCA H E5 H Port 4 Direction Control 00 H P6 b FFCC H E6 H Port 6 (8 bits) 00 H DP6 b FFCE H E7 H Port 6 Direction Control 00 H P7 b FFD0 H E8 H Port 7 (8 bits) 00 H DP7 b FFD2 H E9 H Port 7 Direction Control 00 H Semiconductor Group 20-18
19 P8 b FFD4 H EA H Port 8 (8 bits) 00 H DP8 b FFD6 H EB H Port 8 Direction Control 00 H Note: 1) The system configuration is selected during reset. 2) Bit WDTR indicates a watchdog timer triggered reset Special Notes PEC Pointer s The source and destination pointers for the peripheral event controller are mapped to a special area within the internal RAM. Pointers that are not occupied by the PEC may therefore be used like normal RAM. During Power Down mode or any warm reset the PEC pointers are preserved. The PEC and its registers are described in chapter Interrupt and Trap Functions. GPR Access in the ESFR Area The locations 00 F000H...00 F01EH within the ESFR area are reserved and provide access to the current register bank via short register addressing modes. The GPRs are mirrored to the ESFR area which allows access to the current register bank even after switching register spaces (see example below). MOV R5, DP3 ;GPR access via SFR area EXTR #1 MOV R5, ODP3 ;GPR access via ESFR area Writing Bytes to SFRs All special function registers may be accessed wordwise or bytewise (some of them even bitwise). Reading bytes from word SFRs is a non-critical operation. However, when writing bytes to word SFRs the complementary byte of the respective SFR is cleared with the write operation. Semiconductor Group 20-19
4.3 Analog Value Representation
4.3 Analog Value Representation Introduction This section describes the analog values for all the measuring ranges and output ranges which you can use with the analog modules. Converting analog values
CiA Draft Standard Proposal 447
CiA Draft Standard Proposal 447 Application profile for special-purpose car add-on devices Part 4: Pre-defined s and This DSP is for CiA members only and may be changed without notification. Version: 1.0
The Advanced Encryption Standard
Lecturers: Mark D. Ryan and David Galindo. Cryptography 2017. Slide: 48 The Advanced Encryption Standard Successor of DES DES considered insecure; 3DES considered too slow. NIST competition in 1997 15
Cristina Nita-Rotaru. CS355: Cryptography. Lecture 9: Encryption modes. AES
CS355: Cryptography Lecture 9: Encryption modes. AES Encryption modes: ECB } Message is broken into independent blocks of block_size bits; } Electronic Code Book (ECB): each block encrypted separately.
EEE Lecture 1 -1-
EEE3410 - Lecture 1-1- 1. PC -> Address Move content of the Program Counter to Address Bus 2. Mem(Add) -> ID Move the Data at Location Add from main memory to Instruction Decoder (ID) 3. Acc s -> ALU Move
Developing a Distributed Java-based Speech Recognition Engine
The ITB Journal Volume 5 Issue 1 Article 2 2004 Developing a Distributed Java-based Speech Recognition Engine Tony Ayers Institute of Technology Blanchardstown, tony.ayers@itb.ie Brian Nolan Institute
,- # (%& ( = 0,% % <,( #, $ <<,( > 0,% #% ( - + % ,'3-% & '% #% <,( #, $ <<,(,9 (% +('$ %(- $'$ & " ( (- +' $%(& 2,#. = '%% ($ (- +' $ '%("
FEATURES!" #$$ % %&' % '( $ %( )$*++$ '(% $ *++$ %(%,- *(% (./ *( #'% # *( 0% ( *( % #$$ *( '( + 2' %( $ '( 2! '3 ((&!( *( 4 '3.%" / '3 3.% 7" 28" 9' 9,*: $ 9,*: $% (+'( / *(.( # ( 2(- %3 # $((% # ;' '3$-,(
Documentation for package interchar
Documentation for package interchar Zou Hu (zohooo@yeah.net) February 17, 2015 Contents 1 Introduction 1 2 Commands for normal users 2 3 Commands for macro writers 3 4 Implementation 4 1 Introduction With
LABORATORY MANUAL MICROPROCESSORS AND MICROCONTROLLERS. S.E (I.T) ( S e m. IV)
LABORATORY MANUAL MICROPROCESSORS AND MICROCONTROLLERS S.E (I.T) ( S e m. IV) 1 I n d e x Serial No. T i tl e P a g e N o. 1 8 bit addition with carry 3 2 16 bit addition with carry 5 3 8 bit multiplication
Secret Key Systems (block encoding) Encrypting a small block of text (say 64 bits) General considerations for cipher design:
Secret Key Systems (block encoding) Encrypting a small block of text (say 64 bits) General considerations for cipher design: Secret Key Systems Encrypting a small block of text (say 64 bits) General considerations
LABORATORY MANUAL MICROPROCESSOR AND MICROCONTROLLER
LABORATORY MANUAL S u b j e c t : MICROPROCESSOR AND MICROCONTROLLER TE (E lectr onics) ( S e m V ) 1 I n d e x Serial No T i tl e P a g e N o M i c r o p r o c e s s o r 8 0 8 5 1 8 Bit Addition by Direct
Profiling the International New Venture -A literature review of the empirical evidence
The ITB Journal Volume 5 Issue 1 Article 11 2004 Profiling the International New Venture -A literature review of the empirical evidence Natasha Evers School ofbusiness & Humanities Institute of Technology,
Introduction. CSC/ECE 574 Computer and Network Security. Outline. Introductory Remarks Feistel Cipher DES AES
CSC/ECE 574 Computer and Network Security Topic 3.1 Secret Key Cryptography Algorithms CSC/ECE 574 Dr. Peng Ning 1 Outline Introductory Remarks Feistel Cipher DES AES CSC/ECE 574 Dr. Peng Ning 2 Introduction
21 Yes, in LFP between ldd y and stx y. A) accuracy. J) desk check. D) bandwidth. E (partial credit B) D. P) latency. U) polled interrupt W) private
EE345L Spring 2005 Final Version A Solution Page 1 Jonathan W. Valvano May 14, 2005, 9am - 12 noon First: Last: (4) Question 1. Give max number of bytes on the stack (4) Question 2. Yes/no. If yes, state
A B C DEF A AE E F A A AB F F A
A B C DEF A AE E F A A AB F F A F A F A B E A A F DEF AE D AD A B 2 FED AE A BA B EBF A F AE A E F A A A F ED FE F A F ED EF F A B E AE F DEF A BA FA B E F F E FB ED AB ADA AD A BA FA B AE A EFB A A F
System Data Bus (8-bit) Data Buffer. Internal Data Bus (8-bit) 8-bit register (R) 3-bit address 16-bit register pair (P) 2-bit address
Intel 8080 CPU block diagram 8 System Data Bus (8-bit) Data Buffer Registry Array B 8 C Internal Data Bus (8-bit) F D E H L ALU SP A PC Address Buffer 16 System Address Bus (16-bit) Internal register addressing:
AURORA: A Cryptographic Hash Algorithm Family
AURORA: A Cryptographic Hash Algorithm Family Submitters: Sony Corporation 1 and Nagoya University 2 Algorithm Designers: Tetsu Iwata 2, Kyoji Shibutani 1, Taizo Shirai 1, Shiho Moriai 1, Toru Akishita
Data Transfer Group. What we will learn in this session. ECE 511: Digital System & Microprocessor. Data transfer group instructions:
Data Transfer Group ECE 511: Digital System & Microprocessor What we will learn in this session Data transfer group instructions: Moving data around. 1 Data Transfer Group Instructions to Move data around.
Parts Manual. EPIC II Critical Care Bed REF 2031
EPIC II Critical Care Bed REF 2031 Parts Manual For parts or technical assistance call: USA: 1-800-327-0770 2013/05 B.0 2031-109-006 REV B www.stryker.com Table of Contents English Product Labels... 4
PART-A. 2. Expand ASCII and BCD ASCII American Standard Code for Information Interchange BCD Binary Coded Decimal
PART-A 1. What is radix? Give the radix for binary, octal, decimal and hexadecimal Radix is the total number of digits used in a particular number system Binary - 2 (0,1) Octal - 8 (0 to 7) Decimal - 10
Digital Electronics I
References Digital Electronics I Katz, R.H. (2004). Contemporary logic design. Benjamin/Cummings. Hayes, J.P. (1993). Introduction to digital logic design. Addison-Wesley. Horowitz, P. & Hill, W. (1989).
Unit 3. Digital encoding
Unit 3. Digital encoding Digital Electronic Circuits (Circuitos Electrónicos Digitales) E.T.S.I. Informática Universidad de Sevilla 9/2012 Jorge Juan 2010, 2011, 2012 You are free to
Questions of Ethical Responsibility in the Research of Unaccompanied Minors
The ITB Journal Volume 5 Issue 1 Article 27 2004 Questions of Ethical Responsibility in the Research of Unaccompanied Minors Oonagh Charleton School of Business and Humanities, Institute of Technology
CHAPTER 7. Exercises 17/ / /2 2 0
CHAPTER 7 Exercises E7. (a) For the whole part, we have: Quotient Remainders 23/2 /2 5 5/2 2 2/2 0 /2 0 Reading the remainders in reverse order, we obtain: 23 0 = 0 2 For the fractional part we have 2
Layout of 7400-series Chips Commonly Used in. CDA 3101: Introduction to Computer Hardware and Organization
Layout of 400-series Chips Commonly Used in CDA 30: Introduction to Computer Hardware and Organization Charles N. Winton Department of Computer and Information Sciences University of North Florida 999
Combinatorial Electrosynthesis in Microtiter Plate Wells with Ionic Liquid Electrolytes
Combinatorial Electrosynthesis in Microtiter Plate Wells with Ionic Liquid Electrolytes Markus Schwarz and Bernd Speiser Institut für rganische Chemie, Universität Tübingen, Auf der Morgenstelle 18, D
Consistency of Academic Performance in Higher Education: A Study of an Irish Business Degree Programme
The ITB Journal Volume 5 Issue 1 Article 5 2004 Consistency of Academic Performance in Higher Education: A Study of an Irish Business Degree Programme Julie Byrne Lecturer, School of Business and Humanities,
NACC Uniform Data Set (UDS) FTLD Module
NACC Uniform Data Set (UDS) FTLD Module Data Template For FOLLOW-UP Visit Packet Version 2.0, January 2012 Copyright 2013 University of Washington Created and published by the FTLD work group of the ADC
D EFB B E B EAB ABC DEF C A F C D C DEF C AD C AEC D D E C D EF B ABC AB CD A EFD AD D E
D EFB B E BEAB ABC DEF C A F C D C DEF C AD C AEC D D E A B C D EF B ABC AB CD A EFD AD D E FFF A B FBC AE BC D AD A D F D F D F D D B D A D A ED D D DD F D D D D A A DA ADD D F AD AD C A DD D D F D A
CHAPTER 5 A BLOCK CIPHER INVOLVING A KEY APPLIED ON BOTH THE SIDES OF THE PLAINTEXT
82 CHAPTER 5 A BLOCK CIPHER INVOLVING A KEY APPLIED ON BOTH THE SIDES OF THE PLAINTEXT 83 5.1 Introduction In a pioneering paper, Hill [5] developed a block cipher by using the modular arithmetic inverse
Architecture and development methodology for Location Based Services
The ITB Journal Volume 5 Issue 1 Article 13 2004 Architecture and development methodology for Location Based Services Aaron Hand School of Science, Institute of Technology at Tallaght, Dublin 24., aaron.hand@itnet.ie
Operation Modi of the Timer
PIAT ; Continuation Operation Modi of the Timer o Modus 0 : stopping the counter LC and UC are holded. IRQT is disabled (bit 7 of CMCR get 0) UF is be deleted (Bit 7 of SR) The data in UC, LC, UL, LL und
Grabber. Technical Manual
Grabber 0 MHZ Analog Signal Digitizer Technical Manual 0 th Street, Davis, CA, USA Tel: 0--00 Fax: 0--0 Email: sales@tern.com http://www.tern.com COPYRIGHT Grabber, and A-Engine are trademarks of TERN,
LOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Digital IC packages TTL (transistor-transistor
Justification of Investment in IT systems
The ITB Journal Volume 5 Issue 1 Article 12 2004 Justification of Investment in IT systems Aidan Farrell School of Computing, Dublin Institute of Technology, Kevin Street, Dublin 8., aidan.farrell@dit.ie
NACC Uniform Data Set (UDS) FTLD Module
NACC Uniform Data Set (UDS) FTLD Module Data Template For Initial Visit Packet Version 2.0, January 2012 Copyright 2013 University of Washington Created and published by the FTLD work group of the ADC
35H MPa Hydraulic Cylinder 3.5 MPa Hydraulic Cylinder 35H-3
- - - - ff ff - - - - - - B B BB f f f f f f f 6 96 f f f f f f f 6 f LF LZ f 6 MM f 9 P D RR DD M6 M6 M6 M. M. M. M. M. SL. E 6 6 9 ZB Z EE RC/ RC/ RC/ RC/ RC/ ZM 6 F FP 6 K KK M. M. M. M. M M M M f f
An Adaptive elearning framework- Design Issues and Considerations
The ITB Journal Volume 5 Issue 1 Article 4 2004 An Adaptive elearning framework- Design Issues and Considerations Maria Brennan Institute of Technology Blanchardstown, maria.brennan@itb.ie Follow this
Vidyalankar S.E. Sem. III [INFT] Analog and Digital Circuits Prelim Question Paper Solution
![Vidyalankar S.E. Sem. III [INFT] Analog and Digital Circuits Prelim Question Paper Solution](/thumbs/77/75121612.jpg "Vidyalankar S.E. Sem. III [INFT] Analog and Digital Circuits Prelim Question Paper Solution")
. (a). (b) S.E. Sem. III [INFT] Analog and Digital Circuits Prelim Question Paper Solution Practical Features of OpAmp (A 74) i) Large voltage gain (of the order of 2 0 5 ) ii) Very high input resistance
EECS150 - Digital Design Lecture 23 - FFs revisited, FIFOs, ECCs, LSFRs. Cross-coupled NOR gates
EECS150 - Digital Design Lecture 23 - FFs revisited, FIFOs, ECCs, LSFRs April 16, 2009 John Wawrzynek Spring 2009 EECS150 - Lec24-blocks Page 1 Cross-coupled NOR gates remember, If both R=0 & S=0, then
A Very Efficient Pseudo-Random Number Generator Based On Chaotic Maps and S-Box Tables M. Hamdi, R. Rhouma, S. Belghith
A Very Efficient Pseudo-Random Number Generator Based On Chaotic Maps and S-Box Tables M. Hamdi, R. Rhouma, S. Belghith Abstract Generating random numbers are mainly used to create secret keys or random
i;\-'i frz q > R>? >tr E*+ [S I z> N g> F 'x sa :r> >,9 T F >= = = I Y E H H>tr iir- g-i I * s I!,i --' - = a trx - H tnz rqx o >.F g< s Ire tr () -s
5 C /? >9 T > ; '. ; J ' ' J. \ ;\' \.> ). L; c\ u ( (J ) \ 1 ) : C ) (... >\ > 9 e!) T C). '1!\ /_ \ '\ ' > 9 C > 9.' \( T Z > 9 > 5 P + 9 9 ) :> : + (. \ z : ) z cf C : u 9 ( :!z! Z c (! $ f 1 :.1 f.
A B CDE F B FD D A C AF DC A F
International Journal of Arts & Sciences, CD-ROM. ISSN: 1944-6934 :: 4(20):121 131 (2011) Copyright c 2011 by InternationalJournal.org A B CDE F B FD D A C A BC D EF C CE C A D ABC DEF B B C A E E C A
The Rijndael Block Cipher
The Rijndael Block Cipher Vincent Leith MATH 27.2 May 3, 2 A brief look at the mathematics behind the Rijndael Block Chiper. Introduction The Rijndael Block Chiper was brought about by Joan Daemen and
NTE74HC299 Integrated Circuit TTL High Speed CMOS, 8 Bit Universal Shift Register with 3 State Output
NTE74HC299 Integrated Circuit TTL High Speed CMOS, 8 Bit Universal Shift Register with 3 State Output Description: The NTE74HC299 is an 8 bit shift/storage register with three state bus interface capability
Shift Register Counters
Shift Register Counters Shift register counter: a shift register with the serial output connected back to the serial input. They are classified as counters because they give a specified sequence of states.
PART TEMP RANGE PIN-PACKAGE
9-0850; Rev 4; 6/0 Ω μ INT INT μ PART TEMP RANGE PIN-PACKAGE MAX7359ETG+ -40 C to +85 C 24 TQFN-EP* MAX7359EWA+ -40 C to +85 C 25 WLP * TOP VIEW AD0 GND IC COL0 8 7 6 5 4 3 INPUT +62V TO +36V V CC MAX7359
MASKED INVERSION IN GF(2 N ) USING MIXED FIELD REPRESENTATIONS AND ITS EFFICIENT IMPLEMENTATION FOR AES
Chapter X MASKED INVERSION IN GF( N ) USING MIXED FIELD REPRESENTATIONS AND ITS EFFICIENT IMPLEMENTATION FOR AES SHAY GUERON 1,, ORI PARZANCHEVSKY 1 and OR ZUK 1,3 1 Discretix Technologies, Netanya, ISRAEL
Intermediate Tier - Algebra revision
Intermediate Tier - Algebra revision Contents : Collecting like terms Multiplying terms together Indices Expanding single brackets Expanding double brackets Substitution Solving equations Finding nth term
Firmware Versionen. FAX-Geräte (Tinte) FAX-Geräte (Laser) DCP-Geräte (Tinte)
FAX-Geräte (Tinte) FAX-1355 lz0819_l.pmu 20.05.2010 L 66A3 0003 FAX-1360 lz0819_l.pmu 20.05.2010 L 66A3 0103 FAX-1460 lz0819_l.pmu 20.05.2010 L 66A3 0203 FAX-1560 lz0819_l.pmu 20.05.2010 L 66A3 0303 FAX-1835C
Administrivia. Course Objectives. Overview. Lecture Notes Week markem/cs333/ 2. Staff. 3. Prerequisites. 4. Grading. 1. Theory and application
Administrivia 1. markem/cs333/ 2. Staff 3. Prerequisites 4. Grading Course Objectives 1. Theory and application 2. Benefits 3. Labs TAs Overview 1. What is a computer system? CPU PC ALU System bus Memory
HERU Modbus. Reference Modbus addresses for HERU (Gen 3)
HERU Modbus Reference Modbus addresses for HERU 62-250 (Gen 3) Modbus Registers HERU v0.7.xls Coil status (1bit) RW 5.6.2016 Coil status Discrete Output (1bit) R/W Modbus Register Name Description Application
Enrico Nardelli Logic Circuits and Computer Architecture
Enrico Nardelli Logic Circuits and Computer Architecture Appendix B The design of VS0: a very simple CPU Rev. 1.4 (2009-10) by Enrico Nardelli B - 1 Instruction set Just 4 instructions LOAD M - Copy into
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering TIMING ANALYSIS Overview Circuits do not respond instantaneously to input changes
Default values for unit DX-S standard.
Default values for unit DX-S standard. UNIFLAIR ITALIA spa 1. USER (U) : USER PASSWORD 22. 2. FACTORY (F) : FACTORY PASSWORD 177. Prob PROBES Tipo Min Max U.M. Var. Def Presence Superv /1 Presence external
Chapter 7. Sequential Circuits Registers, Counters, RAM
Chapter 7. Sequential Circuits Registers, Counters, RAM Register - a group of binary storage elements suitable for holding binary info A group of FFs constitutes a register Commonly used as temporary storage
Introduction EE 224: INTRODUCTION TO DIGITAL CIRCUITS & COMPUTER DESIGN. Lecture 6: Sequential Logic 3 Registers & Counters 5/9/2010
EE 224: INTROUCTION TO IGITAL CIRCUITS & COMPUTER ESIGN Lecture 6: Sequential Logic 3 Registers & Counters 05/10/2010 Avinash Kodi, kodi@ohio.edu Introduction 2 A Flip-Flop stores one bit of information
Abel-Grassmann s bands. 1. Introduction
Quasigroups and Related Systems 11 (2004), 95 101 Abel-Grassmann s bands Petar V. Protić and Nebojša Stevanović Abstract Abel-Grassmann s groupoids or shortly AG-groupoids have been considered in a number
PART kHz CRYSTAL ALARM FUNCTION
19-2085; Rev 2; 5/04 3-Wire Serial RTC in a TDFN General Description The 3-wire serial interface real-time clock in a TDFN package contains a real-time clock/calendar and 31 x 8 bits of static RAM (SRAM).
ELECTROMAGNETIC FAULT INJECTION: TOWARDS A FAULT MODEL ON A 32-BIT MICROCONTROLLER
ELECTROMAGNETIC FAULT INJECTION: TOWARDS A FAULT MODEL ON A 32-BIT MICROCONTROLLER Nicolas Moro 1,3, Amine Dehbaoui 2, Karine Heydemann 3, Bruno Robisson 1, Emmanuelle Encrenaz 3 1 CEA Commissariat à l
Appendix D Nomenclature. Abstract
Appendix D Abstract This appendix presents all the common used abbreviations and symbols. The items are listed in groups of units, e.g. [V], [A] and so forth. Instantaneous values are presented with lower
CHAPTER 2 BOOLEAN ALGEBRA
CHAPTER 2 BOOLEAN ALGEBRA This chapter in the book includes: Objectives Study Guide 2.1 Introduction 2.2 Basic Operations 2.3 Boolean Expressions and Truth Tables 2.4 Basic Theorems 2.5 Commutative, Associative,
Communication description SCYLAR -HEAT. Communication description
HEAT Communication description 1 Contents Page 1. INTRODUCTION. GENERAL INFORMATION.1 Protocol. Addressing 3..1 Primary Addressing 3.. Secondary Addressing 3.3 Baudrate 4.4 Readinglist 4 3. SND_NKE 5 4.
ACCRS/QUALITY CORE CORRELATION DOCUMENT: ALGEBRA I
ACCRS/QUALITY CORE CORRELATION DOCUMENT: ALGEBRA I Revised March 25, 2013 Extend the properties of exponents to rational exponents. 1. [N-RN1] Explain how the definition of the meaning of rational exponents
MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) State any two Boolean laws. (Any 2 laws 1 mark each)
Subject Code: 17333 Model Answer Page 1/ 27 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model
page 1 Total ( )
A B C D E F Costs budget of [Claimant / Defendant] dated [ ] Estimated page 1 Work done / to be done Pre-action Disbs ( ) Time ( ) Disbs ( ) Time ( ) Total ( ) 1 Issue /statements of case 0.00 0.00 CMC
UNIT II COMBINATIONAL CIRCUITS:
UNIT II COMBINATIONAL CIRCUITS: INTRODUCTION: The digital system consists of two types of circuits, namely (i) (ii) Combinational circuits Sequential circuits Combinational circuit consists of logic gates
Triangle Congruence and Similarity Review. Show all work for full credit. 5. In the drawing, what is the measure of angle y?
Triangle Congruence and Similarity Review Score Name: Date: Show all work for full credit. 1. In a plane, lines that never meet are called. 5. In the drawing, what is the measure of angle y? A. parallel
Menu. Excitation Tables (Bonus Slide) EEL3701 EEL3701. Registers, RALU, Asynch, Synch
Menu Registers >Storage Registers >Shift Registers More LSI Components >Arithmetic-Logic Units (ALUs) > Carry-Look-Ahead Circuitry (skip this) Asynchronous versus Synchronous Look into my... 1 Excitation
8/13/16. Data analysis and modeling: the tools of the trade. Ø Set of numbers. Ø Binary representation of numbers. Ø Floating points.
Data analysis and modeling: the tools of the trade Patrice Koehl Department of Biological Sciences National University of Singapore http://www.cs.ucdavis.edu/~koehl/teaching/bl5229 koehl@cs.ucdavis.edu
Plane Trusses Trusses
TRUSSES Plane Trusses Trusses- It is a system of uniform bars or members (of various circular section, angle section, channel section etc.) joined together at their ends by riveting or welding and constructed
E2T0 DVP
29-5-26 5116868-E2T DVP-11363-1 ENGLISH Thank you for choosing Delta s DVP series PLC. DVP4TC-E2 temperature measurement module receives 4 points of external thermocouple temperature sensors (J-type, K-type,
LOGIC CIRCUITS. Basic Experiment and Design of Electronics
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Outline Combinational logic circuits Output
Collisions Of SHA-0 and Reduced SHA-1
Collisions Of SHA-0 and Reduced SHA-1 Eli Biham, Rafi Chen Antoine Joux, Patrick Carribault, Christophe Lemuet, and William Jalby Presnted by: Nael Masalha OUTLINE Neutral bits Multi-block technique Multi-block
High Accuracy Low g Inertial Sensor MEMS Sensing, State Machine ASIC
Freescale Semiconductor Data Sheet: Technical Data Document Number: Rev. 4, 03/2012 High Accuracy Low g Inertial Sensor MEMS Sensing, State Machine ASIC The, a SafeAssure solution, is a dual axis, Low
Dallas Semiconductor 17
2 3 8 11 Dallas Semiconductor 17 15 KEITHLEY MODEL 2304 6.0V, 750mA (SOURCE) A B KEITHLEY MODEL 2304 (LOAD) 150Ω 100Ω 4.7kΩ 1kΩ CC V IN 1400mAh Li-POLYMER CELL PC 100Ω DQ V DD 5.1V 0.1µF SNS V SS 0.1µF
New Coding System of Grid Squares in the Republic of Indonesia
September14, 2006 New Coding System of Grid Squares in the Republic of Indonesia Current coding system of grid squares in the Republic of Indonesia is based on similar
DS1742. Y2KC Nonvolatile Timekeeping RAM PIN CONFIGURATION
Y2KC Nonvolatile Timekeeping RAM FEATURES Integrated NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Circuit and Lithium Energy Source Clock Registers are Accessed Identically to the Static RAM;
Homework 3/ Solutions
MTH 310-3 Abstract Algebra I and Number Theory S17 Homework 3/ Solutions Exercise 1. Prove the following Theorem: Theorem Let R and S be rings. Define an addition and multiplication on R S by for all r,
S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques
![S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques](/thumbs/82/86792063.jpg "S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques")
S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 100 Q.1(a) Attempt any SIX of the following : [12]
Operating systems and concurrency B03
Operating systems and concurrency B03 David Kendall Northumbria University David Kendall (Northumbria University) Operating systems and concurrency B03 1 / 13 Introduction A key function of OS is interrupt
SANDWICH SETS AND CONGRUENCES IN COMPLETELY INVERSE AG -GROUPOIDS
ITALIAN JOURNAL OF PURE AND APPLIED MATHEMATICS N. 39 2018 (822 838) 822 SANDWICH SETS AND CONGRUENCES IN COMPLETELY INVERSE AG -GROUPOIDS Waqar Khan School of Mathematics and Statistics Southwest University
Neural Network Based Density Measurement
Bulg. J. Phys. 31 (2004) 163 169 P. Neelamegam 1, A. Rajendran 2 1 PG and Research Department of Physics, AVVM Sri Pushpam College (Autonomous), Poondi, Thanjavur, Tamil Nadu-613 503, India 2 PG and Research
Chapter 3 Trusses. Member CO Free-Body Diagram. The force in CO can be obtained by using section bb. Equations of Equilibrium.
Chapter 3 Trusses Procedure for analysis 1 Free body diagram: make a decision as to how to cut or section the truss through the members where forces are to be determined. 2 Equation of equilibrium: apply
* Note: If Vee varies from recommended value, you cannot get proper contrast or viewing angle.
Example of Power Supply (Except for DMC40401 Series) Normal Temperature Type Extended Temperature Type * Note: If ee varies from recommended value, you cannot get proper contrast or viewing angle. Examples
The Digital Logic Level
The Digital Logic Level Wolfgang Schreiner Research Institute for Symbolic Computation (RISC-Linz) Johannes Kepler University Wolfgang.Schreiner@risc.uni-linz.ac.at http://www.risc.uni-linz.ac.at/people/schreine
Applications of Finite Sets Jeremy Knight Final Oral Exam Texas A&M University March 29 th 2012
Finite Fields and Cryptography Applications of Finite Sets Jeremy Knight Final Oral Exam Texas A&M University March 29 th 2012 A field is a set that 1. is associative, commutative, and distributive for
Improved S-Box Construction from Binomial Power Functions
Malaysian Journal of Mathematical Sciences 9(S) June: 21-35 (2015) Special Issue: The 4 th International Cryptology and Information Security Conference 2014 (Cryptology 2014) MALAYSIAN JOURNAL OF MATHEMATICAL
Introduction to CMOS VLSI Design Lecture 1: Introduction
Introduction to CMOS VLSI Design Lecture 1: Introduction David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Introduction Integrated circuits: many transistors
Worksheets for GCSE Mathematics. Algebraic Expressions. Mr Black 's Maths Resources for Teachers GCSE 1-9. Algebra
Worksheets for GCSE Mathematics Algebraic Expressions Mr Black 's Maths Resources for Teachers GCSE 1-9 Algebra Algebraic Expressions Worksheets Contents Differentiated Independent Learning Worksheets
FPGA Resource Utilization Estimates for NI crio LabVIEW FPGA Version: 8.6 NI-RIO Version: 3.0 Date: 8/5/2008
FPGA Resource Utilization Estimates for NI crio-9104 LabVIEW FPGA Version: 8.6 NI-RIO Version: 3.0 Date: 8/5/2008 Note: The numbers presented in this document are estimates. Actual resource usage for your
Exam for Physics 4051, October 31, 2008
Exam for Physics 45, October, 8 5 points - closed book - calculators allowed - show your work Problem : (6 Points) The 4 bit shift register circuit shown in Figure has been initialized to contain the following
CMPE12 - Notes chapter 1. Digital Logic. (Textbook Chapter 3)
CMPE12 - Notes chapter 1 Digital Logic (Textbook Chapter 3) Transistor: Building Block of Computers Microprocessors contain TONS of transistors Intel Montecito (2005): 1.72 billion Intel Pentium 4 (2000):
COE 202: Digital Logic Design Sequential Circuits Part 4. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:
COE 202: Digital Logic Design Sequential Circuits Part 4 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Objectives Registers Counters Registers 0 1 n-1 A register is a group
The Future We Want: Stark Choices
ABC D EF B FB B FEFB FB B AF B D DB F F B B B B FCCF BACKGROUND The Future We Want: Stark Choices ABC DE FD FBC A FBC DE D A F FBC B A A E D AFD FD DE BF DE D DE AFBC FB DE A F F DB D B A A E NBSAP development
Number Systems 1(Solutions for Vol 1_Classroom Practice Questions)
Chapter Number Systems (Solutions for Vol _Classroom Practice Questions). ns: (d) 5 x + 44 x = x ( x + x + 5 x )+( x +4 x + 4 x ) = x + x + x x +x+5+x +4x+4 = x + x + x 5x 6 = (x6) (x+ ) = (ase cannot
Chapter 1 Problem Solving: Strategies and Principles
Chapter 1 Problem Solving: Strategies and Principles Section 1.1 Problem Solving 1. Understand the problem, devise a plan, carry out your plan, check your answer. 3. Answers will vary. 5. How to Solve
Selma City Schools Curriculum Pacing Guide Grades Subject: Algebra II Effective Year:
Selma City Schools Curriculum Pacing Guide Grades 9-12 Subject: Algebra II Effective Year: 2013-14 Nine 1 Nine 2 Nine 3 Nine 4 X X Time CC COS QC Literacy DOK Lesson References/Activities Date Taught Test
CHW 261: Logic Design
CHW 26: Logic Design Instructors: Prof. Hala Zayed Dr. Ahmed Shalaby http://www.bu.edu.eg/staff/halazayed4 http://bu.edu.eg/staff/ahmedshalaby4# Slide Digital Fundamentals Digital Concepts Slide 2 What?
L institution sportive : rêve et illusion
L institution sportive : rêve et illusion Hafsi Bedhioufi, Sida Ayachi, Imen Ben Amar To cite this version: Hafsi Bedhioufi, Sida Ayachi, Imen Ben Amar. L institution sportive : rêve et illusion. Revue