Lecture Notes. EECS 40 Introduction to Microelectronic Circuits. Prof. C. Chang-Hasnain Spring 2007

Transcription

1 Lecture Notes EES 4 Introduction to Microelectronic ircuits Prof.. hanghasnain Spring 7

2 EE 4 ourse Oeriew EES 4: One of fie EES core courses (with, 6, 6, and 6) introduces hardware side of EES prerequisite for EE5, EE3, EE4, EE5 Prerequisites: Math, Physics 7 ourse inoles three hours of lecture, one hour of discussion and three hours of lab work each week. ourse content: Fundamental circuit concepts and analysis techniques First and second order circuits, impulse and frequency response Op mps Diode and FET: Deice and ircuits mplification, Logic, Filter Text ook Electrical Engineering: Principles and pplications, third edition, llan. Hambley, Pearson Prentice Hall, 5 Supplementary eader Important DTES Office hours, Discussion and Lab Sessions will start on week Stay with ONE Discussion and Lab session you registered. Midterm and Final Dates: Midterms: 67:4 pm on / and 4/(Location TD) Final: 8am on 5/4 (Location TD) est Final Project ontest 5/4 35pm Location TD Winner projects will be displayed on second floor ory Hall. Slide Slide Grading Policy Weights: %: HW sets 5%: Labs 7 structured experiments (7%) one 4week final project (8%) 4%: midterm exams 33%: Final exam No late HW or Lab reports accepted No makeup exams unless Prof. hang s approal is obtained at least 4 hours before exam time; proofs of extraneous circumstances are required. If you miss one of the midterms, you lose % of the grade. Departmental grading policy: typical GP for courses in the lower diision is.7. This GP would result, for example, from 7% 's, 5% 's, % 's, % D's, and 3% F's. Grading Policy (ont d) Weekly HW: ssignment on the web by 5 pm Wednesdays, starting /4/7. Due 5 pm the following Wednesday in HW box, 4 ory. On the top page, right top corner, write your name (in the form: Last Name, First Name) with discussion session number. Graded homework will be returned one week later in discussion sessions. Labs omplete the prelab section before going to the lab, or your points will be taken off. Lab reports are supposed to be turned in at the end of each lab, except for the final project, which is due at the end of the last lab session. It is your responsibility to check with the head GSI from time to time to make sure all grades are entered correctly. Slide 3 Slide 4

3 lassroom ules Please come to class on time. There is no webcast this semester. Turn off cell phones, pagers, radio, D, DD, etc. No food. No pets. Do not come in and out of classroom. Lectures will be recorded and webcasted. Outline hapter Electrical quantities harge, urrent, oltage, Power The ideal basic circuit element Sign conentions ircuit element I characteristics onstruction of a circuit model Kirchhoff s urrent Law Kirchhoff s oltage Law Slide 5 Slide 6 Electric harge lassification of Materials Electrical effects are due to separation of charge electric force (oltage) charges in motion electric flow (current) Macroscopically, most matter is electrically neutral most of the time. Exceptions: clouds in a thunderstorm, people on carpets in dry weather, plates of a charged capacitor, etc. Microscopically, matter is full of electric charges Electric charge exists in discrete quantities, integral multiples of the electronic charge.6 x 9 oulomb Solids in which the outermost atomic electrons are free to moe around are metals. Metals typically hae ~ free electron per atom Examples: Solids in which all electrons are tightly bound to atoms are insulators. Examples: Electrons in semiconductors are not tightly bound and can be easily promoted to a free state. Examples: Slide 7 Slide 8

4 Electric urrent Definition: rate of positie charge flow Symbol: i Units: oulombs per second mperes () Note: urrent has polarity. i dq/dt where q charge (oulombs) t time (in seconds) ndrémarie mpère's Slide 9 Slide Electric urrent Examples. 5 positiely charged particles (each with charge.6 9 ) flow to the right (x direction) eery nanosecond 5 9 Q.6 5 I.6 9 t. 5 electrons flow to the right (x direction) eery microsecond 5 9 Q.6 I.6 9 t 5 Example : cm urrent Density Definition: rate of positie charge flow per unit area Symbol: J Units: / cm Wire attached to end cm cm Suppose we force a current of to flow from to : Electron flow is in x direction: / sec / electron 8 X Semiconductor with 8 free electrons per cm 3 electrons sec Slide Slide

5 urrent Density Example (cont d) Example : Typical dimensions of integrated circuit components are in the range of µm. What is the current density in a wire with µm² area carrying 5 m? Electric Potential (oltage) Definition: energy per unit charge Symbol: Units: Joules/oulomb olts () dw/dq lessandro olta (74587) where w energy (in Joules), q charge (in oulombs) Note: Potential is always referenced to some point. a b Subscript conention: ab means the potential at a minus the potential at b. ab a b Slide 3 Slide 4 Electric Power Definition: transfer of energy per unit time Symbol: p Units: Joules per second Watts (W) p dw/dt (dw/dq)(dq/dt) i _ The Ideal asic ircuit Element i Polarity reference for oltage can be indicated by plus and minus signs eference direction for the current is indicated by an arrow oncept: s a positie charge q moes through a drop in oltage, it loses energy energy change q rate is proportional to # charges/sec James Watt ttributes: Two terminals (points of connection) Mathematically described in terms of current and/or oltage annot be subdiided into other elements Slide 5 Slide 6

6 Note about eference Directions problem like Find the current or Find the oltage is always accompanied by a definition of the direction: i In this case, if the current turns out to be m flowing to the left, we would say i m. In order to perform circuit analysis to determine the oltages and currents in an electric circuit, you need to specify reference directions. There is no need to guess the reference direction so that the answers come out positie. Suppose you hae an unlabelled battery and you measure its oltage with a digital oltmeter (DM). It will tell you the magnitude and sign of the oltage. a b Sign onention Example.4 DM With this circuit, you are measuring ab. The DM indicates.4, so a is lower than b by.4. Which is the positie battery terminal? Note that we hae used the ground symbol ( ) for the reference node on the DM. Often it is labeled for common. Slide 7 Slide 8 nother Example Sign onention for Power Find ab, ca, cb a b bd c cd d Passie sign conention _ i p i _ i _ i p i _ i Note that the labeling conention has nothing to do with whether or not is positie or negatie. If p >, power is being deliered to the box. If p <, power is being extracted from the box. Slide 9 Slide

7 Power If an element is absorbing power (i.e. if p > ), positie charge is flowing from higher potential to lower potential. p i if the passie sign conention is used: i i _ How can a circuit element absorb power? or y conerting electrical energy into heat (resistors in toasters), light (light bulbs), or acoustic energy (speakers); by storing energy (charging a battery). _ Power alculation Example Find the power absorbed by each element: onseration of energy total power deliered equals total power absorbed side: For electronics these are unrealistically large currents milliamperes or smaller is more typical i (W) p (W) Slide Slide ircuit Elements 5 ideal basic circuit elements: oltage source current source resistor inductor capacitor actie elements, capable of generating electric energy passie elements, incapable of generating electric energy Many practical systems can be modeled with just sources and resistors The basic analytical techniques for soling circuits with inductors and capacitors are similar to those for resistie circuits Electrical Sources n electrical source is a deice that is capable of conerting nonelectric energy to electric energy and ice ersa. Examples: battery: chemical electric dynamo (generator/motor): mechanical electric (Ex. gasolinepowered generator, onneille dam) Electrical sources can either delier or absorb power Slide 3 Slide 4

8 Ideal oltage Source ircuit element that maintains a prescribed oltage across its terminals, regardless of the current flowing in those terminals. oltage is known, but current is determined by the circuit to which the source is connected. The oltage can be either independent or dependent on a oltage or current elsewhere in the circuit, and can be constant or timearying. Deice symbols: Ideal urrent Source ircuit element that maintains a prescribed current through its terminals, regardless of the oltage across those terminals. urrent is known, but oltage is determined by the circuit to which the source is connected. The current can be either independent or dependent on a oltage or current elsewhere in the circuit, and can be constant or timearying. Deice symbols: s _ s µ x _ s ρ i x _ i s i s α x i s β i x independent oltagecontrolled currentcontrolled Slide 5 independent oltagecontrolled currentcontrolled Slide 6 Electrical esistance esistance: the ratio of oltage drop and current. The circuit element used to model this behaior is the resistor. ircuit symbol: Units: olts per mpere ohms (Ω) The current flowing in the resistor is proportional to the oltage across the resistor: i (Ohm s Law) where oltage (), i current (), and resistance (Ω) Georg Simon Ohm Electrical onductance onductance is the reciprocal of resistance. Symbol: G Units: siemens (S) or mhos ( ) Example: onsider an 8 Ω resistor. What is its conductance? Werner on Siemens 8689 Ω Slide 7 Slide 8

9 Short ircuit and Open ircuit Short circuit no oltage difference exists all points on the wire are at the same potential. urrent can flow, as determined by the circuit Open circuit no current flows oltage difference can exist, as determined by the circuit Example: Power bsorbed by a esistor p i ( i )i i p i ( / ) / Note that p > always, for a resistor a resistor dissipates electric energy Example: a) alculate the oltage g and current i a. b) Determine the power dissipated in the 8Ω resistor. Slide 9 Slide 3 More Examples Summary re these interconnections permissible? This circuit connection is permissible. This is because the current sources can sustain any oltage across; Hence this is permissible. This circuit connection is NOT permissible. It iolates the KL. urrent rate of charge flow i dq/dt oltage energy per unit charge created by charge separation Power energy per unit time Ideal asic ircuit Elements twoterminal component that cannot be subdiided described mathematically in terms of its terminal oltage and current n ideal oltage source maintains a prescribed oltage regardless of the current in the deice. n ideal current source maintains a prescribed current regardless of the oltage across the deice. resistor constrains its oltage and current to be proportional to each other: i (Ohm s law) Slide 3 Slide 3

10 Summary (cont d) Passie sign conention For a passie deice, the reference direction for current through the element is in the direction of the reference oltage drop across the element urrent s. oltage (I) haracteristic oltage sources, current sources, and resistors can be described by plotting the current (i) as a function of the oltage () _ i Passie? ctie? Slide 33 Slide 34 I haracteristic of Ideal oltage Source a ab _ b i _ s i i s > I haracteristic of Ideal oltage Source a ab _ b i _ s s < i. Plot the I characteristic for s >. For what alues of i does the source absorb power? For what alues of i does the source release power?. epeat s > () i< for release s <. power; i> absorb power 3. What is the I characteristic for an ideal wire?. Plot the I characteristic for s <. For what alues of i does the source absorb power? For what alues of i does the source release power? s < i> release power; i< absorb power Slide 35 Slide 36

11 I haracteristic of Ideal oltage Source I haracteristic of Ideal urrent Source a i i i i ab s _ i s b 3. What is the I characteristic for an ideal wire? Do not forget ab ba. Plot the I characteristic for i s >. For what alues of does the source absorb power? For what alues of does the source release power? > absorb power; < release power Slide 37 Slide 38 Short ircuit and Open ircuit Wire ( short circuit ): no oltage difference exists (all points on the wire are at the same potential) urrent can flow, as determined by the circuit ir ( open circuit ): no current flows oltage difference can exist, as determined by the circuit a _ b I haracteristic of Ideal esistor i. Plot the I characteristic for kω. What is the slope? a ab _ ab a i b b Slide 39 Slide 4

12 More Examples: orrection from last Lec. re these interconnections permissible? This circuit connection is permissible. This is because the current sources can sustain any oltage across; Hence this is permissible. onstruction of a ircuit Model The electrical behaior of each physical component is of primary interest. We need to account for undesired as well as desired electrical effects. This circuit connection is NOT permissible. It iolates the KL. Simplifying assumptions should be made whereer reasonable. Slide 4 Slide 4 Terminology: Nodes and ranches Node: point where two or more circuit elements are connected ircuit Nodes and Loops node is a point where two or more circuit elements are connected. loop is formed by tracing a closed path in a circuit through selected basic circuit elements without passing through any intermediate node more than once ranch: path that connects two nodes Slide 43 Slide 44

13 Kirchhoff s Laws Kirchhoff s urrent Law (KL): The algebraic sum of all the currents entering any node in a circuit equals zero. Kirchhoff s oltage Law (KL): The algebraic sum of all the oltages around any loop in a circuit equals zero. Slide 45 Gusta obert Kirchhoff Notation: Node and ranch oltages Use one node as the reference (the common or ground node) label it with a symbol The oltage drop from node x to the reference node is called the node oltage x. The oltage across a circuit element is defined as the difference between the node oltages at its terminals Example: a b a c s Slide 46 b _ EFEENE NODE Using Kirchhoff s urrent Law (KL) onsider a node connecting seeral branches: i i 3 Formulations of Kirchhoff s urrent Law Formulation : (harge stored in node is zero.) Sum of currents entering node sum of currents leaing node i i 4 Formulation : lgebraic sum of currents entering node urrents leaing are included with a minus sign. Use reference directions to determine whether currents are entering or leaing the node with no concern about actual current directions Slide 47 Formulation 3: lgebraic sum of currents leaing node urrents entering are included with a minus sign. Slide 48

14 Major Implication of KL KL Example KL tells us that all of the elements in a single branch carry the same current. We say these elements are connected in series. m i urrents entering the node: 5 m urrents leaing the node: 5 m urrent entering node urrent leaing node i i 3 formulations of KL:.. 3. Slide 49 Slide 5 Generalization of KL Generalized KL Examples The sum of currents entering/leaing a closed surface is zero. ircuit branches can be inside this surface, i.e. the surface can enclose more than one node! i i 3 5 m 5µ µ i This could be a big chunk of a circuit, e.g. a black box i i 4 i Slide 5 Slide 5

15 Use reference polarities to determine whether a oltage is dropped No concern about actual oltage polarities Using Kirchhoff s oltage Law (KL) onsider a branch which forms part of a loop: loop _ Moing from to We add Slide 53 loop Moing from to We subtract Formulations of Kirchhoff s oltage Law (onseration of energy) Formulation : Sum of oltage drops around loop sum of oltage rises around loop Formulation : lgebraic sum of oltage drops around loop oltage rises are included with a minus sign. (Handy trick: Look at the first sign you encounter on each element when tracing the loop.) Formulation 3: lgebraic sum of oltage rises around loop oltage drops are included with a minus sign. Slide 54 Major Implication of KL KL tells us that any set of elements which are connected at both ends carry the same oltage. We say these elements are connected in parallel. a_ b _ pplying KL in the clockwise direction, starting at the top: b a b a Three closed paths: Path : Path : Path 3: KL Example a 3 a b c b 3 c Slide 55 Slide 56

16 n Underlying ssumption of KL I haracteristic of Elements No timearying magnetic flux through the loop Otherwise, there would be an induced oltage (Faraday s Law) Note: ntennas are designed to pick up electromagnetic waes; regular circuits often do so undesirably. (t) a ab _ b i _ s Find the I characteristic. i oid these loops! (t) How do we deal with antennas (EES 7)? Include a oltage source as the circuit representation of the induced oltage or noise. (Use a lumped model rather than a distributed (wae) model.) Slide 57 Slide 58 Summary hapter n electrical system can be modeled by an electric circuit (combination of paths, each containing or more circuit elements) Lumped model The urrent ersus oltage characteristics (I plot) is a uniersal means of describing a circuit element. Kirchhoff s current law (KL) states that the algebraic sum of all currents at any node in a circuit equals zero. omes from conseration of charge Kirchhoff s oltage law (KL) states that the algebraic sum of all oltages around any closed path in a circuit equals zero. omes from conseration of potential energy Outline esistors in Series oltage Diider onductances in Parallel urrent Diider Nodeoltage nalysis Meshurrent nalysis Superposition Théenin equialent circuits Norton equialent circuits Maximum Power Transfer Slide 59 Slide 6

17 esistors in Series oltage Diider onsider a circuit with multiple resistors connected in series. Find their equialent resistance. SS I 3 KL tells us that the same current (I) flows through eery resistor KL tells us SS I I SS / ( 3 4 ) 4 Equialent resistance of resistors in series is the sum Slide 6 Slide 6 When can the oltage Diider Formula be Used? SS I 3 4 SS I I SS esistors in Parallel onsider a circuit with two resistors connected in parallel. Find their equialent resistance. I x I KL tells us that the same oltage is dropped across each resistor x I I KL tells us SS 3 4 SS 3 4 orrect, if nothing else is connected to nodes Why? What is? Slide 63 Slide 64

18 General Formula for Parallel esistors What single resistance eq is equialent to three resistors in parallel? urrent Diider x I I I I 3 eq eq I SS x I I SS eq Equialent conductance of resistors in parallel is the sum Slide 65 Slide 66 I I 3 Generalized urrent Diider Formula onsider a current diider circuit with > resistors in parallel: 3 I I / I / / 3 I3 / 3 3 I 3 Measuring oltage To measure the oltage drop across an element in a real circuit, insert a oltmeter (digital multimeter in oltage mode) in parallel with the element. oltmeters are characterized by their oltmeter input resistance ( in ). Ideally, this should be ery high (typical alue MΩ) Ideal oltmeter in Slide 67 Slide 68

19 SS ompare to SS in SS in Example: SS, K, 9K M,? in Effect of oltmeter undisturbed circuit circuit with oltmeter inserted _ SS _ in Measuring urrent To measure the current flowing through an element in a real circuit, insert an ammeter (digital multimeter in current mode) in series with the element. mmeters are characterized by their ammeter input resistance ( in ). Ideally, this should be ery low (typical alue Ω). Ideal mmeter in Slide 69 Slide 7 undisturbed circuit _ I I Effect of mmeter Measurement error due to nonzero input resistance: circuit with ammeter inserted Slide 7 I meas Example:, 5 Ω, in Ω I m, Imeas? 5Ω 5Ω _ in I meas in ammeter ompare to Simplify a circuit before applying KL and/or KL: Example: Find I 7 Using Equialent esistances I Slide 7 3 kω 3 6 kω kω 6 kω

20 Nodeoltage ircuit nalysis Method. hoose a reference node ( ground ) Look for the one with the most connections!. Define unknown node oltages those which are not fixed by oltage sources 3. Write KL at each unknown node, expressing current in terms of the node oltages (using the I relationships of branch elements) Special cases: floating oltage sources 4. Sole the set of independent equations N equations for N unknown node oltages Nodal nalysis: Example #. hoose a reference node.. Define the node oltages (except reference node and the one set by the oltage source). 3. pply KL at the nodes with unknown oltage. 3 I S 4. Sole for unknown node oltages. 4 Slide 73 Slide 74 Nodal nalysis: Example # 3 I a 5 4 Nodal nalysis w/ Floating oltage Source floating oltage source is one for which neither side is connected to the reference node, e.g. LL in the circuit below: a LL b I 4 I hallenges: Determine number of nodes needed Deal with different types of sources Slide 75 Problem: We cannot write KL at nodes a or b because there is no way to express the current through the oltage source in terms of a b. Solution: Define a supernode that chunk of the circuit containing nodes a and b. Express KL for this supernode. Incorporate oltage source constraint into KL equation. Slide 76

21 Nodal nalysis: Example #3 I Eq n : KL at supernode supernode 4 I Substitute property of oltage source: a LL Slide 77 b Formal ircuit nalysis Methods NODL NLYSIS ( Nodeoltage Method ) ) hoose a reference node ) Define unknown node oltages ) pply KL to each unknown node, expressing current in terms of the node oltages > N equations for N unknown node oltages 3) Sole for node oltages > determine branch currents Slide 78 MESH NLYSIS ( Meshurrent Method ) ) Select M independent mesh currents such that at least one mesh current passes through each branch* M #branches #nodes ) pply KL to each mesh, expressing oltages in terms of mesh currents > M equations for M unknown mesh currents 3) Sole for mesh currents > determine node oltages *Simple method for planar circuits mesh current is not necessarily identified with a branch current. Mesh nalysis: Example # Mesh nalysis with a urrent Source i a i b. Select M mesh currents.. pply KL to each mesh. 3. Sole for mesh currents. Problem: We cannot write KL for meshes a and b because there is no way to express the oltage drop across the current source in terms of the mesh currents. Solution: Define a supermesh a mesh which aoids the branch containing the current source. pply KL for this supermesh. Slide 79 Slide 8

22 Mesh nalysis: Example # i a i b Eq n : KL for supermesh Eq n : onstraint due to current source: Mesh nalysis with Dependent Sources Exactly analogous to Node nalysis Dependent oltage Source: () Formulate and write KL mesh eqns. () Include and express dependency constraint in terms of mesh currents Dependent urrent Source: () Use supermesh. () Include and express dependency constraint in terms of mesh currents Slide 8 Slide 8 ircuit w/ Dependent Source Example Find i, i and i o Superposition linear circuit is one constructed only of linear elements (linear resistors, and linear capacitors and inductors, linear dependent sources) and independent sources. Linear means I charcteristic of elements/sources are straight lines when plotted Principle of Superposition: In any linear circuit containing multiple independent sources, the current or oltage at any point in the network may be calculated as the algebraic sum of the indiidual contributions of each source acting alone. Slide 83 Slide 84

23 Source ombinations oltage sources in series can be replaced by an equialent oltage source: urrent sources in parallel can be replaced by an equialent current source: Superposition Procedure:. Determine contribution due to one independent source Set all other sources to : eplace independent oltage source by short circuit, independent current source by open circuit. epeat for each independent source 3. Sum indiidual contributions to obtain desired oltage or current i i i i Slide 85 Slide 86 Open ircuit and Short ircuit Open circuit i ; ut off the branch Short circuit ; replace the element by wire Turn off an independent oltage source means eplace by wire Short circuit Turn off an independent current source means i ut off the branch open circuit Find o 4 Superposition Example Ω Ω o Slide 87 Slide 88

24 Equialent ircuit oncept network of oltage sources, current sources, and resistors can be replaced by an equialent circuit which has identical terminal properties (I characteristics) without affecting the operation of the rest of the circuit. Théenin Equialent ircuit ny* linear terminal (port) network of indep. oltage sources, indep. current sources, and linear resistors can be replaced by an equialent circuit consisting of an independent oltage source in series with a resistor without affecting the operation of the rest of the circuit. i i Théenin equialent circuit network of sources and resistors _ i ( ) i ( ) network of sources and resistors _ network of sources and resistors a b L i L L Th Th a b L i L L load resistor Slide 89 Slide 9 I haracteristic of Théenin Equialent The I characteristic for the series combination of elements is obtained by adding their oltage drops: Théenin Equialent Example Find the Theenin equialent with respect to the terminals a,b: For a gien current i, the oltage drop ab is equal to the sum of the oltages dropped across the source ( Th ) and across the resistor (i Th ) Th i a i ab Th i Th ab I characteristic of resistor: i b I characteristic of oltage source: Th Slide 9 Slide 9

25 Th alculation Example # Norton Equialent ircuit ny* linear terminal (port) network of indep. oltage sources, indep. current sources, and linear resistors can be replaced by an equialent circuit consisting of an independent current source in parallel with a resistor without affecting the operation of the rest of the circuit. Set all independent sources to : network of sources and resistors a b L i L L Norton equialent circuit i N N a b L i L L Slide 93 Slide 94 I haracteristic of Norton Equialent The I characteristic for the parallel combination of elements is obtained by adding their currents: For a gien oltage ab, the current i is equal to the sum of the currents in each of the two branches: i N N a ab b i I characteristic of resistor: ig i I characteristic of current source: i I N i I N G Finding I N and N Th nalogous to calculation of Theenin Eq. kt: ) Find o.c oltage and s.c. current I N i sc Th / Th ) Or, find s.c. current and Norton (The) resistance Slide 95 Slide 96

26 Finding I N and N We can derie the Norton equialent circuit from a Théenin equialent circuit simply by making a source transformation: Th Th a b L i L L i N N N Th i i oc Th ; N isc sc Th a b L i L L Th Maximum Power Transfer Theorem Théenin equialent circuit dp dl Th L i L L p i ( Th L ) L ( Th L ) Th 4 ( Th L ) ( ) ( ) Th Th L L Power absorbed by load resistor: L L Th L resistie load receies maximum power from a circuit if the load resistance equals the Théenin resistance of the circuit. L Th Th dp To find the alue of L for which p is maximum, set to : d L L L Slide 97 Slide 98 The Wheatstone ridge ircuit used to precisely measure resistances in the range from Ω to MΩ, with ±.% accuracy and are resistors with known alues 3 is a ariable resistor (typically to,ω) x is the resistor whose alue is to be measured Finding the alue of x djust 3 until there is no current in the detector Then, x 3 Deriation: battery ariable resistor 3 x current detector i i 3 i 3 x Typically, / can be aried from. to in decimal steps i x Slide 99 Slide

27 Finding the alue of x djust 3 until there is no current in the detector Then, x 3 KL > Deriation: i i 3 and i i x Identifying Series and Parallel ombinations Some circuits must be analyzed (not amenable to simple inspection) I 4 3 i i i 3 i x 3 x KL > i 3 3 i x x and i i i 3 i x Special cases: 3 O 3 5 Typically, / can be aried from. to in decimal steps 3 x Slide Slide YDelta onersion These two resistie circuits are equialent for oltages and currents external to the Y and circuits. Internally, the oltages and currents are different. a c b a b DeltatoWye (PitoTee) Equialent ircuits In order for the Delta interconnection to be equialent to the Wye interconnection, the resistance between corresponding terminal pairs must be the same a b c a b c ( a b ) ab a b c b c a c 3 a c b a ( b c ) bc 3 a b c b c a b c a c a b c 3 a b a b c rain Teaser ategory: Important for motors and electrical utilities. c 3 b ( a c ) ca 3 a b c Slide 3 Slide 4

28 Y and Y onersion Formulas ircuit Simplification Example DeltatoWye conersion WyetoDelta conersion Find the equialent resistance ab : Ω Ω a a b c a b c a c b a 3 3 8Ω 6Ω Ω 3 a c a b c a b a b c a b a c b b 3 3 c b 9Ω 4Ω b 9Ω 4Ω 3 c Slide 5 Slide 6 Dependent Sources Nodeoltage Method Dependent current source: treat as independent current source in organizing node eqns substitute constraining dependency in terms of defined node oltages. Dependent oltage source: treat as independent oltage source in organizing node eqns Substitute constraining dependency in terms of defined node oltages. Mesh nalysis Dependent oltage Source: Formulate and write KL mesh eqns. Include and express dependency constraint in terms of mesh currents Dependent urrent Source: Use supermesh. Include and express dependency constraint in terms of mesh currents Slide 7 omments on Dependent Sources dependent source establishes a oltage or current whose alue depends on the alue of a oltage or current at a specified location in the circuit. (deice model, used to model behaior of transistors & amplifiers) To specify a dependent source, we must identify:. the controlling oltage or current (must be calculated, in general). the relationship between the controlling oltage or current and the supplied oltage or current 3. the reference direction for the supplied oltage or current The relationship between the dependent source and its reference cannot be broken! Dependent sources cannot be turned off for arious purposes (e.g. to find the Théenin resistance, or in analysis using Superposition). Slide 8

29 Nodeoltage Method and Dependent Sources If a circuit contains dependent sources, what to do? Th alculation Example # Find the Theenin equialent with respect to the terminals a,b: Example: i I x.4 Ω Ω Ω 5i 8 x Since there is no independent source and we cannot arbitrarily turn off the dependence source, we can add a oltage source x across terminals ab and measure the current through this terminal I x. th x / I x Slide 9 Slide ircuit w/ Dependent Source Example Find i, i and i o Summary of Techniques for ircuit nalysis (hap ) esistor network Parallel resistors Series resistors Ydelta conersion dd current source and find oltage (or ice ersa) Superposition Leae one independent source on at a time Sum oer all responses oltage off S urrent off O Slide Slide

30 Summary of Techniques for ircuit nalysis (hap ) Node nalysis Node oltage is the unknown Sole for KL Floating oltage source using super node Mesh nalysis Loop current is the unknown Sole for KL urrent source using super mesh Theenin and Norton Equialent ircuits Sole for O oltage Sole for S current Outline The capacitor The inductor hapter 3 Slide 3 Slide 4 The apacitor apacitor Two conductors (a,b) separated by an insulator: difference in potential ab > equal & opposite charge Q on conductors Q ab where is the capacitance of the structure, positie () charge is on the conductor at higher potential Parallelplate capacitor: area of the plates (m ) separation between plates d (m) dielectric permittiity of insulator ε (F/m) ε F(F) > capacitance d Slide 5 (stored charge in terms of oltage) Symbol: Units: Farads (oulombs/olt) or (typical range of alues: pf to µf; for supercapacitors up to a few F!) urrentoltage relationship: i dq dt d dt c c c d dt If (geometry) is unchanging, i d /dt Note: Q ( c ) must be a continuous function of time Slide 6 i c Electrolytic (polarized) capacitor c

31 oltage in Terms of urrent Stored Energy Q( t) t c c ( t) i ( t) dt Q() t Q() ic ( t) dt t i ( t) dt () c c PITOS STOE ELETI ENEGY You might think the energy stored on a capacitor is Q, which has the dimension of Joules. ut during charging, the aerage oltage across the capacitor was only half the final alue of for a linear capacitor. Q Thus, energy is. Uses: apacitors are used to store energy for camera flashbulbs, in filters that separate arious frequency signals, and they appear as undesired parasitic elements in circuits where they usually degrade circuit performance Example: pf capacitance charged to 5 olts has ½(5) (pf).5 pj ( 5F supercapacitor charged to 5 olts stores 63 J; if it discharged at a constant rate in ms energy is discharged at a 63 kw rate!) Slide 7 Slide 8 t t w t t Final Initial w more rigorous deriation This deriation holds independent of the circuit! Final c Initial c i c d c dt Final Final c Initial dq dt dt Initial Final c Initial i c dq c Example: urrent, Power & Energy for a apacitor () i (µ) ( t) i( ) d () τ τ d i dt t t (µs) t (µs) (t) µf i(t) c and q must be continuous functions of time; howeer, i c can be discontinuous. Note: In steady state (dc operation), time deriaties are zero is an open circuit Slide 9 Slide

32 apacitors in Series p (W) i(t) (t) (t) t (µs) (t) µf i(t) i(t) eq (t) (t) (t) p i w (J) t (µs) t w pd τ eq Slide Slide apacitie oltage Diider Q: Suppose the oltage applied across a series combination of capacitors is changed by. How will this affect the oltage across each indiidual capacitor? Q Q Q Q Q Slide 3 Note that no net charge can can be introduced to this node. Therefore, Q Q Q Q (t) Q Q Q Note: apacitors in series hae the same incremental charge. Symbol: Inductor Units: Henrys (olts second / mpere) urrent in terms of oltage: di i L L L L t t ( t) dt ( t) L ( τ ) dτ i( t) L L (typical range of alues: µh to H) Note: i L must be a continuous function of time Slide 4 i L L

33 Stored Energy INDUTOS STOE MGNETI ENEGY onsider an inductor haing an initial current i(t ) i p( t) ( t) i( t) Inductors in Series and Parallel ommon urrent w( t) w( t) t t p( τ ) dτ Li Li ommon oltage Slide 5 Slide 6 apacitor Inductor d di i ; w L ; w Li dt dt cannot change instantaneously i can change instantaneously Do not shortcircuit a charged capacitor (> infinite current!) n cap. s in series: n cap. s in parallel: i i In steady state (not timearying), a capacitor behaes like an open circuit. eq eq n n Summary i i i cannot change instantaneously can change instantaneously Do not opencircuit an inductor with current (> infinite oltage!) n ind. s in series: n ind. s in parallel: In steady state, an inductor behaes like a short circuit. Slide 7 L eq L eq n i n i L i L i hapter 4 OUTLINE First Order ircuits and L Examples General Procedure and L ircuits with General Sources Particular and complementary solutions Time constant Second Order ircuits The differential equation Particular and complementary solutions The natural frequency and the damping ratio eading hapter 4 Slide 8

34 s FirstOrder ircuits circuit that contains only sources, resistors and an inductor is called an L circuit. circuit that contains only sources, resistors and a capacitor is called an circuit. L and circuits are called firstorder circuits because their oltages and currents are described by firstorder differential equations. i L s i esponse of a ircuit Transient response of an L or circuit is ehaior when oltage or current source are suddenly applied to or remoed from the circuit due to switching. Temporary behaior Steadystate response (aka. forced response) esponse that persists long after transient has decayed Natural response of an L or circuit is ehaior (i.e., current and oltage) when stored energy in the inductor or capacitor is released to the resistie part of the network (containing no independent sources). Slide 9 Slide 3 Natural esponse Summary First Order ircuits L ircuit i L ircuit s (t) r (t) i c (t) c(t) i s (t) L i L (t) L (t) Inductor current cannot change instantaneously In steady state, an inductor behaes like a short circuit. apacitor oltage cannot change instantaneously In steady state, a capacitor behaes like an open circuit KL around the loop: r (t) c (t) s (t) dc ( t) c ( t) s ( t) dt KL at the node: t ( t) ( x) dx i L L dil ( t) il ( t) is ( t) dt s ( t) Slide 3 Slide 3

35 Procedure for Finding Transient esponse. Identify the ariable of interest For L circuits, it is usually the inductor current i L (t) For circuits, it is usually the capacitor oltage c (t). Determine the initial alue (at t t and t ) of the ariable ecall that i L (t) and c (t) are continuous ariables: i L (t ) i L (t ) and c (t ) c (t ) ssuming that the circuit reached steady state before t, use the fact that an inductor behaes like a short circuit in steady state or that a capacitor behaes like an open circuit in steady state Procedure (cont d) 3. alculate the final alue of the ariable (its alue as t ) gain, make use of the fact that an inductor behaes like a short circuit in steady state (t ) or that a capacitor behaes like an open circuit in steady state (t ) 4. alculate the time constant for the circuit τ L/ for an L circuit, where is the Théenin equialent resistance seen by the inductor τ for an circuit where is the Théenin equialent resistance seen by the capacitor Slide 33 Slide 34 Natural esponse of an ircuit Soling for the oltage (t ) onsider the following circuit, for which the switch is closed for t <, and then opened at t : For t >, the circuit reduces to i o o t o Notation: is used to denote the time just prior to switching is used to denote the time immediately after switching o pplying KL to the circuit: The oltage on the capacitor at t is o Solution: ( t) () e t / Slide 35 Slide 36

36 Soling for the urrent (t > ) Soling for Power and Energy Deliered (t > ) o Note that the current changes abruptly: i( ) for o o t >, i( t) e o i( ) i Slide 37 t / t e t / ( ) o o p w t o o e p( x) dx o t / t o e t / ( e ) x / i dx Slide 38 t e t / ( ) o Natural esponse of an L ircuit onsider the following circuit, for which the switch is closed for t <, and then opened at t : I o o t i Notation: is used to denote the time just prior to switching is used to denote the time immediately after switching t< the entire system is at steadystate; and the inductor is like short circuit The current flowing in the inductor at t is I o and across is. L Soling for the urrent (t ) For t >, the circuit reduces to I o pplying KL to the L circuit: (t)i(t) t t, ii, t arbitrary t>, ii(t) and ( t) Solution: o i( t) i() e L ( / L) t di( t) L dt i I e (/L)t Slide 39 Slide 4

37 I o Soling for the oltage (t > ) o Note that the oltage changes abruptly: ( ) for t >, ( t) i I ( ) I o Slide 4 L e i( t) I o e ( / L) t ( / L) t Soling for Power and Energy Deliered (t > ) p i w t I o I o o e p( x) dx LI ( / L) t t I o e o ( / L) t ( e ) ( / L) x Slide 4 L dx i t I e ( / L) t ( ) o L Natural esponse Summary L ircuit Inductor current cannot change instantaneously i( ) i( i( t) i() e time constant i ) t /τ τ L Slide 43 ircuit apacitor oltage cannot change instantaneously ( time constant ) ( ( t) () e ) t /τ τ We compute with pulses. We send beautiful pulses in: ut we receie lousylooking pulses at the output: Eery node in a real circuit has capacitance; it s the charging of these capacitances that limits circuit performance (speed) Digital Signals apacitor charging effects are responsible! Slide 44 oltage oltage time time

38 ircuit Model for a Logic Gate Pulse Distortion ecall (from Lecture ) that electronic building blocks referred to as logic gates are used to implement logical functions (NND, NO, NOT) in digital Is ny logical function can be implemented using these gates. logic gate can be modeled as a simple circuit: in (t) out The input oltage pulse width must be large enough; otherwise the output pulse is distorted. (We need to wait for the output to reach a recognizable logic leel, before changing the input again.) in (t) switches between low (logic ) and high (logic ) oltage states out Time out Pulse width Time out Pulse width out Pulse width Time Slide 45 Slide 46 Example Suppose a oltage pulse of width 5 µs and height 4 is applied to the input of this circuit beginning at t : τ.5 µs in.5 kω nf First, out will increase exponentially toward 4. out When in goes back down, out will decrease exponentially back down to. What is the peak alue of out? The output increases for 5 µs, or time constants. It reaches e or 86% of the final alue..86 x is the peak alue s (t) First Order ircuits: Forced esponse r (t) KL around the loop: r (t) c (t) s (t) i c (t) dc ( t) c ( t) s ( t) dt c(t) i s (t) L KL at the node: t ( t) ( x) dx i L i L (t) L dil ( t) il ( t) is ( t) dt s L (t) ( t) Slide 47 Slide 48

39 omplete Solution oltages and currents in a st order circuit satisfy a differential equation of the form dx( t) x( t) τ f ( t) dt f(t) is called the forcing function. The complete solution is the sum of particular solution (forced response) and complementary solution (natural response). x( t) x ( t) x ( t) Particular solution satisfies the forcing function omplementary solution is used to satisfy the initial conditions. The initial conditions determine the alue of K. dxp ( t) xp ( t) τ f ( t) dt p c dxc ( t) xc ( t) τ dt ( ) t / xc t Ke τ Slide 49 Homogeneous equation The Time onstant The complementary solution for any st order circuit is t / xc ( t) Ke τ For an circuit, τ For an L circuit, τ L/ Slide 5 What Does X c (t) Look Like? t x ( ) / c t e τ τ 4 τ is the amount of time necessary for an exponential to decay to 36.7% of its initial alue. /τ is the initial slope of an exponential with an initial alue of. The Particular Solution The particular solution x p (t) is usually a weighted sum of f(t) and its first deriatie. If f(t) is constant, then x p (t) is constant. If f(t) is sinusoidal, then x p (t) is sinusoidal. Slide 5 Slide 5

40 The Particular Solution: F(t) onstant Guess a solution x P ( t) t Equation holds for all time and time ariations are independent and thus each time ariation coefficient is indiidually zero Slide 53 dxp ( t) x ( t) τ dt P F d( t) ( t) τ F dt ( t) τ F ( τ F) ( ) t ( ) ( τ F) F The Particular Solution: F(t) Sinusoid dxp ( t) xp ( t) τ F sin( wt) F cos( wt) dt Guess a solution x P ( t) sin( wt) cos( wt) d( sin( wt) cos( wt)) ( sin( wt) cos( wt)) τ F sin( wt) F cos( wt) dt ( τω F )sin( ωt) ( τω F )cos( ωt) ( τω F ) ( τω F ) Equation holds for all time and time ariations are independent F τωf τωf F and thus each time ariation ( τω) ( τω) coefficient is indiidually zero τω xp ( t) sin( ωt) cos( ωt) ( τω) ( τω) ( τω) cos( ωt θ ); where θ tan ( τω) ( τω) Slide 54 The Particular Solution: F(t) Exp. The Total Solution: F(t) Sinusoid Guess a solution x ( t) e P αt Equation holds for all time and time ariations are independent and thus each time ariation coefficient is indiidually zero ( ατ F ) ατ F dxp ( t) αt xp ( t) τ F e F dt αt αt d( e ) αt ( e ) τ F e F dt αt αt αt ( e ) ατe F e F αt F ) ( ατ F ) e ( ( F ) F dxp ( t) xp ( t) τ F sin( wt) F cos( wt) dt F τωf τωf F x P ( t) sin( wt) cos( wt) ( τω) ( τω) x ( t) Ke x ( t) sin( wt) cos( wt) Ke T t τ Only K is unknown and is determined by the initial condition at t x () sin() cos() Ke T x ( ) K ( t ) T t τ Example: x T (t) (t) τ ( t ) K ( t ) Slide 55 Slide 56

41 Example t s c Gien c ( ), s cos(ωt), ω. Find i(t), c (t)? nd Order ircuits ny circuit with a single capacitor, a single inductor, an arbitrary number of sources, and an arbitrary number of resistors is a circuit of order. ny oltage or current in such a circuit is the solution to a nd order differential equation. Slide 57 Slide 58 nd Order L ircuit s (t) i (t) pplication: Filters bandpass filter such as the IF amp for the M radio. lowpass filter with a sharper cutoff than can be obtained with an circuit. L The Differential Equation KL around the loop: i (t) s (t) r (t) c (t) l (t) s (t) t r (t) l (t) di( t) i( t) i( x) dx L s ( t) dt di( t) d i( t) ds ( t) i( t) L dt L dt L dt L c (t) Slide 59 Slide 6

42 The Differential Equation The oltage and current in a second order circuit is the solution to a differential equation of the following form: d x t ( ) dx( t) α ω x( t) f ( t) dt dt x( t) x ( t) x ( t) p c X p (t) is the particular solution (forced response) and X c (t) is the complementary solution (natural response). The Particular Solution The particular solution x p (t) is usually a weighted sum of f(t) and its first and second deriaties. If f(t) is constant, then x p (t) is constant. If f(t) is sinusoidal, then x p (t) is sinusoidal. Slide 6 Slide 6 The omplementary Solution The complementary solution has the following form: x ( t) Ke c K is a constant determined by initial conditions. s is a constant determined by the coefficients of the differential equation. st st d Ke dke st α ω Ke dt dt s Ke α ske ω Ke st st st s α s ω st haracteristic Equation To find the complementary solution, we need to sole the characteristic equation: s ζω s ω α ζω The characteristic equation has two rootscall them s and s. x ( t) K e K e c s t s t s ζω ω ζ s ζω ω ζ Slide 63 Slide 64

43 Damping atio and Natural Frequency α ζ ω damping ratio s ζω ω ζ s ζω ω ζ Oerdamped : eal Unequal oots If ζ >, s and s are real and not equal. i c ( t) K e ςω ω ς t K e ςω ω ς t The damping ratio determines what type of solution we will get: Exponentially decreasing (ζ >) Exponentially decreasing sinusoid (ζ < ) The natural frequency is ω It determines how fast sinusoids wiggle. i(t) e6 t i(t) e6. t Slide 65 Slide 66 Underdamped: omplex oots If ζ <, s and s are complex. Define the following constants: α ζω ωd ω ζ ( ω ω ) x ( t) e cos t sin t α t c d d i(t) e5..e5 3.E t Slide 67 ritically damped: eal Equal oots If ζ, s and s are real and equal. x ( t) K e K te c ςω t Slide 68 ςω t Note: The degeneracy of the roots results in the extra factor of t

44 Example For the example, what are ζ and ω? i (t) d i( t) di( t) ds ( t) i( t) Ω dt L dt L L dt 769pF d xc ( t) dxc ( t) ζω ω xc ( t) dt dt 59µH ω, ζω, ζ L L L ζ. Example ω π455 Is this system oer damped, under damped, or critically damped? What will the current look like? i(t) e5..e5 3.E t Slide 69 Slide 7 Slightly Different Example Increase the resistor to kω What are ζ and ω? s (t) i (t) kω 769pF 59µH ζ. ω π455 Slide 7 i(t) e6 t Types of ircuit Excitation Linear Time Inariant ircuit SteadyState Excitation (D SteadyState) Linear Time Inariant ircuit Sinusoidal (Single Frequency) Excitation SteadyState Slide 7 Digital Pulse Source Linear Time Inariant ircuit O Linear Time Inariant ircuit Transient Excitation

45 Signal () elatie mplitude signal Signal () signal Signal () Why is SingleFrequency Excitation Important? Some circuits are drien by a singlefrequency sinusoidal source. Some circuits are drien by sinusoidal sources whose frequency changes slowly oer time. You can express any periodic electrical signal as a sum of singlefrequency sinusoids so you can analyze the response of the (linear, timeinariant) circuit to each indiidual frequency component and then sum the responses to get the total response. This is known as Fourier Transform and is tremendously important to all kinds of engineering disciplines! Slide 73 c a epresenting a Square Wae as a Sum of Sinusoids b d Slide 74 T i me (ms) Frequency (Hz) (a)square wae with second period. (b) Fundamental component (dotted) with second period, thirdharmonic (solid black) with/3second period, and their sum (blue). (c) Sum of first ten components. (d) Spectrum with terms. SteadyState Sinusoidal nalysis lso known as steadystate ny steady state oltage or current in a linear circuit with a sinusoidal source is a sinusoid. This is a consequence of the nature of particular solutions for sinusoidal forcing functions. ll steady state oltages and currents hae the same frequency as the source. In order to find a steady state oltage or current, all we need to know is its magnitude and its phase relatie to the source We already know its frequency. Usually, an steady state oltage or current is gien by the particular solution to a differential equation. hapter 5 OUTLINE Phasors as notation for Sinusoids rithmetic with omplex Numbers omplex impedances ircuit analysis using complex impdenaces Deratie/Integration as multiplication/diision Phasor elationship for ircuit Elements eading hap 5 ppendix Slide 75 Slide 76

46 t Example : nd Order L ircuit t Example : nd Order L ircuit s L s L Slide 77 Slide 78 Sinusoidal Sources reate Too Much lgebra Guess a solution x P ( t) sin( wt) cos( wt) dxp ( t) xp ( t) τ F sin( wt) F cos( wt) dt d( sin( wt) cos( wt)) ( sin( wt) cos( wt)) τ F sin( wt) F cos( wt) dt ( τ F )sin( wt) ( τ F )cos( wt) Two terms to be general Deraties ddition Equation holds for all time ( τ F) and time ariations are ( τ F ) independent and thus each F time ariation coefficient is τf τf F τ τ indiidually zero Phasors (ectors that rotate in the complex plane) are a cleer alternatie. Slide 79 y z imaginary axis omplex Numbers () j ( ) θ real x axis ectangular oordinates Z x jy Polar oordinates: Z z θ Exponential Form: Z jθ Z e ze jθ Slide 8 x is the real part y is the imaginary part z is the magnitude θ is the phase x z cosθ z x y Z z(cosθ j sin θ ) j e π j 9 j e y z sinθ θ tan y x

47 Euler s Identities omplex Numbers () j j e θ θ Z ze z θ e cosθ e sinθ e e jθ jθ jθ jθ e e j cosθ jθ jθ j sinθ θ θ cos sin Exponential Form of a complex number Z rithmetic With omplex Numbers To compute phasor oltages and currents, we need to be able to perform computation with complex numbers. ddition Subtraction Multiplication Diision (nd later use multiplication by jω to replace Diffrentiation Integration Slide 8 Slide 8 ddition ddition is most easily performed in rectangular coordinates: x jy z jw (x z) j(y w) ddition Imaginary xis eal xis Slide 83 Slide 84

48 Subtraction Subtraction is most easily performed in rectangular coordinates: x jy z jw Subtraction Imaginary xis (x z) j(y w) eal xis Slide 85 Slide 86 Multiplication Multiplication Multiplication is most easily performed in polar coordinates: M θ M φ Imaginary xis ( M M ) (θ φ) eal xis Slide 87 Slide 88

49 Diision Diision is most easily performed in polar coordinates: M θ M φ / ( M / M ) (θ φ) Diision Imaginary xis / eal xis Slide 89 Slide 9 rithmetic Operations of omplex Numbers dd and Subtract: it is easiest to do this in rectangular format dd/subtract the real and imaginary parts separately Multiply and Diide: it is easiest to do this in exponential/polar format Multiply (diide) the magnitudes dd (subtract) the phases Z Z θ z e z θ z cosθ jz sinθ j θ z e z θ z cosθ jz sinθ j Z Z ( z cosθ z cos θ ) j( z sinθ z sin θ ) Z Z ( z cosθ z cos θ ) j( z sinθ z sin θ ) Z Z ( z z ) e ( z z ) ( θ θ ) j( θ θ ) j θ θ Z / Z ( z / z ) e ( ) ( z / z ) ( θ θ ) Phasors ssuming a source oltage is a sinusoid timearying function (t) cos (ωt θ) We can write: j( ωt θ ) j( ωt θ ) ( t) cos( ωt θ ) e e e e jθ Define Phasor as e θ Similarly, if the function is (t) sin (ωt θ) π π j( ωt θ ) ( t) sin( ωt θ ) cos( ωt θ ) e e Phasor π ( θ ) Slide 9 Slide 9

50 Phasor: otating omplex ector jφ jwt t { e e } ( e j ω e ) ( t) cos( ωt φ) e Imaginary xis cos(ωtφ) otates at uniform angular elocity ωt eal xis The head start angle is φ. omplex Exponentials We represent a realalued sinusoid as the real part of a complex exponential after multiplying j t by e ω. omplex exponentials proide the link between time functions and phasors. llow deraties and integrals to be replaced by multiplying or diiding by jω make soling for steady state simple algebra with complex numbers. Phasors allow us to express currentoltage relationships for inductors and capacitors much like we express the currentoltage relationship for a resistor. Slide 93 Slide 94 I elationship for a apacitor apacitor Impedance () i(t) (t) i( t) Suppose that (t) is a sinusoid: (t) e{ M e j(ωtθ) } Find i(t). d( t) dt i(t) d( t) i( t) (t dt ) j( ωt θ ) j( ωt θ ) ( t) cos( ωt θ ) e e d( t) d j( ωt θ ) j( ωt θ ) j( ωt θ ) j( ωt θ ) i( t) e e j e e dt dt ω ω e j( ωt θ ) e j( ωt θ ) π ω sin( ω t θ ) ω cos( ω t θ ) j θ π π Zc ( θ θ ) ( ) j I π ω ω ω jω I θ Slide 95 Slide 96

51 apacitor Impedance () i(t) d( t) i( t) (t dt ) ( ) cos( ω θ ) e θ j( ωt θ ) t t e d( t) de dt dt I θ θ ( θ θ ) I I θ jω jω j( ωt θ ) j( ωt θ ) i( t) e e jωe I Z c Phasor definition Example (t) cos(377t 3 ) µf What is? What is I? What is i(t)? Slide 97 Slide 98 omputing the urrent Inductor Impedance Note: The differentiation and integration operations become algebraic operations i(t) L (t) ( t) L di( t) dt d jω dt dt jω jωl I Slide 99 Slide

52 Example i(t) µ cos(π t 3 ) L µh What is I? What is? What is (t)? Slide lead oltage 7 cos( ω t) Phase inductor current π π 7sin( ωt) 7 cos( ωt ) 7 capacitor current π π 7sin( ωt) 7 cos( ωt ) 7 Slide t ehind Phasor Diagrams phasor diagram is just a graph of seeral phasors on the complex plane (using real and imaginary axes). phasor diagram helps to isualize the relationships between currents and oltages. apacitor: I leads by 9 o Inductor: leads I by 9 o Impedance steadystate analysis using phasors allows us to express the relationship between current and oltage using a formula that looks likes Ohm s law: I Z Z is called impedance. Slide 3 Slide 4

53 Some Thoughts on Impedance Impedance depends on the frequency ω. Impedance is (often) a complex number. Impedance allows us to use the same solution techniques for steady state as we use for D steady state. Example: Single Loop ircuit kω µf f6 Hz,? How do we find? First compute impedances for resistor and capacitor: Z kω kω Z /j (πf x µf).65kω 9 Slide 5 Slide 6 Impedance Example kω What happens when ω changes?.65kω 9 kω µf Now use the oltage diider to find :.65kΩ 9.65kΩ 9 kω ω Find Slide 7 Slide 8

54 ircuit nalysis Using omplex Impedances Suitable for steady state. KL ( t) ( t) ( t) 3 ( ω θ ) ( ω θ ) ( ω θ ) cos t cos t cos t 3 3 Phasor Form KL j( ωt θ ) j( ωt θ ) j( ωt θ3 ) e e e 3e e e e j( θ ) j( θ ) j( θ3 ) 3 3 Phasor Form KL I I I3 Use complex impedances for inductors and capacitors and follow same analysis as in chap. SteadyState nalysis 5m.µF kω Find (t) for ωπ 3 5m j53kω kω Slide 9 Slide Find the Equialent Impedance 5m Z eq 3 ( j53) 53 9 Z eq j Z eq 468.Ω 6. 5m 468.Ω 6. IZ eq ( t).34 cos(π 3t 6. ) hange the Frequency 5m.µF kω Find (t) for ωπ 455 j3.5ω 5m kω Slide Slide

55 Find an Equialent Impedance Series Impedance 5m Z eq Z eq ( j3.5) j3.5 Z eq 3.5Ω m 3.5Ω IZ eq 7.5m ( t) 7.5m cos(π 455t 89.8 ) Z Z Z 3 Z eq Z Z Z 3 For example: L L Z eq jω(l L ) Z eq jω jω Z eq Slide 3 Slide 4 Parallel Impedance SteadyState Nodeoltage nalysis Z Z Z 3 Z eq I sin(ωt) L I cos(ωt) For example: /Z eq /Z /Z /Z 3 Try using Theinin equialent circuit. Z L eq L L L jω ( L L ) Z eq jω( ) What happens if the sources are at different frequencies? Slide 5 Slide 6

56 esistor I relationship i. I where is the resistance in ohms, phasor oltage, I phasor current (boldface indicates complex quantity) apacitor I relationship i d /dt...phasor current I phasor oltage / capacitie impedance Z : I /Z where Z /jω, j () / and boldface indicates complex quantity ( t) cos( ωt) i t ω ( ) cos( ) t ( t) cos( ωt) i ( t) ω sin( ωt) L ( t) cos( ωt) i t ωl ω ( ) sin( ) t Inductor I relationship L Ldi L /dt...phasor oltage L phasor current I L / inductie impedance Z L L I L Z L where Z L jωl, j () / and boldface indicates complex quantity I I ω 9 I ωl 9 Slide 7 Slide 8 f6 Hz TH O Theenin Equialent kω µf Z kω kω Z /j (πf x µf).65kω 9 Z TH TH Z TH.65kΩ kΩ 9 kω kω.65kω 9 Z Z kΩ 9 kω oot Mean Square (rms) alues rms alued defined as ssuming a sinusoid gies Using an identity gies Ealuating at limits gies MS MS T ( t) dt T m [ T sin(ωt θ ) sin(θ )] T ω w o T MS m t dt T cos ( ω θ ) o T m MS t dt T [ cos(ω θ )] o T period MS m Slide 9 Slide

57 Power: Instantaneous and Timeerage For a esistor The instantaneous power is The timeaerage power is PE T For an Impedance ( t) i The instantaneous power is The timeaerage power ist PE T The reactie power at ω is Q Im{ T Slide ( t) p( t) ( t) i( t) T ( t) p( t) dt dt [ ( t) dt] T T ( t p ( t) ( t) i( t) T * rms I rms p( t) dt ( t) i( t) dt e{ T rms I * rms } P E Q T ( rms I rms ) } rms Maximum erage Power Transfer TH Z TH Maximum time aerage power occurs when Z * LOD Z TH This presents a resistie impedance to the source Z total ZTH Z Power transferred is P E Slide Z LOD * TH * * e{ I } e{ } rms hapter 6 OUTLINE Frequency esponse for haracterization symptotic Frequency ehaior Log magnitude s log frequency plot Phase s log frequency plot d scale Transfer function example el and Decibel (d) bel (symbol ) is a unit of measure of ratios of power leels, i.e. relatie power leels. The name was coined in the early th century in honor of lexander Graham ell, a telecommunications pioneer. The bel is a logarithmic measure. The number of bels for a gien ratio of power leels is calculated by taking the logarithm, to the base, of the ratio. one bel corresponds to a ratio of :. log (P /P ) where P and P are power leels. The bel is too large for eeryday use, so the decibel (d), equal to., is more commonly used. d log (P /P ) d are used to measure Electric power, Gain or loss of amplifiers, Insertion loss of filters. Slide 3 Slide 4

58 Logarithmic Measure for Power To express a power in terms of decibels, one starts by choosing a reference power, P reference, and writing Power P in decibels log (P/P reference ) Exercise: Express a power of 5 mw in decibels relatie to watt. P (d) log (5 x 3 ) 3 d Exercise: Express a power of 5 mw in decibels relatie to mw. P (d) log (5) 7 d. dm to express absolute alues of power relatie to a milliwatt. dm log (power in milliwatts / milliwatt) mw dm mw dm Logarithmic Measures for oltage or urrent From the expression for power ratios in decibels, we can readily derie the corresponding expressions for oltage or current ratios. Suppose that the oltage (or current I) appears across (or flows in) a resistor whose resistance is. The corresponding power dissipated, P, is / (or I ). We can similarly relate the reference oltage or current to the reference power, as Hence, P reference ( reference ) / or P reference (I reference ). oltage, in decibels log (/ reference ) urrent, I, in decibels log (I/I reference ) Slide 5 Slide 6 Logarithmic Measures for oltage or urrent Note that the oltage and current expressions are just like the power expression except that they hae as the multiplier instead of because power is proportional to the square of the oltage or current. Exercise: How many decibels larger is the oltage of a 9olt transistor battery than that of a.5olt battery? Let reference.5. The ratio in decibels is log (9/.5) log (6) 6 d. Logarithmic Measures for oltage or urrent The gain produced by an amplifier or the loss of a filter is often specified in decibels. The input oltage (current, or power) is taken as the reference alue of oltage (current, or power) in the decibel defining expression: oltage gain in d log ( output / input ) urrent gain in d log (I output /I input Power gain in d log (P output /P input ) Example: The oltage gain of an amplifier whose input is. m and whose output is.5 is log (.5/.x 3 ) 68 d. Slide 7 Slide 8

59 ode Plot Plot of magnitude of transfer function s. frequency oth x and y scale are in log scale Y scale in d Log Frequency Scale Decade atio of higher to lower frequency Octae atio of higher to lower frequency Frequency esponse The shape of the frequency response of the complex ratio of phasors OUT / IN is a conenient means of classifying a circuit behaior and identifying key parameters. OUT IN Gain Low Pass Frequency reak point OUT IN reak point High Pass Frequency Gain FYI: These are log ratio s log frequency plots Slide 9 Slide 3 IN OUT IN Example ircuit TransferFunction T OUT IN OUT IN (/ jw) / jω ) ( T Zc Z Z jω c ) OUT, Ohms Ohms uf reak Point alues When dealing with resonant circuits it is conenient to refer to the frequency difference between points at which the power from the circuit is half that at the peak of resonance. Such frequencies are known as halfpower frequencies, and the power output there referred to the peak power (at the resonant frequency) is log (P halfpower /P resonance ) log (/) 3 d. Slide 3 Slide 3

60 Example: ircuit in Slide #3 Magnitude Example: ircuit in Slide #3 Phase Magnitude. OUT IN ( j ω ) w p /( ) ctual alue adian Frequency Ohms uf j Phase OUT IN ( jω) adian Frequency 45 o ctual alue is Ohms uf Phase{ } Phase{ } j 45 Slide 33 Slide 34 ode Plot: Label as d Transfer Function Magnitude in d 6 4 OUT IN ( jω) w p /( ) Ohms uf Transfer function is a function of frequency omplex quantity oth magnitude and phase are function of frequency in Two Port filter network out adian Frequency Note: Magnitude in d log ( OUT / IN ) out out H( f ) out in H(f) H ( f ) θ in ( θ θ ) in Slide 35 Slide 36

61 Filters ircuit designed to retain a certain frequency range and discard others Lowpass: pass low frequencies and reject high frequencies Highpass: pass high frequencies and reject low frequencies andpass: pass some particular range of frequencies, reject other frequencies outside that band Notch: reject a range of frequencies and pass all other frequencies H ( f ) H ( f ) ommon Filter Transfer Function s. Freq Low Pass Frequency and Pass Frequency H ( f ) H ( f ) High Pass Frequency and eject Frequency Slide 37 Slide 38 FirstOrder Lowpass Filter FirstOrder Highpass Filter H(f) ( jω) tan ( jω) jω ω Let ω and f π H(f) H ( f ) θ H ( f ), tan f f f θ f / H ( f ) H ( f ) log ( )log 3 d H () ( ) ( ω ) H(f) θ f ( ω) ( ) jω π tan ( ω) ( jω) jω ω f f H ( f ) π, tan f f f / H ( f ) H ( f ) log ( )log 3 d H () Slide 39 Slide 4

62 FirstOrder Lowpass Filter FirstOrder Highpass Filter H(f) jωl ωl Let ω and f L π L H(f) H ( f ) θ H ( f ), θ tan f f f f tan ωl L L jωl ωl H(f) jωl ωl Let ω and f L π L H(f) H ( f ) θ π L tan f f H ( f ) π, tan f f f θ f ωl L L Slide 4 Slide 4 FirstOrder Filter ircuits hange of oltage or urrent with hange of Frequency S High Pass Low Pass S Low Pass L High Pass One may wish to specify the change of a quantity such as the output oltage of a filter when the frequency changes by a factor of (an octae) or (a decade). For example, a singlestage lowpass filter has at frequencies aboe ω / an output that changes at the rate d per decade. H / ( /jω) H (/jω) / ( /jω) H / ( jωl) H L jωl / ( jωl) Slide 43 Slide 44

63 Highfrequency asymptote of Lowpass filter Lowfrequency asymptote of Highpass filter The high frequency asymptote of magnitude ode plot assumes d/decade slope s f f H ( f ) f H ( f ) log d H ( f ) s f f f f H ( f ) f f f f H ( f ) log d H (. f ) The low frequency asymptote of magnitude ode plot assumes d/decade slope Slide 45 Slide 46 SecondOrder Filter ircuits Series esonance IN S and Pass Low Pass High Pass L and eject Z /jω jωl H P / Z H LP (/jω) / Z H HP jωl / Z H H LP H HP oltage diider OUT IN OUT IN Z Z Z Z L Substitute branch elements OUT IN jω L / jω rrange in resonance form j( ωl / ω) OUT esonance quality factor Q ωl atio of reactance to resistance losely related to number of round trip cycles before /e decay. Maximum when w /(L) andwidth is f /Q Slide 47 Slide 48

64 dmittance OUT OUT Parallel esonance I S Y Y Y Substitute branch elements S I jw j ω L rrange in resonance form OUT L I IN I S j( ω ) ωl Maximum I S / when w /(L) OUT esonance quality factor Q ωl atio of reactance to resistance losely related to number of round trip cycles before /e decay. andwidth is f /Q OUTLINE hapter 4 Opmp from Port locks Opmp Model and its Idealization Negatie Feedback for Stability omponents around Opmp define the ircuit Function eading hap 4 Slide 49 Slide 5 The Operational mplifier The operational amplifier ( op amp ) is a basic building block used in analog circuits. Its behaior is modeled using a dependent source. When combined with resistors, capacitors, and inductors, it can perform arious useful functions: amplification/scaling of an input signal sign changing (inersion) of an input signal addition of multiple input signals subtraction of one input signal from another integration (oer time) of an input signal differentiation (with respect to time) of an input signal analog filtering nonlinear functions like exponential, log, sqrt, etc Isolate input from output; allow cascading Slide 5 High Quality Dependent Source In an mplifier MPLIFIE SYMOL Differential mplifier ( ) depends only on input ( ) Slide 5 MPLIFIE MODEL ircuit Model in linear region See the utility of this: this Model when used correctly mimics the behaior of an amplifier but omits the complication of the many many transistors and other components. i

65 Op mp Terminals 3 signal terminals: inputs and output I op amps hae additional terminals for D power supplies ommonmode signal ( )/ Differential signal Inerting input Noninerting input positie power supply output negatie power supply Model for Internal Operation is differential gain or open loop gain Ideal op amp i o ommon mode gain ( ), cm d o cm cm d d Since ( ), o cm ircuit Model i i _ i o i o ( ) o Slide 53 Slide 54 Model and Feedback Opmp and Use of Feedback Negatie feedback connecting the output port to the negatie input (port ) Positie feedback connecting the output port to the positie input (port ) Input impedance: looking into the input terminals Output impedance: Impedance in series with the output terminals ircuit Model i i o i o i o _ ( ) ery highgain differential amplifier can function in an extremely linear fashion as an operational amplifier by using negatie feedback. IN Summing Point Negatie feedback Stabilizes the output Hambley Example pp. 644 for Power Steering We can show that that for and i, IN IN i ircuit Model Stable, finite, and independent of the properties of the OP MP! Slide 55 Slide 56

66 SummingPoint onstraint heck if under negatie feedback Small i result in large o Output o is connected to the inerting input to reduce i esulting in i Summingpoint constraint i i irtual short circuit Not only oltage drop is (which is short circuit), input current is This is different from short circuit, hence called irtual short circuit. Ideal Opmp nalysis Technique pplies only when Negatie Feedback is present in circuit! ssumption : The potential between the opamp input terminals, () (), equals zero. ssumption : The currents flowing into the opamp s two input terminals both equal zero. No urrents IN EXMPLE No Potential Difference Slide 57 Slide 58 Ideal Opnalysis: NonInerting mplifier Yes Negatie Feedback is present in this circuit! ssumption : The potential between the opamp input terminals, () (), equals zero. ssumption : The currents flowing into the opamp s two input terminals both equal zero. IN EXMPLE KL with currents in only two branches IN appears here in in out out in Noninerting mplifier NonInerting mplifier Ideal oltage amplifier losed loop gain in in, i i Use KL t Node. _ L ( ) ( ) i o ( ) in Input impedance i o in in Slide 59 Slide 6

67 Ideal Opmp nalysis: Inerting mplifier oltage is Only two currents for KL Yes Negatie Feedback is present in circuit! IN IN I OUT L OUT ( ) OUT in Inerting mplifier with reference oltage Negatie feedback checked Use summingpoint constraint i in _ Inerting mplifier losed loop gain, i i Use KL t Node. ( in ) ( out ) i o Input impedance o i in Ideal oltage source independent of load resistor L o in Slide 6 Slide 6 oltage Follower Example i 5 in _ L in i 4 i 3 i i _ L Switch is open ( ) ( ) i o ( ) in Slide 63, i i 3 ( in ) i3 in i4 i5 ( ) i 5 in o, in in Slide 64

68 Example Example in i 4 i 3 i 5 i i _ L Switch is closed, i i 3 ( in ) ( ) i4 i 5 in o, in in Slide 65 Design an analog front end circuit to an instrument system equires to work with 3 fullscale of input signals (by manual switch): ±, ±, ± For each input range, the output needs to be ± The input resistance is MΩ o ( ) Switch at c in Slide 66 in b a a b in Switch at b a b c a in Switch at a a b c c b a _ L Example (cont d) Summing mplifier M Ω in a b c Max ( ) a b a b ( ). a b c a b c a a. ( ). a b c a b c kω, 9 kω, 9kΩ a b c Switch at c Switch at b Switch at a _ Slide 67 Slide 68

69 Difference mplifier Integrator Want o K indt _ What is the difference between: 3 4 in Slide 69 Slide 7 Differentiator ridge mplifier Want x (ε) _ in a _ x a in Slide 7 Slide 7

70 pplication: Digitaltonalog onersion D can be used to conert the digital representation of an audio signal into an analog oltage that is then used to drie speakers so that you can hear it! Weightedadder D/ conerter S4 K 8 S3 S S 4it D/ K 4K 8K (Transistors are used as electronic switches) 5K S closed if LS S " if next bit S3 " if " " S4 " if MS Slide 73 inary number (olts) MS LS nalog output nalog Output () haracteristic of 4it D Digital Input Slide 74 ctie Filter ontain few components Transfer function that is insensitie to component tolerance Easily adjusted equire a small spread of components alues llow a wide range of useful transfer functions ctie Filter Example 3 in _ (k) f f Slide 75 Slide 76

71 ctie Filter Solution o k Use Use KL KL t t Node Node ( 3 ) jω ( in 3 ) ( 3 ) jω ( 3 o ) o k ω jω (3 k ) in Let ω / o H ( ω ) in ω, H ( ω ) k D gain k ω ω (3 k ) ω ω k ω ω, H ( ω ) 3 k k ω >> ω, H ( ω ) ω ω ω log H ( ω ) decays at a rate of 4 d / decade Slide 77 in 3 ascaded ctie Filter Example _ 3 f f (k) f _ (k ) f Slide 78 ascaded ctie Filter Solution o k k ω jω (3 k ) ω jω(3 k) in Let ω /, ω / o k k H ( ω) in ω ω ω ω (3 ) (3 ) ω ω ω ω ω, H ( ω) k k D gain ω ω, H ( ω) 3 k 3 k k k k k kk 4 ω >> ω, H ( ω) ω 4 ω ω ω log H ( ω) decays at a rate of 8 d / decade Slide 79 hapter OUTLINE Diode urrent and Equation Some Interesting ircuit pplications Load Line nalysis Solar ells, Detectors, Zener Diodes ircuit nalysis with Diodes Halfwae ectifier lamps and oltage Doublers using apacitors eading Hambley..8 Supplementary Notes hapter Slide 8

72 I haracteristics Diode Physical ehaior and Equation In forward bias ( on pside) we hae almost unlimited flow (ery low resistance). Qualitatiely, the I characteristics must look like: In reerse bias ( on nside) almost no current can flow. Qualitatiely, the I characteristics must look like: The current is close to zero for any negatie bias I current increases rapidly with I F F Schematic Deice N type P type Qualitatie I characteristics: I positie, easy conduction negatie, no conduction I Symbol Quantitatie I characteristics: I I (e q kt ) In which kt/q is.6 and I O is a constant depending on diode area. Typical alues: to 6. Interestingly, the graph of this equation looks just like the figure to the left. nonideality factor n times kt/q is often included. I Slide 8 Slide 8 The pn Junction I s. Equation I characteristic of PN junctions In EES 5, 3, and other courses you will learn why the I s. relationship for PN junctions is of the form I I (e q kt ) where I is a constant proportional to junction area and depending on doping in P and N regions, 9 q electronic charge.6, k is oltzman constant, and T is absolute temperature. KT q.6 at3 K, a typical alue for I is 5 We note that in forward bias, I increases exponentially and is in the µm range for oltages typically in the range of.6.8. In reerse bias, the current is essentially zero. Diode Ideal (Perfect ectifier) Model The equation I I q exp( ) kt 5 is graphed below for I urrent in m Forward oltage in 5 5 The characteristic is described as a rectifier that is, a deice that permits current to pass in only one direction. (The hydraulic analog is a check alue.) Hence the symbol: I Simple Perfect ectifier Model If we can ignore the small forwardbias oltage drop of a diode, a simple effectie model is the perfect rectifier, whose I characteristic is gien below: I eerse bias Forward I, any <, any bias I > perfect rectifier Slide 83 Slide 84

73 urrent (microamp) Diode LargeSignal Model (.7 Drop) forward bias () Improed LargeSignal Diode Model: If we choose not to ignore the small forwardbias oltage drop of a diode, it is a ery good approximation to regard the oltage drop in forward bias as a constant, about.7. the Large signal model results..7 eerse bias Forward I, any <.7, any bias I >.7 I The LargeSignal Diode Model I S (t) ssume the ideal (perfect rectifier) model. rectified ersion of input waeform ectifier ircuit (t) S (t) (t) t t Slide 85 Slide 86 Peak Detector ircuit pnjunction eerse reakdown i (t) ssume the ideal (perfect rectifier) model. (t) Key Point: The capacitor charges due to one way current behaior of the diode. i (t) (t) i t s the reerse bias oltage increases, the peak electric field in the depletion region increases. When the electric field exceeds a critical alue (E crit x 5 /cm), the reerse current shows a dramatic increase: reerse (leakage) current breakdown oltage D I D () forward current D () Slide 87 Slide 88

74 Zener Diode Zener diode is designed to operate in the breakdown mode. reerse (leakage) current breakdown oltage D I D () forward current D () Load Line nalysis Method. Graph the I relationships for the nonlinear element and for the rest of the circuit. The operating point of the circuit is found from the intersection of these two cures. Th I I Example: Th / Th operating point t Th s (t) D 5 o (t) integrated circuit Th The I characteristic of all of the circuit except the nonlinear element is called the load line Slide 89 Slide 9 Solar cell: Example of simple PN junction What is a solar cell? Deice that conerts sunlight into electricity Photooltaic (Solar) ell I qd kt D I S ( e ) I optical How does it work? In simple configuration, it is a diode made of PN junction Incident light is absorbed by material reates electronhole pairs that transport through the material through Diffusion (concentration gradient) Drift (due to electric field) PN Junction Diode in the dark I D () D () with incident light Operating point The load line a simple resistor. Slide 9 Slide 9

75 I characteristics of the deice Example : Photodiode I characteristics of a PN junction is gien by e I I exp( ) kt S I L where I s is the saturation intensity depending on band gap and doping of the material and I L is the photocurrent generated due to light oc I sc ( m, I m ) n intrinsic region is placed between the ptype and ntype regions W j W iregion, so that most of the electronhole pairs are generated in the depletion region faster response time (~ GHz operation) I D () Efficiency is defined as η I m. m FF * oc * I sc Light Intensity Light Intensity FF is the Fill Factor oc Open circuit oltage I sc Short circuit current I mp, mp urrent and oltage at maximum power operating point in the dark with incident light D () Slide 93 Slide 94 Th Photodetector ircuit Using Load Line Th I s light shines on the photodiode, carriers are generated by absorption. These excess carriers are swept by the electric field at the junction creating drift current, which is same direction as the reerse bias current and hence negatie current. The current is proportional to light intensity and hence can proide a direct measurement of light intensity photodetector. What happens when th is too large? Why use th? operating points under different light conditions. Th I Th / Th s light intensity increases. Why? load line ircuit symbol I D Ideal Diode Model of PN Diode D reerse bias forward bias n ideal diode passes current only in one direction. n ideal diode has the following properties: when I D >, D when D <, I D I characteristic I D () D () Switch model I D Diode behaes like a switch: closed in forward bias mode open in reerse bias mode D Slide 95 Slide 96

76 LargeSignal Diode Model ircuit symbol I characteristic Switch model I D I D () I D Don Diode: Large Signal Model Use piecewise linear model D reerse bias forward bias D () D Don For a Si pn diode, Don.7 ULE : When I D >, D Don ULE : When D < Don, I D Diode behaes like a oltage source in series with a switch: closed in forward bias mode open in reerse bias mode Slide 97 Slide 98 How to nalyze ircuits with Diodes diode has only two states: forward biased: I D >, D (or.7 ) reerse biased: I D, D < (or.7 ) Procedure:. Guess the state(s) of the diode(s). heck to see if KL and KL are obeyed. 3. If KL and KL are not obeyed, refine your guess 4. epeat steps 3 until KL and KL are obeyed. Diode Logic: ND Gate Diodes can be used to perform logic functions: ND gate output oltage is high only if both and are high cc ND Inputs and ary between olts ( low ) and cc ( high ) etween what oltage leels does ary? OUT 5 EO Example: s (t) (t) If s (t) >, diode is forward biased (else KL is disobeyed try it) If s (t) <, diode is reerse biased (else KL is disobeyed try it) Slope Shift.7 Up 5 IN Slide 99 Slide 3

77 Diode Logic: O Gate Diodes can be used to perform logic functions: Diode Logic: Incompatibility and Decay Diode Only Gates are asically Incompatible: Inputs and ary between olts ( low ) and cc ( high ) etween what oltage leels does ary? O gate output oltage is high if either (or both) and are high ND gate output oltage is high only if both and are high cc O gate output oltage is high if either (or both) and are high OUT 5 EO O ND ND O O Slope Shift.7 Down.7 5 IN ND High want ND >> O ND Low want ND << O Signal Decays with each stage (Not regeneratie) Slide 3 Slide 3 Deice Isolation using pn Junctions regions of ntype Si n n n n n ptype Si No current flows if oltages are applied between ntype regions, because two pn junctions are backtoback nregion nregion Why are pn Junctions Important for Is? The basic building block in digital Is is the MOS transistor, whose structure contains reersebiased diodes. pn junctions are important for electrical isolation of transistors located next to each other at the surface of a Si wafer. The junction capacitance of these diodes can limit the performance (operating speed) of digital circuits pregion > ntype regions isolated in ptype substrate and ice ersa Slide 33 Slide 34

78 Power onersion ircuits onerting to D Potential applications: harging a battery ectifier Equialent circuit >.6, diode short circuit o I.6 <.6, diode open circuit o I m sin (ωt) o Slide 35 Slide 36 Halfwae ectifier ircuits HalfWae ectifier dding a capacitor: what does it do? m sin (ωt) urrent charging up capacitor Slide 37 Slide 38

79 Leel Shift ircuit oltage Doubler ircuit IN OUT IN t IN OUT IN OUT OUT Leel Shift Peak Detect t Once the capacitor is charged by the negatie most oltage the rest of the signal is shifted up by that amount. The final output is the peak to peak oltage of the input. Slide 39 Slide 3 Week OUTLINE asic Semiconductor Materials n and p doping andgap Gauss s Law Poisson Equation Depletion approximation Diode I characteristics Lasers and LEDs Solar ells eading Supplementary Notes hap 3 onductors, Insulators and Semiconductors Solids with free electrons that is electrons not directly inoled in the interatomic bonding are the familiar metals (u, l, Fe, u, etc). Solids with no free electrons are the familiar insulators (glass, quartz crystals, ceramics, etc.) Silicon is an insulator, but at higher temperatures some of the bonding electrons can get free and make it a little conducting hence the term semiconductor Pure silicon is a poor conductor (and a poor insulator). It has 4 alence electrons, all of which are needed to bond with nearest neighbors. No free electrons. Slide 3 Slide 3

80 The Periodic Table III I Electronic onds in Silicon D picture of perfect crystal of pure silicon; double line is a SiSi bond with each line representing an electron Si ion (charge 4 q) Two electrons in each bond ctual structure is 3dimensional tetrahedral just like carbon bonding in organic and inorganic materials. Essentially no free electrons, and no conduction insulator Slide 33 Slide 34 How to get conduction in Si? Doping Silicon with Donors (ntype) We must either: ) hemically modify the Si to produce free carriers (permanent) or Donors donate mobile electrons (and thus ntype silicon) Example: add arsenic (s) to the silicon crystal: ) Electrically induce them by the field effect (switchable) For the first approach controlled impurities, dopants, are added to Si: dd group elements (5 bonding electrons s four for Si), such as phosphorus or arsenic (Extra electrons produce free electrons for conduction.) or s Mobile electron donated by s ion dd group III elements (3 bonding electrons), such as boron Deficiency of electrons results in free holes Immobile (stuck) positiely charged arsenic ion after 5 th electron left The extra electron with s, breaks free and becomes a free electron for conduction Slide 35 Slide 36

81 Doping with cceptors (ptype) Group III element (boron, typically) is added to the crystal Immobile (stuck) negatie boron ion after accepting electron from neighboring bond Mobile hole contributed by ion and later path Doping Typical doping densities: 6 ~ 9 cm 3 tomic density for Si: 5 x atoms/cm 3 8 cm 3 is in 5, two persons in entire erkeley wearing a green hat Pn junction effect is like The hole which is a missing bonding electron, breaks free from the acceptor and becomes a roaming positie charge, free to carry current in the semiconductor. It is positiely charged. Slide 37 Slide 38 Shockley s Parking Garage nalogy for onduction in Si Shockley s Parking Garage nalogy for onduction in Si Twostory parking garage on a hill: Twostory parking garage on a hill: If the lower floor is full and top one is empty, no traffic is possible. nalog of an insulator. ll electrons are locked up. If one car is moed upstairs, it can moe ND THE HOLE ON THE LOWE FLOO N MOE. onduction is possible. nalog to warmedup semiconductor. Some electrons get free (and leae holes behind). Slide 39 Slide 3