EE 40 Course Overview. Introduction. Grading Policy. Important DATES

Transcription

1 Introduction Instructor: Prof. Connie ChangHasnain Office: 63M Cory Hall Office hour: M 34, W cch@eecs.berkeley.edu Secretary: Therese George, 53 Cory, therese@eecs.berkeley.edu ackground 987: Ph. D., EECS, UC erkeley Experiences: ellcore; ssistant/ssociate Prof. in EE, Stanford Uniersity; Founder, CEO, andwidth9 996 : Professor of EECS, erkeley 4 : Director, Center for Optoelectronic NanoSemiconducto Tech. Some Current esearch Projects ertical caity surface emitting lasers Integrating CSEL and MEMS Synthesis of nanowires and quantum dots Slow down light in semiconductor to < m/sec. EE 4 Course Oeriew EECS 4: One of fie EECS core courses (with, 6, 6, and 6C) introduces hardware side of EECS prerequisite for EE5, EE3, EE4, EE5 Prerequisites: Math, Physics 7 Course inoles three hours of lecture, one hour of discussion and three hours of lab work each week. Course content: Fundamental circuit concepts and analysis techniques First and second order circuits, impulse and frequency response Op mps Diode and FET: Deice and Circuits mplification, Logic, Filter Text ook Electrical Engineering: Principles and pplications, third edition, llan. Hambley, Pearson Prentice Hall, 5 Supplementary Notes Slide Slide Important DTES Office hours, Discussion and Lab Sessions will start on week Stay with ONE Discussion and Lab session you registered. Midterm and Final Dates: Midterm: am on 9/7, /5, /9 (Location TD) Final: 8am on / (Location TD) est Lecture Notes Contest Due at 63M Cory, 5pm, /5 onus points equialent to % of final grade for one winner If none of the submission contains complete information, no winner will be selected. est Final Project Contest /8 35pm Location TD Slide 3 Grading Policy Weights: %: HW sets 5%: Labs 7 structured experiments (7%) one 4week final project (8%) 3% each: 3 midterm exams 35%: Final exam No late HW or Lab reports accepted No makeup exams unless Prof. Chang s approal is obtained at least 4 hours before exam time; proofs of extraneous circumstances are required. Slide 4

2 Grading Policy (Cont d) Weekly HW: ssignment on the web by 5 pm Wednesdays, starting 8/3/5. Due 5 pm the following Wednesday in HW box, 4 Cory. On the top page, right top corner, write your name (in the form: Last Name, First Name) with discussion session number. Graded homework will be returned one week later in discussion sessions. Labs Complete the prelab section before going to the lab. Satisfactory completion of each lab is necessary to pass class. Classroom ules Please come to class on time. Turn off cell phones, pagers, radio, CD, DD, etc. No food. No pets. Do not come in and out of classroom. Lectures will be recorded and webcasted. Slide 5 Slide 6 Week Electric Charge Outline Electrical quantities Charge Current oltage Power The ideal basic circuit element Sign conentions Circuit element I characteristics Construction of a circuit model Kirchhoff s laws a closer look eading Chapter and beginning of Ch. Electrical effects are due to separation of charge electric force (oltage) charges in motion electric flow (current) Macroscopically, most matter is electrically neutral most of the time. Exceptions: clouds in a thunderstorm, people on carpets in dry weather, plates of a charged capacitor, etc. Microscopically, matter is full of electric charges Electric charge exists in discrete quantities, integral multiples of the electronic charge.6 x 9 Coulomb Slide 7 Slide 8

3 Classification of Materials Solids in which the outermost atomic electrons are free to moe around are metals. Metals typically hae ~ free electron per atom Examples: Solids in which all electrons are tightly bound to atoms are insulators. Examples: Electrons in semiconductors are not tightly bound and can be easily promoted to a free state. Examples: Slide 9 Slide Electric Current Definition: rate of positie charge flow Symbol: i Units: Coulombs per second mperes () Note: Current has polarity. i dq/dt where q charge (Coulombs) t time (in seconds) Electric Current Examples. 5 positiely charged particles (each with charge.6 9 C) flow to the right (x direction) eery nanosecond 5 9 Q.6 5 I.6 9 t. 5 electrons flow to the right (x direction) eery microsecond ndrémarie mpère's 5 9 Q.6 I.6 9 t Slide Slide

4 Example : C cm Current Density Definition: rate of positie charge flow per unit area Symbol: J Units: / cm Wire attached to end cm cm Suppose we force a current of to flow from C to C: Electron flow is in x direction: C / sec C / electron 8 X Semiconductor with 8 free electrons per cm 3 C electrons sec Current Density Example (cont d) Example : Typical dimensions of integrated circuit components are in the range of µm. What is the current density in a wire with µm² area carrying 5 m? Slide 3 Slide 4 Electric Potential (oltage) Definition: energy per unit charge Symbol: Units: Joules/Coulomb olts () dw/dq where w energy (in Joules), q charge (in Coulombs) Note: Potential is always referenced to some point. a b lessandro olta (74587) Subscript conention: ab means the potential at a minus the potential at b. ab a b Electric Power Definition: transfer of energy per unit time Symbol: p Units: Joules per second Watts (W) Concept: p dw/dt (dw/dq)(dq/dt) i s a positie charge q moes through a drop in oltage, it loses energy energy change q rate is proportional to # charges/sec James Watt Slide 5 Slide 6

5 _ The Ideal asic Circuit Element i Polarity reference for oltage can be indicated by plus and minus signs eference direction for the current is indicated by an arrow Note about eference Directions problem like Find the current or Find the oltage is always accompanied by a definition of the direction: i ttributes: Two terminals (points of connection) Mathematically described in terms of current and/or oltage Cannot be subdiided into other elements In this case, if the current turns out to be m flowing to the left, we would say i m. In order to perform circuit analysis to determine the oltages and currents in an electric circuit, you need to specify reference directions. There is no need to guess the reference direction so that the answers come out positie. Slide 7 Slide 8 Sign Conention Example Suppose you hae an unlabelled battery and you measure its oltage with a digital oltmeter (DM). It will tell you the magnitude and sign of the oltage. Find ab, ca, cb nother Example a c cd a.4 DM With this circuit, you are measuring ab. The DM indicates.4, so a is lower than b by.4. b bd d b Which is the positie battery terminal? Note that we hae used the ground symbol ( ) for the reference node on the DM. Often it is labeled C for common. Note that the labeling conention has nothing to do with whether or not is positie or negatie. Slide 9 Slide

6 Sign Conention for Power Power Passie sign conention _ i p i _ i _ i p i _ i If an element is absorbing power (i.e. if p > ), positie charge is flowing from higher potential to lower potential. p i if the passie sign conention is used: i i _ or _ If p >, power is being deliered to the box. If p <, power is being extracted from the box. How can a circuit element absorb power? y conerting electrical energy into heat (resistors in toasters), light (light bulbs), or acoustic energy (speakers); by storing energy (charging a battery). Slide Slide Power Calculation Example Find the power absorbed by each element: Conseration of energy total power deliered equals total power absorbed side: For electronics these are unrealistically large currents milliamperes or smaller is more typical i (W) p (W) Circuit Elements 5 ideal basic circuit elements: oltage source current source resistor inductor capacitor actie elements, capable of generating electric energy passie elements, incapable of generating electric energy Many practical systems can be modeled with just sources and resistors The basic analytical techniques for soling circuits with inductors and capacitors are similar to those for resistie circuits Slide 3 Slide 4

7 Electrical Sources n electrical source is a deice that is capable of conerting nonelectric energy to electric energy and ice ersa. Examples: battery: chemical electric dynamo (generator/motor): mechanical electric (Ex. gasolinepowered generator, onneille dam) Electrical sources can either delier or absorb power Ideal oltage Source Circuit element that maintains a prescribed oltage across its terminals, regardless of the current flowing in those terminals. oltage is known, but current is determined by the circuit to which the source is connected. The oltage can be either independent or dependent on a oltage or current elsewhere in the circuit, and can be constant or timearying. Deice symbols: s _ s µ x _ s ρ i x _ independent oltagecontrolled currentcontrolled Slide 5 Slide 6 Ideal Current Source Circuit element that maintains a prescribed current through its terminals, regardless of the oltage across those terminals. Current is known, but oltage is determined by the circuit to which the source is connected. The current can be either independent or dependent on a oltage or current elsewhere in the circuit, and can be constant or timearying. Deice symbols: i s i s α x i s β i x independent oltagecontrolled currentcontrolled Electrical esistance esistance: the ratio of oltage drop and current. The circuit element used to model this behaior is the resistor. Circuit symbol: Units: olts per mpere ohms (Ω) The current flowing in the resistor is proportional to the oltage across the resistor: i (Ohm s Law) where oltage (), i current (), and resistance (Ω) Georg Simon Ohm Slide 7 Slide 8

8 Electrical Conductance Conductance is the reciprocal of resistance. Symbol: G Units: siemens (S) or mhos ( ) Example: Consider an 8 Ω resistor. What is its conductance? Ω Short Circuit and Open Circuit Short circuit no oltage difference exists all points on the wire are at the same potential. Current can flow, as determined by the circuit Open circuit no current flows oltage difference can exist, as determined by the circuit Werner on Siemens 8689 Slide 9 Slide 3 Example: Power bsorbed by a esistor p i ( i )i i p i ( / ) / Note that p > always, for a resistor a resistor dissipates electric energy Example: a) Calculate the oltage g and current i a. b) Determine the power dissipated in the 8Ω resistor. More Examples re these interconnections permissible? This circuit connection is permissible. This is because the current sources can sustain any oltage across; Hence this is permissible. This circuit connection is NOT permissible. It iolates the KCL. Slide 3 Slide 3

9 Summary Current rate of charge flow i dq/dt oltage energy per unit charge created by charge separation Power energy per unit time Ideal asic Circuit Elements twoterminal component that cannot be subdiided described mathematically in terms of its terminal oltage and current n ideal oltage source maintains a prescribed oltage regardless of the current in the deice. n ideal current source maintains a prescribed current regardless of the oltage across the deice. resistor constrains its oltage and current to be proportional to each other: i (Ohm s law) Summary (cont d) Passie sign conention For a passie deice, the reference direction for current through the element is in the direction of the reference oltage drop across the element Slide 33 Slide 34 Current s. oltage (I) Characteristic oltage sources, current sources, and resistors can be described by plotting the current (i) as a function of the oltage () _ i Passie? ctie? I Characteristic of Ideal oltage Source a ab _ b i _ s i. Plot the I characteristic for s >. For what alues of i does the source absorb power? For what alues of i does the source release power?. epeat s > () i< for release s <. power; i> absorb power 3. What is the I characteristic for an ideal wire? i s > Slide 35 Slide 36

10 I Characteristic of Ideal oltage Source a ab _ b i _ s s < i I Characteristic of Ideal oltage Source a ab _ b i _ s i. Plot the I characteristic for s <. For what alues of i does the source absorb power? For what alues of i does the source release power? s < i> release power; i< absorb power 3. What is the I characteristic for an ideal wire? Do not forget ab ba Slide 37 Slide 38 I Characteristic of Ideal Current Source _ i i s. Plot the I characteristic for i s >. For what alues of does the source absorb power? For what alues of does the source release power? i Short Circuit and Open Circuit Wire ( short circuit ): no oltage difference exists (all points on the wire are at the same potential) Current can flow, as determined by the circuit ir ( open circuit ): no current flows oltage difference can exist, as determined by the circuit > absorb power; < release power Slide 39 Slide 4

11 a _ b I Characteristic of Ideal esistor i. Plot the I characteristic for kω. What is the slope? i More Examples: Correction from last Lec. re these interconnections permissible? This circuit connection is permissible. This is because the current sources can sustain any oltage across; Hence this is permissible. a ab _ ab a This circuit connection is NOT permissible. It iolates the KCL. b b Slide 4 Slide 4 Construction of a Circuit Model The electrical behaior of each physical component is of primary interest. Terminology: Nodes and ranches Node: point where two or more circuit elements are connected We need to account for undesired as well as desired electrical effects. Simplifying assumptions should be made whereer reasonable. ranch: path that connects two nodes Slide 43 Slide 44

12 Circuit Nodes and Loops node is a point where two or more circuit elements are connected. loop is formed by tracing a closed path in a circuit through selected basic circuit elements without passing through any intermediate node more than once Kirchhoff s Laws Kirchhoff s Current Law (KCL): The algebraic sum of all the currents entering any node in a circuit equals zero. Kirchhoff s oltage Law (KL): The algebraic sum of all the oltages around any loop in a circuit equals zero. Gusta obert Kirchhoff Slide 45 Slide 46 Notation: Node and ranch oltages Use one node as the reference (the common or ground node) label it with a symbol The oltage drop from node x to the reference node is called the node oltage x. The oltage across a circuit element is defined as the difference between the node oltages at its terminals Example: a b a c s Slide 47 b _ EFEENCE NODE Using Kirchhoff s Current Law (KCL) Consider a node connecting seeral branches: i i i 4 i 3 Use reference directions to determine whether currents are entering or leaing the node with no concern about actual current directions Slide 48

13 Formulations of Kirchhoff s Current Law Formulation : (Charge stored in node is zero.) Sum of currents entering node sum of currents leaing node Major Implication of KCL KCL tells us that all of the elements in a single branch carry the same current. We say these elements are connected in series. Formulation : lgebraic sum of currents entering node Currents leaing are included with a minus sign. Formulation 3: lgebraic sum of currents leaing node Currents entering are included with a minus sign. Slide 49 Current entering node Current leaing node i i Slide 5 KCL Example Generalization of KCL 5 m m i Currents entering the node: Currents leaing the node: The sum of currents entering/leaing a closed surface is zero. Circuit branches can be inside this surface, i.e. the surface can enclose more than one node! 5 m 3 formulations of KCL:.. 3. This could be a big chunk of a circuit, e.g. a black box i i i 3 i 4 Slide 5 Slide 5

14 Generalized KCL Examples 5 m Using Kirchhoff s oltage Law (KL) Consider a branch which forms part of a loop: i 5µ µ i loop _ Moing from to We add loop Moing from to We subtract Use reference polarities to determine whether a oltage is dropped No concern about actual oltage polarities Slide 53 Slide 54 Formulations of Kirchhoff s oltage Law (Conseration of energy) Formulation : Sum of oltage drops around loop sum of oltage rises around loop Formulation : lgebraic sum of oltage drops around loop oltage rises are included with a minus sign. (Handy trick: Look at the first sign you encounter on each element when tracing the loop.) Formulation 3: lgebraic sum of oltage rises around loop oltage drops are included with a minus sign. Slide 55 Major Implication of KL KL tells us that any set of elements which are connected at both ends carry the same oltage. We say these elements are connected in parallel. a_ b _ pplying KL in the clockwise direction, starting at the top: b a b a Slide 56

15 Three closed paths: Path : Path : Path 3: KL Example a 3 a b c b 3 c n Underlying ssumption of KL No timearying magnetic flux through the loop Otherwise, there would be an induced oltage (Faraday s Law) Note: ntennas are designed to pick up electromagnetic waes; regular circuits often do so undesirably. oid these loops! How do we deal with antennas (EECS 7)? (t) (t) Include a oltage source as the circuit representation of the induced oltage or noise. (Use a lumped model rather than a distributed (wae) model.) Slide 57 Slide 58 I Characteristic of Elements esistors in Series a ab _ b i _ s Find the I characteristic. i Consider a circuit with multiple resistors connected in series. Find their equialent resistance. SS I 3 KCL tells us that the same current (I) flows through eery resistor KL tells us 4 Equialent resistance of resistors in series is the sum Slide 59 Slide 6

16 oltage Diider When can the oltage Diider Formula be Used? SS I 3 3 I SS / ( 3 4 ) SS I 3 4 SS I SS 3 4 SS 3 4 Correct, if nothing else is connected to nodes Why? What is? Slide 6 Slide 6 I SS esistors in Parallel Consider a circuit with two resistors connected in parallel. Find their equialent resistance. I x I KL tells us that the same oltage is dropped across each resistor x I I KCL tells us General Formula for Parallel esistors What single resistance eq is equialent to three resistors in parallel? I 3 I eq eq Equialent conductance of resistors in parallel is the sum Slide 63 Slide 64

17 Current Diider x Generalized Current Diider Formula Consider a current diider circuit with > resistors in parallel: I SS I I x I I SS eq I I I I3 3 I 3 I 3 3 I / / / 3 / 3 Slide 65 Slide 66 Summary n electrical system can be modeled by an electric circuit (combination of paths, each containing or more circuit elements) Lumped model The Current ersus oltage characteristics (I plot) is a uniersal means of describing a circuit element. Kirchhoff s current law (KCL) states that the algebraic sum of all currents at any node in a circuit equals zero. Comes from conseration of charge Kirchhoff s oltage law (KL) states that the algebraic sum of all oltages around any closed path in a circuit equals zero. Comes from conseration of potential energy Summary (cont d) esistors in Series oltage Diider Conductances in Parallel Current Diider Slide 67 Slide 68

18 Week Outline Nodeoltage nalysis MeshCurrent nalysis Superposition Théenin equialent circuits Norton equialent circuits Maximum Power Transfer eading Chapter Measuring oltage To measure the oltage drop across an element in a real circuit, insert a oltmeter (digital multimeter in oltage mode) in parallel with the element. oltmeters are characterized by their oltmeter input resistance ( in ). Ideally, this should be ery high (typical alue MΩ) Ideal oltmeter in Slide 69 Slide 7 Effect of oltmeter Measuring Current SS undisturbed circuit circuit with oltmeter inserted _ Compare to SS in SS in Example: SS, K, 9K M,? in SS _ in To measure the current flowing through an element in a real circuit, insert an ammeter (digital multimeter in current mode) in series with the element. mmeters are characterized by their ammeter input resistance ( in ). Ideally, this should be ery low (typical alue Ω). Ideal mmeter in Slide 7 Slide 7

19 undisturbed circuit _ I I Effect of mmeter Measurement error due to nonzero input resistance: circuit with ammeter inserted Slide 73 I meas Example:, 5 Ω, in Ω I m, Imeas? 5Ω 5Ω _ in I meas in ammeter Compare to Simplify a circuit before applying KCL and/or KL: Example: Find I 7 Using Equialent esistances I Slide 74 3 kω 3 6 kω kω 6 kω Nodeoltage Circuit nalysis Method. Choose a reference node ( ground ) Look for the one with the most connections!. Define unknown node oltages those which are not fixed by oltage sources 3. Write KCL at each unknown node, expressing current in terms of the node oltages (using the I relationships of branch elements) Special cases: floating oltage sources 4. Sole the set of independent equations N equations for N unknown node oltages Nodal nalysis: Example #. Choose a reference node.. Define the node oltages (except reference node and the one set by the oltage source). 3. pply KCL at the nodes with unknown oltage. 3 I S 4. Sole for unknown node oltages. 4 Slide 75 Slide 76

20 Nodal nalysis: Example # 3 I a 5 4 Nodal nalysis w/ Floating oltage Source floating oltage source is one for which neither side is connected to the reference node, e.g. LL in the circuit below: a LL b I 4 I Challenges: Determine number of nodes needed Deal with different types of sources Slide 77 Problem: We cannot write KCL at nodes a or b because there is no way to express the current through the oltage source in terms of a b. Solution: Define a supernode that chunk of the circuit containing nodes a and b. Express KCL for this supernode. Incorporate oltage source constraint into KCL equation. Slide 78 Nodal nalysis: Example #3 I Eq n : KCL at supernode supernode 4 I Substitute property of oltage source: a LL Slide 79 b Formal Circuit nalysis Methods NODL NLYSIS ( Nodeoltage Method ) ) Choose a reference node ) Define unknown node oltages ) pply KCL to each unknown node, expressing current in terms of the node oltages > N equations for N unknown node oltages 3) Sole for node oltages > determine branch currents Slide 8 MESH NLYSIS ( MeshCurrent Method ) ) Select M independent mesh currents such that at least one mesh current passes through each branch* M #branches #nodes ) pply KL to each mesh, expressing oltages in terms of mesh currents > M equations for M unknown mesh currents 3) Sole for mesh currents > determine node oltages *Simple method for planar circuits mesh current is not necessarily identified with a branch current.

21 Mesh nalysis: Example # Mesh nalysis with a Current Source i a i b. Select M mesh currents.. pply KL to each mesh. 3. Sole for mesh currents. Problem: We cannot write KL for meshes a and b because there is no way to express the oltage drop across the current source in terms of the mesh currents. Solution: Define a supermesh a mesh which aoids the branch containing the current source. pply KL for this supermesh. Slide 8 Slide 8 Mesh nalysis: Example # i a i b Eq n : KL for supermesh Eq n : Constraint due to current source: Mesh nalysis with Dependent Sources Exactly analogous to Node nalysis Dependent oltage Source: () Formulate and write KL mesh eqns. () Include and express dependency constraint in terms of mesh currents Dependent Current Source: () Use supermesh. () Include and express dependency constraint in terms of mesh currents Slide 83 Slide 84

22 Circuit w/ Dependent Source Example Find i, i and i o Superposition linear circuit is one constructed only of linear elements (linear resistors, and linear capacitors and inductors, linear dependent sources) and independent sources. Linear means I charcteristic of elements/sources are straight lines when plotted Principle of Superposition: In any linear circuit containing multiple independent sources, the current or oltage at any point in the network may be calculated as the algebraic sum of the indiidual contributions of each source acting alone. Slide 85 Slide 86 Source Combinations oltage sources in series can be replaced by an equialent oltage source: Current sources in parallel can be replaced by an equialent current source: Superposition Procedure:. Determine contribution due to one independent source Set all other sources to : eplace independent oltage source by short circuit, independent current source by open circuit. epeat for each independent source 3. Sum indiidual contributions to obtain desired oltage or current i i i i Slide 87 Slide 88

23 Open Circuit and Short Circuit Superposition Example Open circuit i ; Cut off the branch Short circuit ; replace the element by wire Find o Ω 4 Turn off an independent oltage source means eplace by wire Short circuit Ω o Turn off an independent current source means i Cut off the branch open circuit Slide 89 Slide 9 Equialent Circuit Concept network of oltage sources, current sources, and resistors can be replaced by an equialent circuit which has identical terminal properties (I characteristics) without affecting the operation of the rest of the circuit. Théenin Equialent Circuit ny* linear terminal (port) network of indep. oltage sources, indep. current sources, and linear resistors can be replaced by an equialent circuit consisting of an independent oltage source in series with a resistor without affecting the operation of the rest of the circuit. i i Théenin equialent circuit network of sources and resistors _ i ( ) i ( ) network of sources and resistors _ network of sources and resistors a b L i L L Th Th a b L i L L load resistor Slide 9 Slide 9

24 I Characteristic of Théenin Equialent The I characteristic for the series combination of elements is obtained by adding their oltage drops: Théenin Equialent Example Find the Theenin equialent with respect to the terminals a,b: For a gien current i, the oltage drop ab is equal to the sum of the oltages dropped across the source ( Th ) and across the resistor (i Th ) Th Th i a ab I characteristic of resistor: i i ab Th i b I characteristic of oltage source: Th Slide 93 Slide 94 Th Calculation Example # Norton Equialent Circuit ny* linear terminal (port) network of indep. oltage sources, indep. current sources, and linear resistors can be replaced by an equialent circuit consisting of an independent current source in parallel with a resistor without affecting the operation of the rest of the circuit. Set all independent sources to : network of sources and resistors a b L i L L Norton equialent circuit i N N a b L i L L Slide 95 Slide 96

25 I Characteristic of Norton Equialent The I characteristic for the parallel combination of elements is obtained by adding their currents: For a gien oltage ab, the current i is equal to the sum of the currents in each of the two branches: i N N a ab b i I characteristic of resistor: ig i I characteristic of current source: i I N i I N G Finding I N and N Th nalogous to calculation of Theenin Eq. Ckt: ) Find o.c oltage and s.c. current I N i sc Th / Th ) Or, find s.c. current and Norton (The) resistance Slide 97 Slide 98 Finding I N and N We can derie the Norton equialent circuit from a Théenin equialent circuit simply by making a source transformation: Th Th a b L i L L i N N N Th i oc Th ; in isc sc Th a b L i L L Th Maximum Power Transfer Theorem Théenin equialent circuit dp dl Th L i L L p i ( Th L ) L ( Th L ) Th 4 ( Th L ) ( ) ( ) Th Th L L Power absorbed by load resistor: L L Th L resistie load receies maximum power from a circuit if the load resistance equals the Théenin resistance of the circuit. L Th Th dp To find the alue of L for which p is maximum, set to : d L L L Slide 99 Slide

26 Week 3 (Lec 3.3.) Outline Wheatstone ridge DeltaY Conersion Dependent Sources Potential plots for resistie circuits The capacitor The inductor eading Chap. and Chap. 3 The Wheatstone ridge Circuit used to precisely measure resistances in the range from Ω to MΩ, with ±.% accuracy and are resistors with known alues 3 is a ariable resistor (typically to,ω) x is the resistor whose alue is to be measured battery ariable resistor 3 x current detector Slide Slide Finding the alue of x djust 3 until there is no current in the detector Finding the alue of x djust 3 until there is no current in the detector Then, x 3 Deriation: Then, x 3 Deriation: KCL > i i 3 and i i x KL > i 3 3 i x x and i i 3 i i i 3 i x x 3 i i i 3 i x x i 3 i x Typically, / can be aried from. to in decimal steps Typically, / can be aried from. to in decimal steps 3 x Slide 3 Slide 4

27 Identifying Series and Parallel Combinations Some circuits must be analyzed (not amenable to simple inspection) I 4 3 YDelta Conersion These two resistie circuits are equialent for oltages and currents external to the Y and circuits. Internally, the oltages and currents are different. a c b a b Special cases: 3 O 3 5 b c a c 3 b c a b c a c a b c 3 a b a b c rain Teaser Category: Important for motors and electrical utilities. Slide 5 Slide 6 DeltatoWye (PitoTee) Equialent Circuits In order for the Delta interconnection to be equialent to the Wye interconnection, the resistance between corresponding terminal pairs must be the same Y and Y Conersion Formulas DeltatoWye conersion WyetoDelta conersion a b c a b c ( a b ) ab a b c b c a b c a b c a b a 3 3 a c 3 b a ( b c ) bc 3 a b c b ( a c ) ca 3 a b c 3 a c a b c a b a b c a c 3 b b 3 3 c c c Slide 7 Slide 8

28 Circuit Simplification Example Dependent Sources Find the equialent resistance ab : Ω a 8Ω Ω 6Ω 9Ω 4Ω b Ω a 9Ω b 4Ω Nodeoltage Method Dependent current source: treat as independent current source in organizing node eqns substitute constraining dependency in terms of defined node oltages. Dependent oltage source: treat as independent oltage source in organizing node eqns Substitute constraining dependency in terms of defined node oltages. Mesh nalysis Dependent oltage Source: Formulate and write KL mesh eqns. Include and express dependency constraint in terms of mesh currents Dependent Current Source: Use supermesh. Include and express dependency constraint in terms of mesh currents Slide 9 Slide Comments on Dependent Sources dependent source establishes a oltage or current whose alue depends on the alue of a oltage or current at a specified location in the circuit. (deice model, used to model behaior of transistors & amplifiers) To specify a dependent source, we must identify:. the controlling oltage or current (must be calculated, in general). the relationship between the controlling oltage or current and the supplied oltage or current 3. the reference direction for the supplied oltage or current The relationship between the dependent source and its reference cannot be broken! Dependent sources cannot be turned off for arious purposes (e.g. to find the Théenin resistance, or in analysis using Superposition). Slide Nodeoltage Method and Dependent Sources If a circuit contains dependent sources, what to do? Example:.4 Ω Slide i Ω Ω 5i 8

29 Th Calculation Example # Find the Theenin equialent with respect to the terminals a,b: Circuit w/ Dependent Source Example Find i, i and i o Slide 3 Slide 4 Summary of Techniques for Circuit nalysis (Chap ) esistor network Parallel resistors Series resistors Ydelta conersion dd current source and find oltage (or ice ersa) Superposition Leae one independent source on at a time Sum oer all responses oltage off SC Current off OC Summary of Techniques for Circuit nalysis (Chap ) Node nalysis Node oltage is the unknown Sole for KCL Floating oltage source using super node Mesh nalysis Loop current is the unknown Sole for KL Current source using super mesh Theenin and Norton Equialent Circuits Sole for OC oltage Sole for SC current Slide 5 Slide 6

30 Open Circuit and Short Circuit Open circuit i ; Cut off the branch Short circuit ; replace the element by wire Turn off an independent oltage source means eplace by wire Short circuit Turn off an independent current source means i Cut off the branch open circuit Potential Plots for a Single esistor and Two esistors in Series (Potential is Plotted ertically) rrows represent oltage drops Slide 7 Slide 8 Potential Plot for Two esistors in Parallel The Capacitor Two conductors (a,b) separated by an insulator: difference in potential ab > equal & opposite charge Q on conductors Q C ab (stored charge in terms of oltage) where C is the capacitance of the structure, positie () charge is on the conductor at higher potential rrows represent oltage drops Parallelplate capacitor: area of the plates (m ) separation between plates d (m) dielectric permittiity of insulator ε (F/m) ε C F(F) > capacitance d Slide 9 Slide

31 Symbol: Capacitor Units: Farads (Coulombs/olt) or (typical range of alues: pf to µf; for supercapacitors up to a few F!) Currentoltage relationship: i dq dt C d C dt c c c dc dt If C (geometry) is unchanging, i C C d C /dt C i c Electrolytic (polarized) capacitor c C Q( t) oltage in Terms of Current t c c ( t) C i ( t) dt Q() t Q() ic ( t) dt C C t i ( t) dt () Uses: Capacitors are used to store energy for camera flashbulbs, in filters that separate arious frequency signals, and they appear as undesired parasitic elements in circuits where they usually degrade circuit performance c c Note: Q ( c ) must be a continuous function of time Slide Slide Stored Energy more rigorous deriation CPCITOS STOE ELECTIC ENEGY You might think the energy stored on a capacitor is Q C, which has the dimension of Joules. ut during charging, the aerage oltage across the capacitor was only half the final alue of for a linear capacitor. This deriation holds independent of the circuit! i c c Q C Thus, energy is. Example: pf capacitance charged to 5 olts has ½(5) (pf).5 pj ( 5F supercapacitor charged to 5 olts stores 63 J; if it discharged at a constant rate in ms energy is discharged at a 63 kw rate!) t t w t t Final Initial w C Final c Initial c i c d c dt C Final Final c Initial dq dt dt C Initial Final c Initial dq Slide 3 Slide 4

32 Example: Current, Power & Energy for a Capacitor () i (µ) ( t) i( ) d () C τ τ d i C dt t t (µs) t (µs) (t) µf i(t) c and q must be continuous functions of time; howeer, i c can be discontinuous. Note: In steady state (dc operation), time deriaties are zero C is an open circuit p (W) w (J) t (µs) t (µs) (t) µf i(t) p i t w pd τ C Slide 5 Slide 6 Capacitors in Series Capacitie oltage Diider i(t) (t) C (t) C Slide 7 i(t) C eq C C C eq (t) (t) (t) Q: Suppose the oltage applied across a series combination of capacitors is changed by. How will this affect the oltage across each indiidual capacitor? Q C Q Q C Q Q Slide 8 Note that no net charge can can be introduced to this node. Therefore, Q Q Q Q C C C (t) C Q Q C C Q C Note: Capacitors in series hae the same incremental charge.

33 Practical Capacitors capacitor can be constructed by interleaing the plates with two dielectric layers and rolling them up, to achiee a compact size. Symbol: L Inductor Units: Henrys (olts second / mpere) (typical range of alues: µh to H) To achiee a small olume, a ery thin dielectric with a high dielectric constant is desirable. Howeer, dielectric materials break down and become conductors when the electric field (units: /cm) is too high. eal capacitors hae maximum oltage ratings n engineering tradeoff exists between compact size and high oltage rating Current in terms of oltage: di i L L L L t t ( t) dt ( t) L ( τ ) dτ i( t) L L Note: i L must be a continuous function of time i L Slide 9 Slide 3 Stored Energy INDUCTOS STOE MGNETIC ENEGY Consider an inductor haing an initial current i(t ) i p( t) ( t) i( t) Inductors in Series and Parallel Common Current w( t) w( t) t p( τ ) dτ t Li Li Common oltage Slide 3 Slide 3

34 Mutual Inductance i M i L L di di L M dt dt di di M L dt dt Example: Transformer % flux linkage N turns N turns Slide 33 / N /N Capacitor d i C dt w C cannot change instantaneously i can change instantaneously Do not shortcircuit a charged capacitor (> infinite current!) n n cap. s in series: C C n cap. s in parallel: C eq eq Summary i n i C i i Slide 34 Inductor i cannot change instantaneously can change instantaneously Do not opencircuit an inductor with current (> infinite oltage!) n ind. s in series: di L dt w Li n ind. s in parallel: L eq L eq n i n i L i L i Summary Steadystate nothing is time arying. In steady state, an inductor behaes like a short circuit In steady state, a capacitor behaes like an open circuit Chapter 4 (Lec. 33 to 5) OUTLINE First Order Circuits C and L Examples General Procedure C and L Circuits with General Sources Particular and complementary solutions Time constant Second Order Circuits The differential equation Particular and complementary solutions The natural frequency and the damping ratio eading Chapter 4 Slide 35 Slide 36

35 s FirstOrder Circuits circuit that contains only sources, resistors and an inductor is called an L circuit. circuit that contains only sources, resistors and a capacitor is called an C circuit. L and C circuits are called firstorder circuits because their oltages and currents are described by firstorder differential equations. i L s i C esponse of a Circuit Transient response of an L or C circuit is ehaior when oltage or current source are suddenly applied to or remoed from the circuit due to switching. Temporary behaior Steadystate response (aka. forced response) esponse that persists long after transient has decayed Natural response of an L or C circuit is ehaior (i.e., current and oltage) when stored energy in the inductor or capacitor is released to the resistie part of the network (containing no independent sources). Slide 37 Slide 38 Natural esponse Summary First Order Circuits L Circuit i L C Circuit C s (t) r (t) C i c (t) c(t) i s (t) L i L (t) L (t) Inductor current cannot change instantaneously In steady state, an inductor behaes like a short circuit. Capacitor oltage cannot change instantaneously In steady state, a capacitor behaes like an open circuit KL around the loop: r (t) c (t) s (t) dc ( t) C c ( t) s ( t) dt KCL at the node: t ( t) ( x) dx i L L dil ( t) il ( t) is ( t) dt s ( t) Slide 39 Slide 4

36 Procedure for Finding Transient esponse. Identify the ariable of interest For L circuits, it is usually the inductor current i L (t) For C circuits, it is usually the capacitor oltage c (t). Determine the initial alue (at t t and t ) of the ariable ecall that i L (t) and c (t) are continuous ariables: i L (t ) i L (t ) and c (t ) c (t ) ssuming that the circuit reached steady state before t, use the fact that an inductor behaes like a short circuit in steady state or that a capacitor behaes like an open circuit in steady state Procedure (cont d) 3. Calculate the final alue of the ariable (its alue as t ) gain, make use of the fact that an inductor behaes like a short circuit in steady state (t ) or that a capacitor behaes like an open circuit in steady state (t ) 4. Calculate the time constant for the circuit τ L/ for an L circuit, where is the Théenin equialent resistance seen by the inductor τ C for an C circuit where is the Théenin equialent resistance seen by the capacitor Slide 4 Slide 4 Natural esponse of an C Circuit Soling for the oltage (t ) Consider the following circuit, for which the switch is closed for t <, and then opened at t : For t >, the circuit reduces to i o t o o C Notation: is used to denote the time just prior to switching is used to denote the time immediately after switching o pplying KCL to the C circuit: C The oltage on the capacitor at t is o Solution: ( t) () e t / C Slide 43 Slide 44

37 Soling for the Current (t > ) Soling for Power and Energy Deliered (t > ) o Note that the current changes abruptly: i( ) o for t >, i( t) e o i( ) o C i Slide 45 t / C t e t / C ( ) o o p w t o o e p( x) dx C o t / C t C o e t / C ( e ) x / C i dx Slide 46 t e t / C ( ) o Natural esponse of an L Circuit Consider the following circuit, for which the switch is closed for t <, and then opened at t : I o o t i Notation: is used to denote the time just prior to switching is used to denote the time immediately after switching t< the entire system is at steadystate; and the inductor is like short circuit The current flowing in the inductor at t is I o and across is. L Soling for the Current (t ) For t >, the circuit reduces to I o pplying KL to the L circuit: (t)i(t) t t, ii, t arbitrary t>, ii(t) and ( t) Solution: o i( t) i() e L ( / L) t di( t) L dt i I e (/L)t Slide 47 Slide 48

38 I o Soling for the oltage (t > ) o Note that the oltage changes abruptly: ( ) for t >, ( t) i I ( ) I o Slide 49 L e i( t) I o e ( / L) t ( / L) t Soling for Power and Energy Deliered (t > ) p i w t I o I o o e p( x) dx LI ( / L) t t I o e o ( / L) t ( e ) ( / L) x Slide 5 L dx i t I e ( / L) t ( ) o L Natural esponse Summary L Circuit Inductor current cannot change instantaneously i( ) i( i( t) i() e time constant i ) t /τ τ L Slide 5 C C Circuit Capacitor oltage cannot change instantaneously ( time constant ) ( ( t) () e ) t /τ τ C We compute with pulses. We send beautiful pulses in: ut we receie lousylooking pulses at the output: Eery node in a real circuit has capacitance; it s the charging of these capacitances that limits circuit performance (speed) Digital Signals Capacitor charging effects are responsible! Slide 5 oltage oltage time time

39 Circuit Model for a Logic Gate Pulse Distortion ecall (from Lecture ) that electronic building blocks referred to as logic gates are used to implement logical functions (NND, NO, NOT) in digital ICs ny logical function can be implemented using these gates. logic gate can be modeled as a simple C circuit: in (t) C out The input oltage pulse width must be large enough; otherwise the output pulse is distorted. (We need to wait for the output to reach a recognizable logic leel, before changing the input again.) in (t) C switches between low (logic ) and high (logic ) oltage states out Time out Pulse width.c Time out Pulse width C out Pulse width C Time Slide 53 Slide 54 Example Suppose a oltage pulse of width 5 µs and height 4 is applied to the input of this circuit beginning at t : τ C.5 µs in.5 kω C nf First, out will increase exponentially toward 4. out When in goes back down, out will decrease exponentially back down to. What is the peak alue of out? The output increases for 5 µs, or time constants. It reaches e or 86% of the final alue..86 x is the peak alue C s (t) First Order Circuits: Forced esponse r (t) C KL around the loop: r (t) c (t) s (t) i c (t) dc ( t) C c ( t) s ( t) dt c(t) i s (t) L KCL at the node: t ( t) ( x) dx i L i L (t) L dil ( t) il ( t) is ( t) dt s L (t) ( t) Slide 55 Slide 56

40 Complete Solution oltages and currents in a st order circuit satisfy a differential equation of the form dx( t) x( t) τ f ( t) dt f(t) is called the forcing function. The complete solution is the sum of particular solution (forced response) and complementary solution (natural response). x( t) x ( t) x ( t) Particular solution satisfies the forcing function Complementary solution is used to satisfy the initial conditions. The initial conditions determine the alue of K. dxp ( t) xp ( t) τ f ( t) dt p c dxc ( t) xc ( t) τ dt t / xc ( t) Ke τ Slide 57 Homogeneous equation The Time Constant The complementary solution for any st order circuit is t / xc ( t) Ke τ For an C circuit, τ C For an L circuit, τ L/ Slide 58 What Does X c (t) Look Like? t x ( ) / c t e τ τ 4 τ is the amount of time necessary for an exponential to decay to 36.7% of its initial alue. /τ is the initial slope of an exponential with an initial alue of. The Particular Solution The particular solution x p (t) is usually a weighted sum of f(t) and its first deriatie. If f(t) is constant, then x p (t) is constant. If f(t) is sinusoidal, then x p (t) is sinusoidal. Slide 59 Slide 6

41 The Particular Solution: F(t) Constant Guess a solution x P ( t) t Equation holds for all time and time ariations are independent and thus each time ariation coefficient is indiidually zero dxp ( t) x ( t) τ dt P F d( t) ( t) τ F dt ( t) τ F ( τ F) ( ) t ( ) ( τ F) F The Particular Solution: F(t) Sinusoid Guess a solution x P ( t) sin( wt) cos( wt) dxp ( t) xp ( t) τ F sin( wt) F cos( wt) dt d( sin( wt) cos( wt)) ( sin( wt) cos( wt)) τ F sin( wt) F cos( wt) dt ( τ F )sin( wt) ( τ F )cos( wt) Equation holds for all time and time ariations are independent and thus each time ariation coefficient is indiidually zero ( τ F ) ( τ F ) F τf τ τf F τ Slide 6 Slide 6 The Particular Solution: F(t) Exp. The Total Solution: F(t) Sinusoid Guess a solution x ( t) e P αt Equation holds for all time and time ariations are independent and thus each time ariation coefficient is indiidually zero ( ατ F ) ατ F dxp ( t) αt xp ( t) τ F e F dt αt αt d( e ) αt ( e ) τ F e F dt αt αt αt ( e ) ατe F e F αt F ) ( ατ F ) e ( ( F ) F x P ( t) sin( wt) cos( wt) x ( t) Ke C T t τ dxp ( t) xp ( t) τ F sin( wt) F cos( wt) dt x ( t) sin( wt) cos( wt) Ke Only K is unknown and is determined by the initial condition at t x () sin() cos() Ke T x ( ) K ( t ) T C t τ Example: x T (t) C (t) τ F τf τ C ( t ) τf F τ K C ( t ) Slide 63 Slide 64

42 Example t s C c Gien c ( ), s cos(ωt), ω. Find i(t), c (t)? nd Order Circuits ny circuit with a single capacitor, a single inductor, an arbitrary number of sources, and an arbitrary number of resistors is a circuit of order. ny oltage or current in such a circuit is the solution to a nd order differential equation. Slide 65 Slide 66 nd Order LC Circuit s (t) i (t) pplication: Filters bandpass filter such as the IF amp for the M radio. lowpass filter with a sharper cutoff than can be obtained with an C circuit. L C The Differential Equation KL around the loop: i (t) s (t) r (t) c (t) l (t) s (t) t r (t) l (t) di( t) i( t) i( x) dx L s ( t) C dt di( t) d i( t) ds ( t) i( t) L dt LC dt L dt L C c (t) Slide 67 Slide 68

43 The Differential Equation The oltage and current in a second order circuit is the solution to a differential equation of the following form: d x t ( ) dx( t) α ω x( t) f ( t) dt dt x( t) x ( t) x ( t) p c X p (t) is the particular solution (forced response) and X c (t) is the complementary solution (natural response). The Particular Solution The particular solution x p (t) is usually a weighted sum of f(t) and its first and second deriaties. If f(t) is constant, then x p (t) is constant. If f(t) is sinusoidal, then x p (t) is sinusoidal. Slide 69 Slide 7 The Complementary Solution The complementary solution has the following form: x ( t) Ke c K is a constant determined by initial conditions. s is a constant determined by the coefficients of the differential equation. st st d Ke dke st α ω Ke dt dt s Ke α ske ω Ke st st st s α s ω st Characteristic Equation To find the complementary solution, we need to sole the characteristic equation: s ζω s ω α ζω The characteristic equation has two rootscall them s and s. x ( t) K e K e c s t s t s ζω ω ζ s ζω ω ζ Slide 7 Slide 7

44 Damping atio and Natural Frequency α ζ ω damping ratio s ζω ω ζ s ζω ω ζ Oerdamped : eal Unequal oots If ζ >, s and s are real and not equal. i c ( t) K e ςω ω ς t K e ςω ω ς t The damping ratio determines what type of solution we will get: Exponentially decreasing (ζ >) Exponentially decreasing sinusoid (ζ < ) The natural frequency is ω It determines how fast sinusoids wiggle. i(t) e6 t i(t) e6. t Slide 73 Slide 74 Underdamped: Complex oots If ζ <, s and s are complex. Define the following constants: ωd ω ζ α ζω ( ω ω ) x ( t) e cos t sin t αt c d d i(t) e5..e5 3.E t Slide 75 Critically damped: eal Equal oots If ζ, s and s are real and equal. x ( t) K e K te c ςω t Slide 76 ςω t Note: The degeneracy of the roots results in the extra factor of t

45 Example For the example, what are ζ and ω? i (t) d i( t) di( t) ds ( t) i( t) Ω dt L dt LC L dt 769pF d xc ( t) dxc ( t) ζω ω xc ( t) dt dt 59µH C ω, ζω, ζ LC L L ζ. Example ω π455 Is this system oer damped, under damped, or critically damped? What will the current look like? i(t) e5..e5 3.E t Slide 77 Slide 78 Slightly Different Example Increase the resistor to kω What are ζ and ω? s (t) i (t) kω 769pF 59µH ζ. ω π455 Slide 79 i(t) e6 t Types of Circuit Excitation Linear Time Inariant Circuit SteadyState Excitation (DC SteadyState) Linear Time Inariant Circuit Sinusoidal (Single Frequency) Excitation C SteadyState Slide 8 Digital Pulse Source Linear Time Inariant Circuit O Linear Time Inariant Circuit Transient Excitation

46 Signal () elatie mplitude signal Signal () signal Signal () Why is SingleFrequency Excitation Important? Some circuits are drien by a singlefrequency sinusoidal source. Some circuits are drien by sinusoidal sources whose frequency changes slowly oer time. You can express any periodic electrical signal as a sum of singlefrequency sinusoids so you can analyze the response of the (linear, timeinariant) circuit to each indiidual frequency component and then sum the responses to get the total response. This is known as Fourier Transform and is tremendously important to all kinds of engineering disciplines! Slide 8 c a epresenting a Square Wae as a Sum of Sinusoids b d Slide 8 T i me (ms) Frequency (Hz) (a)square wae with second period. (b) Fundamental component (dotted) with second period, thirdharmonic (solid black) with/3second period, and their sum (blue). (c) Sum of first ten components. (d) Spectrum with terms. SteadyState Sinusoidal nalysis lso known as C steadystate ny steady state oltage or current in a linear circuit with a sinusoidal source is a sinusoid. This is a consequence of the nature of particular solutions for sinusoidal forcing functions. ll C steady state oltages and currents hae the same frequency as the source. In order to find a steady state oltage or current, all we need to know is its magnitude and its phase relatie to the source We already know its frequency. Usually, an C steady state oltage or current is gien by the particular solution to a differential equation. SteadyState Sinusoidal nalysis lso known as C steadystate ny steady state oltage or current in a linear circuit with a sinusoidal source is a sinusoid. This is a consequence of the nature of particular solutions for sinusoidal forcing functions. ll C steady state oltages and currents hae the same frequency as the source. In order to find a steady state oltage or current, all we need to know is its magnitude and its phase relatie to the source We already know its frequency. Usually, an C steady state oltage or current is gien by the particular solution to a differential equation. Slide 83 Slide 84

47 Chapter 5 (Lec ) OUTLINE Phasors as notation for Sinusoids rithmetic with Complex Numbers Complex impedances Circuit analysis using complex impdenaces Deratie/Integration as multiplication/diision Phasor elationship for Circuit Elements eading Chap 5 ppendix t Example : nd Order LC Circuit s C L Slide 85 Slide 86 t Example : nd Order LC Circuit s C L Slide 87 Why is SingleFrequency Excitation Important? Some circuits are drien by a singlefrequency sinusoidal source. Some circuits are drien by sinusoidal sources whose frequency changes slowly oer time. You can express any periodic electrical signal as a sum of singlefrequency sinusoids so you can analyze the response of the (linear, timeinariant) circuit to each indiidual frequency component and then sum the responses to get the total response. This is known as Fourier Transform and is tremendously important to all kinds of engineering disciplines! Slide 88

48 Signal () elatie mplitude signal Signal () signal Signal () c a epresenting a Square Wae as a Sum of Sinusoids b d Slide 89 T i me (ms) Frequency (Hz) (a)square wae with second period. (b) Fundamental component (dotted) with second period, thirdharmonic (solid black) with/3second period, and their sum (blue). (c) Sum of first ten components. (d) Spectrum with terms. SteadyState Sinusoidal nalysis lso known as C steadystate ny steady state oltage or current in a linear circuit with a sinusoidal source is a sinusoid. This is a consequence of the nature of particular solutions for sinusoidal forcing functions. ll C steady state oltages and currents hae the same frequency as the source. In order to find a steady state oltage or current, all we need to know is its magnitude and its phase relatie to the source We already know its frequency. Usually, an C steady state oltage or current is gien by the particular solution to a differential equation. Slide 9 Sinusoidal Sources Create Too Much lgebra Guess a solution x P ( t) sin( wt) cos( wt) dxp ( t) xp ( t) τ F sin( wt) F cos( wt) dt d( sin( wt) cos( wt)) ( sin( wt) cos( wt)) τ F sin( wt) F cos( wt) dt ( τ F )sin( wt) ( τ F )cos( wt) Two terms to be general Deraties ddition Equation holds for all time ( τ F) and time ariations are ( τ F ) independent and thus each F time ariation coefficient is τf τf F τ τ indiidually zero Phasors (ectors that rotate in the complex plane) are a cleer alternatie. Slide 9 y z imaginary axis Complex Numbers () j ( ) θ real x axis ectangular Coordinates Z x jy Polar Coordinates: Z z θ Exponential Form: Z jθ Z e ze jθ Slide 9 x is the real part y is the imaginary part z is the magnitude θ is the phase x z cosθ z x y Z z(cosθ j sin θ ) e j π j e 9 j y z sinθ θ tan y x

49 Euler s Identities Complex Numbers () j j e θ θ Z ze z θ e cosθ e sinθ e e jθ jθ jθ jθ e e j cosθ jθ jθ j sinθ θ θ cos sin Exponential Form of a complex number Z rithmetic With Complex Numbers To compute phasor oltages and currents, we need to be able to perform computation with complex numbers. ddition Subtraction Multiplication Diision (nd later use multiplication by jω to replace Diffrentiation Integration Slide 93 Slide 94 ddition ddition is most easily performed in rectangular coordinates: x jy z jw (x z) j(y w) ddition Imaginary xis eal xis Slide 95 Slide 96

50 Subtraction Subtraction is most easily performed in rectangular coordinates: x jy z jw Subtraction Imaginary xis (x z) j(y w) eal xis Slide 97 Slide 98 Multiplication Multiplication Multiplication is most easily performed in polar coordinates: M θ M φ Imaginary xis ( M M ) (θ φ) eal xis Slide 99 Slide

51 Diision Diision is most easily performed in polar coordinates: M θ M φ / ( M / M ) (θ φ) Diision Imaginary xis / eal xis Slide Slide rithmetic Operations of Complex Numbers dd and Subtract: it is easiest to do this in rectangular format dd/subtract the real and imaginary parts separately Multiply and Diide: it is easiest to do this in exponential/polar format Multiply (diide) the magnitudes dd (subtract) the phases Z Z z e z θ z cosθ jz sinθ jθ z e z θ z cosθ jz sinθ jθ Z Z ( z cosθ z cos θ ) j( z sinθ z sin θ ) Z Z ( z cosθ z cos θ ) j( z sinθ z sin θ ) Z Z ( z z ) e ( z z ) ( θ θ ) j( θ θ ) j θ θ Z / Z ( z / z ) e ( ) ( z / z ) ( θ θ ) Phasors ssuming a source oltage is a sinusoid timearying function (t) cos (ωt θ) We can write: j( ωt θ ) j( ωt θ ) ( t) cos( ωt θ ) e e e e jθ Define Phasor as e θ Similarly, if the function is (t) sin (ωt θ) π π j( ωt θ ) ( t) sin( ωt θ ) cos( ωt θ ) e e Phasor π ( θ ) Slide 3 Slide 4

52 Phasor: otating Complex ector jφ jwt t { e e } ( e j ω e ) ( t) cos( ωt φ) e Imaginary xis cos(ωtφ) otates at uniform angular elocity ωt eal xis The head start angle is φ. Complex Exponentials We represent a realalued sinusoid as the real part of a complex exponential after multiplying j t by e ω. Complex exponentials proide the link between time functions and phasors. llow deraties and integrals to be replaced by multiplying or diiding by jω make soling for C steady state simple algebra with complex numbers. Phasors allow us to express currentoltage relationships for inductors and capacitors much like we express the currentoltage relationship for a resistor. Slide 5 Slide 6 I elationship for a Capacitor Capacitor Impedance () i(t) C (t) i( t) C Suppose that (t) is a sinusoid: (t) e{ M e j(ωtθ) } Find i(t). d( t) dt i(t) d( t) i( t) C C (t dt ) j( ωt θ ) j( ωt θ ) ( t) cos( ωt θ ) e e d( t) C d j( ωt θ ) j( ωt θ ) C j( ωt θ ) j( ωt θ ) i( t) C e e j e e dt dt ω ωc e j( ωt θ ) e j( ωt θ ) π ω C sin( ω t θ ) ω C cos( ω t θ ) j θ π π Zc ( θ θ ) ( ) j I π ωc ωc ωc jωc I θ Slide 7 Slide 8

53 Capacitor Impedance () i(t) d( t) i( t) C C (t dt ) ( ) cos( ω θ ) e θ j( ωt θ ) t t e d( t) de dt dt ω I θ θ ( θ θ ) I I θ jωc jωc j( ωt θ ) j( ωt θ ) i( t) C e C e j Ce I Z c Phasor definition Example (t) cos(377t 3 ) C µf What is? What is I? What is i(t)? Slide 9 Slide Computing the Current Inductor Impedance Note: The differentiation and integration operations become algebraic operations i(t) L (t) ( t) L di( t) dt d jω dt dt jω jωl I Slide Slide

54 Example i(t) µ cos(π t 3 ) L µh What is I? What is? What is (t)? Slide 3 oltage 7 cos( ω t) Phase inductor current π π 7sin( ωt) 7 cos( ωt ) 7 capacitor current π π 7sin( ωt) 7 cos( ωt ) 7 Slide 4 Phasor Diagrams phasor diagram is just a graph of seeral phasors on the complex plane (using real and imaginary axes). phasor diagram helps to isualize the relationships between currents and oltages. Capacitor: I leads by 9 o Inductor: leads I by 9 o Impedance C steadystate analysis using phasors allows us to express the relationship between current and oltage using a formula that looks likes Ohm s law: I Z Z is called impedance. Slide 5 Slide 6

55 Some Thoughts on Impedance Impedance depends on the frequency ω. Impedance is (often) a complex number. Impedance allows us to use the same solution techniques for C steady state as we use for DC steady state. Example: Single Loop Circuit kω µf C f6 Hz, C? How do we find C? First compute impedances for resistor and capacitor: Z kω kω Z C /j (πf x µf).65kω 9 Slide 7 Slide 8 Impedance Example kω What happens when ω changes? C.65kΩ 9 kω µf C Now use the oltage diider to find C : C.65kΩ 9.65kΩ 9 kω C ω Find C Slide 9 Slide

56 Circuit nalysis Using Complex Impedances Suitable for C steady state. KL ( t) ( t) ( t) 3 ( ω θ ) ( ω θ ) ( ω θ ) cos t cos t cos t 3 3 e e e Phasor Form KL j( ωt θ ) j( ωt θ ) j( ωt θ3 ) e 3 e e e j( θ ) j( θ ) j( θ3 ) 3 3 Phasor Form KCL I I I3 Use complex impedances for inductors and capacitors and follow same analysis as in chap. SteadyState C nalysis 5m.µF kω Find (t) for ωπ 3 5m j53kω kω Slide Slide Find the Equialent Impedance Z eq 5m 3 ( j53) 53 9 Z eq j Z eq 468.Ω 6. 5m 468.Ω 6. IZ eq ( t).34 cos(π 3t 6. ) Change the Frequency 5m.µF kω Find (t) for ωπ 455 j3.5ω 5m kω Slide 3 Slide 4

57 Find an Equialent Impedance Series Impedance 5m Z eq Z eq ( j3.5) j3.5 Z eq 3.5Ω m 3.5Ω IZ eq 7.5m ( t) 7.5m cos(π 455t 89.8 ) Z Z Z 3 Z eq Z Z Z 3 For example: L L Z eq jω(l L ) Z eq C C jωc jωc Z eq Slide 5 Slide 6 Parallel Impedance SteadyState C Nodeoltage nalysis C Z Z Z 3 Z eq I sin(ωt) L I cos(ωt) /Z eq /Z /Z /Z 3 For example: Z L L eq L L jω ( L L ) Z eq C C jω( C C ) Nodal analysis or mesh? What are the nodes (or meshes)? What happens if the sources are at different frequencies? Slide 7 Slide 8

58 Theenin Equialent esistor I relationship i. I where is the resistance in ohms, phasor oltage, I phasor current (boldface indicates complex quantity) Capacitor I relationship i C Cd C /dt...phasor current I C phasor oltage C / capacitie impedance Z C: I C C /Z C where Z C /jωc, j () / and boldface indicates complex quantity Inductor I relationship L Ldi L /dt...phasor oltage L phasor current I L / inductie impedance Z L L I L Z L where Z L jωl, j () / and boldface indicates complex quantity f6 Hz TH OC kω µf C Z kω kω Z C /j (πf x µf).65kω 9 Z TH TH Z TH.65kΩ kΩ 9 kω kω.65kω 9 Z ZC kΩ 9 kω Slide 9 Slide 3 oot Mean Square (rms) alues rms alued defined as ssuming a sinusoid gies Using an identity gies Ealuating at limits gies MS MS T ( t) dt T m [ T sin(ωt θ ) sin(θ )] T ω w o T MS m t dt T cos ( ω θ ) o T m MS t dt T [ cos(ω θ )] o T period MS m Power: Instantaneous and Timeerage For a esistor The instantaneous power is The timeaerage power is PE T For an Impedance ( t) i The instantaneous power is The timeaerage power ist PE T The reactie power at ω is Q Im{ T ( t) p( t) ( t) i( t) T ( t) p( t) dt dt [ ( t) dt] T T ( t p ( t) ( t) i( t) T * rms I rms p( t) dt ( t) i( t) dt e{ T rms I * rms } P E Q T ( rms I rms ) } rms Slide 3 Slide 3

59 Maximum erage Power Transfer TH Z TH Maximum time aerage power occurs when Z * LOD Z TH This presents a resistie impedance to the source Z total ZTH Z Power transferred is P E Slide 33 Z LOD * TH * * e{ I } e{ } rms OUTLINE Chapter 6 (Lec ) Frequency esponse for Characterization symptotic Frequency ehaior Log magnitude s log frequency plot Phase s log frequency plot d scale Transfer function example eading Chap eader Chapter Slide 34 Power: Instantaneous and Timeerage For a esistor The instantaneous power is The timeaerage power is PE T For an Impedance ( t) i The instantaneous power is The timeaerage power ist PE T The reactie power at ω is Q Im{ T Slide 35 ( t) p( t) ( t) i( t) T ( t) p( t) dt dt [ ( t) dt] T T ( t p ( t) ( t) i( t) T * rms I rms p( t) dt ( t) i( t) dt e{ T rms I * rms } P E Q T ( rms I rms ) } rms Maximum erage Power Transfer TH Z TH Maximum time aerage power occurs when Z * LOD Z TH This presents a resistie impedance to the source Z total ZTH Z Power transferred is P E Slide 36 Z LOD * TH * * e{ I } e{ } rms

60 el and Decibel (d) bel (symbol ) is a unit of measure of ratios of power leels, i.e. relatie power leels. The name was coined in the early th century in honor of lexander Graham ell, a telecommunications pioneer. The bel is a logarithmic measure. The number of bels for a gien ratio of power leels is calculated by taking the logarithm, to the base, of the ratio. one bel corresponds to a ratio of :. log (P /P ) where P and P are power leels. The bel is too large for eeryday use, so the decibel (d), equal to., is more commonly used. d log (P /P ) d are used to measure Electric power, Gain or loss of amplifiers, Insertion loss of filters. Logarithmic Measure for Power To express a power in terms of decibels, one starts by choosing a reference power, P reference, and writing Power P in decibels log (P/P reference ) Exercise: Express a power of 5 mw in decibels relatie to watt. P (d) log (5 x 3 ) 3 d Exercise: Express a power of 5 mw in decibels relatie to mw. P (d) log (5) 7 d. dm to express absolute alues of power relatie to a milliwatt. dm log (power in milliwatts / milliwatt) mw dm mw dm Slide 37 Slide 38 Logarithmic Measures for oltage or Current From the expression for power ratios in decibels, we can readily derie the corresponding expressions for oltage or current ratios. Suppose that the oltage (or current I) appears across (or flows in) a resistor whose resistance is. The corresponding power dissipated, P, is / (or I ). We can similarly relate the reference oltage or current to the reference power, as P reference ( reference ) / or P reference (I reference ). Logarithmic Measures for oltage or Current Note that the oltage and current expressions are just like the power expression except that they hae as the multiplier instead of because power is proportional to the square of the oltage or current. Exercise: How many decibels larger is the oltage of a 9olt transistor battery than that of a.5olt battery? Let reference.5. The ratio in decibels is log (9/.5) log (6) 6 d. Hence, oltage, in decibels log (/ reference ) Current, I, in decibels log (I/I reference ) Slide 39 Slide 4

61 Logarithmic Measures for oltage or Current The gain produced by an amplifier or the loss of a filter is often specified in decibels. The input oltage (current, or power) is taken as the reference alue of oltage (current, or power) in the decibel defining expression: oltage gain in d log ( output / input ) Current gain in d log (I output /I input Power gain in d log (P output /P input ) Example: The oltage gain of an amplifier whose input is. m and whose output is.5 is log (.5/.x 3 ) 68 d. Slide 4 ode Plot Plot of magnitude of transfer function s. frequency oth x and y scale are in log scale Y scale in d Log Frequency Scale Decade atio of higher to lower frequency Octae atio of higher to lower frequency Slide 4 Frequency esponse Example Circuit The shape of the frequency response of the complex ratio of phasors OUT / IN is a conenient means of classifying a circuit behaior and identifying key parameters. IN T T C OUT OUT IN reak point Gain Low Pass OUT IN reak point Gain High Pass TransferFunction OUT IN Zc Z Z OUT c IN, Ohms Ohms C uf Frequency Frequency OUT IN (/ jwc) / jω C) ( jωc) FYI: These are log ratio s log frequency plots Slide 43 Slide 44

62 reak Point alues When dealing with resonant circuits it is conenient to refer to the frequency difference between points at which the power from the circuit is half that at the peak of resonance. Such frequencies are known as halfpower frequencies, and the power output there referred to the peak power (at the resonant frequency) is log (P halfpower /P resonance ) log (/) 3 d. symptotic ehaior of Transfer Functions atio of polynomials form IN OUT IN IN jω C jωd Low frequency asymptotic limit jω C jωd OUT jw C jωd ω High frequency asymptotic limit jω jωd OUT ω C D Special cases When > ω When C > ω When > ω When D > ω Slide 45 Slide 46 reak Points of Transfer Functions Log magnitude ersus log frequency plot atio of polynomials form OUT IN jω C jωd Numerator reak Point (slope change upward) Occurs when jω > ω z / Magnitude ω ω Denominator reak Point (slope change downward) Occurs when C jωd > ω p C/D FYI: z is for zero of the numerator and p is for zero of the denominator giing one oer zero or a pole. Filter design consists of specifying frequency locations of zeros and poles.. ω adian Frequency ω Slide 47 Slide 48

63 Phase ersus log frequency Example: Circuit in Slide #3 Magnitude Phase adian Frequency Magnitude. OUT IN ( j ω C ) w p /( C) ctual alue adian Frequency Ohms C uf j Slide 49 Slide 5 Example: Circuit in Slide #3 Phase ode Plot: Label as d Phase OUT IN ( jωc) adian Frequency 45 o ctual alue is Ohms C uf Phase{ } Phase{ } j 45 Magnitude in d 6 4 OUT IN ( jωc) w p /( C) adian Frequency Note: Magnitude in d log ( OUT / IN ) Ohms C uf Slide 5 Slide 5

64 Transfer Function Transfer function is a function of frequency Complex quantity oth magnitude and phase are function of frequency in Two Port filter network out out H( f ) out in H(f) H ( f ) θ in out ( θ θ ) in Filters Circuit designed to retain a certain frequency range and discard others Lowpass: pass low frequencies and reject high frequencies Highpass: pass high frequencies and reject low frequencies andpass: pass some particular range of frequencies, reject other frequencies outside that band Notch: reject a range of frequencies and pass all other frequencies Slide 53 Slide 54 Common Filter Transfer Function s. Freq FirstOrder Lowpass Filter H ( f ) H ( f ) Low Pass Frequency and Pass Frequency H ( f ) H ( f ) High Pass Frequency and eject Frequency C H(f) ( jωc) tan ( jωc) jωc ωc Let ω and f C π C H(f) H ( f ) θ H ( f ), tan f f f θ f / H ( f ) H ( f ) log ( )log 3 d H () ( ) C ( ωc ) C Slide 55 Slide 56

65 FirstOrder Highpass Filter FirstOrder Lowpass Filter H(f) f ( ωc) ( ) jωc π tan ( ωc) ( jωc) jωc ωc f f H ( f ) π, θ tan f f f / H ( f ) H ( f ) log ( )log 3 d H () C C H(f) jωl ωl Let ω and f L π L H(f) H ( f ) θ tan H ( f ), tan f f f θ f ωl L L Slide 57 Slide 58 FirstOrder Highpass Filter FirstOrder Filter Circuits jωl ωl H(f) jωl ωl Let ω and f L π L H(f) H ( f ) θ π L tan f f H ( f ) π, θ tan f f f f ωl L L S High Pass C H / ( /jωc) Low Pass H C (/jωc) / ( /jωc) S Low Pass L H / ( jωl) High Pass H L jωl / ( jωl) Slide 59 Slide 6

66 Change of oltage or Current with Change of Frequency One may wish to specify the change of a quantity such as the output oltage of a filter when the frequency changes by a factor of (an octae) or (a decade). For example, a singlestage C lowpass filter has at frequencies aboe ω /C an output that changes at the rate d per decade. Highfrequency asymptote of Lowpass filter The high frequency asymptote of magnitude ode plot assumes d/decade slope s f f H ( f ) f H ( f ) log d H ( f ) Slide 6 Slide 6 Lowfrequency asymptote of Highpass filter SecondOrder Filter Circuits s f f f f H ( f ) f f f f H ( f ) log d H (. f ) S and Pass Low Pass High Pass C L and eject Z /jωc jωl H P / Z H LP (/jωc) / Z H HP jωl / Z H H LP H HP The low frequency asymptote of magnitude ode plot assumes d/decade slope Slide 63 Slide 64

67 Series esonance Parallel esonance oltage diider OUT IN OUT IN OUT IN Z Z Z Z L jω L / jωc j( ωl / ωc) C IN Substitute branch elements rrange in resonance form Maximum when w /(LC) OUT esonance quality factor Q ωl atio of reactance to resistance Closely related to number of round trip cycles before /e decay. andwidth is f /Q dmittance OUT OUT I S Y Y Y Substitute branch elements S I jwc j ω L rrange in resonance form OUT L I IN I S j( ωc ) ωl Maximum I S / when w /(LC) C OUT esonance quality factor Q ωl atio of reactance to resistance Closely related to number of round trip cycles before /e decay. andwidth is f /Q Slide 65 Slide 66 OUTLINE Chapter 4 (Lec ) Opmp from Port locks Opmp Model and its Idealization Negatie Feedback for Stability Components around Opmp define the Circuit Function eading Chap 4 The Operational mplifier The operational amplifier ( op amp ) is a basic building block used in analog circuits. Its behaior is modeled using a dependent source. When combined with resistors, capacitors, and inductors, it can perform arious useful functions: amplification/scaling of an input signal sign changing (inersion) of an input signal addition of multiple input signals subtraction of one input signal from another integration (oer time) of an input signal differentiation (with respect to time) of an input signal analog filtering nonlinear functions like exponential, log, sqrt, etc Slide 67 Slide 68

68 High Quality Dependent Source In an mplifier Op mp Terminals MPLIFIE SYMOL Differential mplifier ( ) MPLIFIE MODEL Circuit Model in linear region i 3 signal terminals: inputs and output IC op amps hae additional terminals for DC power supplies Commonmode signal ( )/ Differential signal positie power supply depends only on input ( ) See the utility of this: this Model when used correctly mimics the behaior of an amplifier but omits the complication of the many many transistors and other components. Inerting input Noninerting input output negatie power supply Slide 69 Slide 7 Op mp Terminal oltages and Currents ll oltages are referenced to a common node. Current reference directions are into the op amp. i i i c common node (external to the op amp) i cc o i c o cc Model for Internal Operation is differential gain or open loop gain Ideal op amp i o Common mode gain ( ), cm d o cm cm d d Since ( ), o cm Circuit Model i i _ i o i o ( ) o Slide 7 Slide 7

69 Model and Feedback Opmp and Use of Feedback Negatie feedback connecting the output port to the negatie input (port ) Positie feedback connecting the output port to the positie input (port ) Circuit Model i i o i o i o _ ( ) ery highgain differential amplifier can function in an extremely linear fashion as an operational amplifier by using negatie feedback. IN Summing Point IN Negatie feedback Stabilizes the output Hambley Example pp. 644 for Power Steering i Circuit Model We can show that that for and i, IN Stable, finite, and independent of the properties of the OP MP! Slide 73 Slide 74 Negatie Feedback Familiar examples of negatie feedback: Thermostat controlling room temperature Drier controlling direction of automobile Photochromic lenses in eyeglasses Familiar examples of positie feedback: Microphone squawk in room sound system Mechanical bistability in light switches Thermonuclear reaction in Hbomb Fundamentally pushes toward stability Fundamentally pushes toward instability or bistability SummingPoint Constraint Check if under negatie feedback Small i result in large o Output o is connected to the inerting input to reduce i esulting in i Summingpoint constraint i i irtual short circuit Not only oltage drop is (which is short circuit), input current is This is different from short circuit, hence called irtual short circuit. Slide 75 Slide 76

70 Ideal Opmp nalysis Technique pplies only when Negatie Feedback is present in circuit! ssumption : The potential between the opamp input terminals, () (), equals zero. ssumption : The currents flowing into the opamp s two input terminals both equal zero. No Currents IN EXMPLE No Potential Difference Ideal Opnalysis: NonInerting mplifier Yes Negatie Feedback is present in this circuit! ssumption : The potential between the opamp input terminals, () (), equals zero. ssumption : The currents flowing into the opamp s two input terminals both equal zero. IN EXMPLE KCL with currents in only two branches IN appears here in in out out in Noninerting mplifier Slide 77 Slide 78 NonInerting mplifier Ideal oltage amplifier Closed loop gain in in, i i Use KCL t Node. _ L ( ) ( ) i o ( ) in Input impedance i o in in Ideal Opmp nalysis: Inerting mplifier oltage is Only two currents for KCL Yes Negatie Feedback is present in circuit! IN IN I OUT L OUT ( ) OUT in Inerting mplifier with reference oltage Slide 79 Slide 8

71 Negatie feedback checked Use summingpoint constraint i in _ Inerting mplifier Closed loop gain, i i Use KCL t Node. ( in ) ( out ) i o Input impedance o i in Ideal oltage source independent of load resistor L o in in oltage Follower _ ( ) ( ) i o ( ) in L Slide 8 Slide 8 Example Example in i 4 i 3 i 5 i i _ L 3 Switch is open, i i ( in ) i3 in i4 i5 ( ) i 5 in o, in in Slide 83 in i 4 i 3 i 5 i i _ L Switch is closed, i i 3 ( in ) ( ) i4 i 5 in o, in in Slide 84

72 Example Example (cont d) Design an analog front end circuit to an instrument system equires to work with 3 fullscale of input signals (by manual switch): ±, ±, ± For each input range, the output needs to be ± The input resistance is MΩ o ( ) Switch at c in Slide 85 in b a a b in Switch at b a b c a in Switch at a a b c c b a _ L M Ω in a b c Max ( ) a b a b ( ). a b c a b c a a. ( ). a b c a b c kω, 9 kω, 9kΩ a b c Switch at c Switch at b Switch at a 9 Slide 86 Summing mplifier Difference mplifier Slide 87 Slide 88

73 Integrator Differentiator Want o K indt Want What is the difference between: in C in C _ Slide 89 Slide 9 ridge mplifier pplication: Digitaltonalog Conersion in a x x (ε) _ a Slide 9 DC can be used to conert the digital representation of an audio signal into an analog oltage that is then used to drie speakers so that you can hear it! Weightedadder D/ conerter S4 K 8 S3 S S 4it D/ K 4K 8K (Transistors are used as electronic switches) 5K S closed if LS S " if next bit S3 " if " " S4 " if MS Slide 9 inary number (olts) MS LS nalog output

74 nalog Output () Characteristic of 4it DC Digital Input Slide 93 ctie Filter Contain few components Transfer function that is insensitie to component tolerance Easily adjusted equire a small spread of components alues llow a wide range of useful transfer functions Slide 94 ctie Filter Example ctie Filter Solution in 3 C C Slide 95 _ (k) f f o k ( ) ω ( in 3 ) ( 3 ) Use KCL t Node jωc ( 3 o ) o k ω C jω C k 3 Use KCL t Node j C in (3 ) Let ω / C o H ( ω ) in ω, H ( ω ) k DC gain k ω ω (3 k ) ω ω k ω ω, H ( ω ) 3 k k ω >> ω, H ( ω ) ω ω ω log H ( ω ) decays at a rate of 4 d / decade Slide 96

75 Cascaded ctie Filter Example Cascaded ctie Filter Solution in 3 C C _ 3 (k) f C f C _ (k ) f f o k k ω C jω C (3 k ) ω C jωc(3 k) in Let ω / C, ω / C o k k H ( ω) in ω ω ω ω (3 ) (3 ) ω ω ω ω ω, H ( ω) k k DC gain ω ω ω, H ( ) 3 k 3 k k k k k kk 4 ω >> ω, H ( ω) ω 4 ω ω ω log H ( ω) decays at a rate of 8 d / decade Slide 97 Slide 98 Chapter (Week ) OUTLINE Diode Current and Equation Some Interesting Circuit pplications Load Line nalysis Solar Cells, Detectors, Zener Diodes Circuit nalysis with Diodes Halfwae ectifier Clamps and oltage Doublers using Capacitors eading Hambley..8 Supplementary Notes Chapter In forward bias ( on pside) we hae almost unlimited flow (ery low resistance). Qualitatiely, the I characteristics must look like: In reerse bias ( on nside) almost no current can flow. Qualitatiely, the I characteristics must look like: I Characteristics The current is close to zero for any negatie bias I current increases rapidly with I F F Slide 99 Slide 3

76 Schematic Deice Diode Physical ehaior and Equation N type P type Qualitatie I characteristics: I positie, easy conduction negatie, no conduction I Symbol Quantitatie I characteristics: I I (e q kt ) In which kt/q is.6 and I O is a constant depending on diode area. Typical alues: to 6. Interestingly, the graph of this equation looks just like the figure to the left. nonideality factor n times kt/q is often included. I The pn Junction I s. Equation I characteristic of PN junctions In EECS 5, 3, and other courses you will learn why the I s. relationship for PN junctions is of the form I I (e q kt ) where I is a constant proportional to junction area and depending on doping in P and N regions, 9 q electronic charge.6, k is oltzman constant, and T is absolute temperature. KT q.6 at3 K, a typical alue for I is 5 We note that in forward bias, I increases exponentially and is in the µm range for oltages typically in the range of.6.8. In reerse bias, the current is essentially zero. Slide 3 Slide 3 Diode Ideal (Perfect ectifier) Model The equation I I q exp( ) kt 5 is graphed below for I Current in m Forward oltage in 5 5 The characteristic is described as a rectifier that is, a deice that permits current to pass in only one direction. (The hydraulic analog is a check alue.) Hence the symbol: I Simple Perfect ectifier Model If we can ignore the small forwardbias oltage drop of a diode, a simple effectie model is the perfect rectifier, whose I characteristic is gien below: I eerse bias Forward I, any <, any bias I > perfect rectifier Current (microamp) Diode LargeSignal Model (.7 Drop) forward bias () Improed LargeSignal Diode Model: If we choose not to ignore the small forwardbias oltage drop of a diode, it is a ery good approximation to regard the oltage drop in forward bias as a constant, about.7. the Large signal model results..7 eerse bias Forward I, any <.7, any bias I >.7 I The LargeSignal Diode Model I Slide 33 Slide 34

77 ssume the ideal (perfect rectifier) model. ectifier Circuit S (t) Peak Detector Circuit ssume the ideal (perfect rectifier) model. i (t) S (t) (t) t i (t) C C (t) i t rectified ersion of input waeform (t) Key Point: The capacitor charges due to one way current behaior of the diode. C (t) C t Slide 35 Slide 36 pnjunction eerse reakdown s the reerse bias oltage increases, the peak electric field in the depletion region increases. When the electric field exceeds a critical alue (E crit x 5 /cm), the reerse current shows a dramatic increase: reerse (leakage) current I D () Zener diode is designed to operate in the breakdown mode. reerse (leakage) current breakdown oltage D Zener Diode I D () forward current D () forward current breakdown oltage D D () Example: t s (t) D 5 o (t) integrated circuit Slide 37 Slide 38

78 Load Line nalysis Method. Graph the I relationships for the nonlinear element and for the rest of the circuit. The operating point of the circuit is found from the intersection of these two cures. Th Th I Th / Th Slide 39 I operating point Th The I characteristic of all of the circuit except the nonlinear element is called the load line Solar cell: Example of simple PN junction What is a solar cell? Deice that conerts sunlight into electricity How does it work? In simple configuration, it is a diode made of PN junction Incident light is absorbed by material Creates electronhole pairs that transport through the material through Diffusion (concentration gradient) Drift (due to electric field) Slide 3 PN Junction Diode Photooltaic (Solar) Cell I characteristics of the deice I qd kt D I S ( e ) in the dark I D () I D () optical with incident light Operating point The load line a simple resistor. I characteristics of a PN junction is gien by e I I exp( ) kt S I L where I s is the saturation intensity depending on band gap and doping of the material and I L is the photocurrent generated due to light Efficiency is defined as η I m. m FF * oc * I sc Light Intensity Light Intensity FF is the Fill Factor oc ( I m, I m ) sc oc Open circuit oltage I sc Short circuit current I mp, mp Current and oltage at maximum power Slide 3 Slide 3

79 Example : Photodiode Photodetector Circuit Using Load Line operating point in the dark n intrinsic region is placed between the ptype and ntype regions W j W iregion, so that most of the electronhole pairs are generated in the depletion region faster response time (~ GHz operation) I D () D () Th Th I s light shines on the photodiode, carriers are generated by absorption. These excess carriers are swept by the electric field at the junction creating drift current, which is same direction as the reerse bias current and hence negatie current. The current is proportional to light intensity and hence can proide a direct measurement of light intensity photodetector. operating points under different light conditions. Th I Th / Th s light intensity increases. Why? load line with incident light What happens when th is too large? Why use th? Slide 33 Slide 34 Circuit symbol I D Ideal Diode Model of PN Diode D I characteristic reerse bias I D () forward bias D () Switch model I D D LargeSignal Diode Model Circuit symbol I characteristic Switch model I D D I D () forward bias reerse bias D () Don I D Don D n ideal diode passes current only in one direction. n ideal diode has the following properties: when I D >, D when D <, I D Diode behaes like a switch: closed in forward bias mode open in reerse bias mode ULE : When I D >, D Don ULE : When D < Don, I D For a Si pn diode, Don.7 Diode behaes like a oltage source in series with a switch: closed in forward bias mode open in reerse bias mode Slide 35 Slide 36

80 Diode: Large Signal Model Use piecewise linear model How to nalyze Circuits with Diodes diode has only two states: forward biased: I D >, D (or.7 ) reerse biased: I D, D < (or.7 ) Procedure:. Guess the state(s) of the diode(s). Check to see if KCL and KL are obeyed. 3. If KCL and KL are not obeyed, refine your guess 4. epeat steps 3 until KCL and KL are obeyed. Example: s (t) (t) If s (t) >, diode is forward biased (else KL is disobeyed try it) If s (t) <, diode is reerse biased (else KL is disobeyed try it) Slide 37 Slide 38 Diode Logic: ND Gate Diode Logic: O Gate Diodes can be used to perform logic functions: Diodes can be used to perform logic functions: ND gate output oltage is high only if both and are high cc Inputs and ary between olts ( low ) and cc ( high ) etween what oltage leels does C ary? Inputs and ary between olts ( low ) and cc ( high ) etween what oltage leels does C ary? O gate output oltage is high if either (or both) and are high ND C OUT 5 EOC OUT 5 EOC O C Slope Shift.7 Up Slope Shift.7 Down 5 IN.7 5 IN Slide 39 Slide 3

81 Diode Logic: Incompatibility and Decay Diode Only Gates are asically Incompatible: ND gate output oltage is high only if both and are high cc O gate output oltage is high if either (or both) and are high Digital Logic: Diodes with Dependent Sources EE4 TTL (TransistorTransistor Logic EOC 5 OUT 5 Shift.7 Slope > ND C ND O C O D_ON.7 i βi EOC F In practice does not go below. 5 IN C ND High want ND >> O C ND Low want ND << O Signal Decays with each stage (Not regeneratie) Incase you are interested: True TTL has at least three dependent sources that are associated with the three bipolar transistors on which it is based. Slide 3 Slide 3 Deice Isolation using pn Junctions regions of ntype Si n n n n n ptype Si No current flows if oltages are applied between ntype regions, because two pn junctions are backtoback nregion nregion Why are pn Junctions Important for ICs? The basic building block in digital ICs is the MOS transistor, whose structure contains reersebiased diodes. pn junctions are important for electrical isolation of transistors located next to each other at the surface of a Si wafer. The junction capacitance of these diodes can limit the performance (operating speed) of digital circuits pregion > ntype regions isolated in ptype substrate and ice ersa Slide 33 Slide 34

82 Power Conersion Circuits Conerting C to DC Potential applications: Charging a battery ectifier Equialent circuit >.6, diode short circuit o I.6 <.6, diode open circuit o I m sin (ωt) o Slide 35 Slide 36 Halfwae ectifier Circuits HalfWae ectifier dding a capacitor: what does it do? m sin (ωt) C Current charging up capacitor Slide 37 Slide 38

83 Leel Shift Circuit oltage Doubler Circuit C C IN C OUT IN t IN C OUT IN C C OUT OUT Leel Shift Peak Detect t Once the capacitor is charged by the negatie most oltage the rest of the signal is shifted up by that amount. The final output is the peak to peak oltage of the input. Slide 39 Slide 33 Week OUTLINE asic Semiconductor Materials n and p doping andgap Gauss s Law Poisson Equation Depletion approximation Diode I characteristics Lasers and LEDs Solar Cells eading Supplementary Notes Chap 3 Conductors, Insulators and Semiconductors Solids with free electrons that is electrons not directly inoled in the interatomic bonding are the familiar metals (Cu, l, Fe, u, etc). Solids with no free electrons are the familiar insulators (glass, quartz crystals, ceramics, etc.) Silicon is an insulator, but at higher temperatures some of the bonding electrons can get free and make it a little conducting hence the term semiconductor Pure silicon is a poor conductor (and a poor insulator). It has 4 alence electrons, all of which are needed to bond with nearest neighbors. No free electrons. Slide 33 Slide 33

84 The Periodic Table III I Electronic onds in Silicon D picture of perfect crystal of pure silicon; double line is a SiSi bond with each line representing an electron Si ion (charge 4 q) Two electrons in each bond ctual structure is 3dimensional tetrahedral just like carbon bonding in organic and inorganic materials. Essentially no free electrons, and no conduction insulator Slide 333 Slide 334 How to get conduction in Si? Doping Silicon with Donors (ntype) We must either: ) Chemically modify the Si to produce free carriers (permanent) or Donors donate mobile electrons (and thus ntype silicon) Example: add arsenic (s) to the silicon crystal: ) Electrically induce them by the field effect (switchable) For the first approach controlled impurities, dopants, are added to Si: dd group elements (5 bonding electrons s four for Si), such as phosphorus or arsenic (Extra electrons produce free electrons for conduction.) or s Mobile electron donated by s ion dd group III elements (3 bonding electrons), such as boron Deficiency of electrons results in free holes Immobile (stuck) positiely charged arsenic ion after 5 th electron left The extra electron with s, breaks free and becomes a free electron for conduction Slide 335 Slide 336

85 Doping with cceptors (ptype) Group III element (boron, typically) is added to the crystal Immobile (stuck) negatie boron ion after accepting electron from neighboring bond Mobile hole contributed by ion and later path Doping Typical doping densities: 6 ~ 9 cm 3 tomic density for Si: 5 x atoms/cm 3 8 cm 3 is in 5, two persons in entire erkeley wearing a green hat Pn junction effect is like The hole which is a missing bonding electron, breaks free from the acceptor and becomes a roaming positie charge, free to carry current in the semiconductor. It is positiely charged. Slide 337 Slide 338 Shockley s Parking Garage nalogy for Conduction in Si Shockley s Parking Garage nalogy for Conduction in Si Twostory parking garage on a hill: Twostory parking garage on a hill: If the lower floor is full and top one is empty, no traffic is possible. nalog of an insulator. ll electrons are locked up. If one car is moed upstairs, it can moe ND THE HOLE ON THE LOWE FLOO CN MOE. Conduction is possible. nalog to warmedup semiconductor. Some electrons get free (and leae holes behind). Slide 339 Slide 34

86 Shockley s Parking Garage nalogy for Conduction in Si Twostory parking garage on a hill: Shockley s Parking Garage nalogy for Conduction in Si Twostory parking garage on a hill: If an extra car is donated to the upper floor, it can moe. Conduction is possible. nalog to Ntype semiconductor. (n electron donor is added to the crystal, creating free electrons). If a car is remoed from the lower floor, it leaes a HOLE which can moe. Conduction is possible. nalog to Ptype semiconductor. (cceptors are added to the crystal, consuming bonding electrons,creating free holes). Slide 34 Slide 34 Summary of n and ptype silicon Junctions of n and ptype egions Pure silicon is an insulator. t high temperatures it conducts weakly. If we add an impurity with extra electrons (e.g. arsenic, phosphorus) these extra electrons are set free and we hae a pretty good conductor (ntype silicon). pn junctions form the essential basis of all semiconductor deices. silicon chip may hae 8 to 9 pn junctions today. How do they behae*? What happens to the electrons and holes? What is the electrical circuit model for such junctions? n and p regions are brought into contact : If we add an impurity with a deficit of electrons (e.g. boron) then bonding electrons are missing (holes), and the resulting holes can moe around again a pretty good conductor (ptype silicon) aluminum? n p aluminum wire Now what is really interesting is when we join ntype and ptype silicon, that is make a pn junction. It has interesting electrical properties. *Note that the textbook has a ery good explanation. Slide 343 Slide 344

87 Schematic diagram net acceptor concentration N ptype ntype Physical structure: (an example) For simplicity, assume that the doping profile changes abruptly at the junction. The pn Junction Diode net donor concentration N D crosssectional area D D I D SiO Circuit symbol I D D metal ptype Si ntype Si metal SiO Depletion egion When the junction is first formed, mobile carriers diffuse across the junction (due to the concentration gradients) Holes diffuse from the p side to the n side, leaing behind negatiely charged immobile acceptor ions Electrons diffuse from the n side to the p side, leaing behind positiely charged immobile donor ions acceptor ions donor ions p region depleted of mobile carriers is formed at the junction. The space charge due to immobile ions in the depletion region establishes an electric field that opposes carrier diffusion. n Slide 345 Slide 346 Depletion egion pproximation When the junction is first formed, mobile carriers diffuse across the junction (due to the concentration gradients) Holes diffuse from the p side to the n side, leaing behind negatiely charged immobile acceptor ions Electrons diffuse from the n side to the p side, leaing behind positiely charged immobile donor ions acceptor ions donor ions p region depleted of mobile carriers is formed at the junction. The space charge due to immobile ions in the depletion region establishes an electric field that opposes carrier diffusion. n Summary: pnjunction Diode I Under forward bias, the potential barrier is reduced, so that carriers flow (by diffusion) across the junction Current increases exponentially with increasing forward bias The carriers become minority carriers once they cross the junction; as they diffuse in the quasineutral regions, they recombine with majority carriers (supplied by the metal contacts) injection of minority carriers Under reerse bias, the potential barrier is increased, so that negligible carriers flow across the junction If a minority carrier enters the depletion region (by thermal generation or diffusion from the quasineutral regions), it will be swept across the junction by the builtin electric field collection of minority carriers reerse current I D () D () Slide 347 Slide 348

88 Charge Density Distribution Charge is stored in the depletion region. quasineutral p region acceptor ions p n depletion region donor ions charge density (C/cm 3 ) quasineutral n region distance Effect of pplied oltage D p The quasineutral p and n regions hae low resistiity, whereas the depletion region has high resistiity. Thus, when an external oltage D is applied across the diode, almost all of this oltage is dropped across the depletion region. (Think of a oltage diider circuit.) If D > (forward bias), the potential barrier to carrier diffusion is reduced by the applied oltage. If D < (reerse bias), the potential barrier to carrier diffusion is increased by the applied oltage. n Slide 349 Slide 35 Forward ias eerse ias s D increases, the potential barrier to carrier diffusion across the junction decreases*, and current increases exponentially. D > p n The carriers that diffuse across the junction become minority carriers in the quasineutral regions; they then recombine with majority carriers, dying out with distance. I D (mperes) s D increases, the potential barrier to carrier diffusion across the junction increases*; thus, no carriers diffuse across the junction. D < p n ery small amount of reerse current (I D < ) does flow, due to minority carriers diffusing from the quasineutral regions into the depletion region and drifting across the junction. I D (mperes) * Hence, the width of the depletion region decreases. D (olts) * Hence, the width of the depletion region increases. D (olts) Slide 35 Slide 35

89 Optoelectronic Diodes Light incident on a pn junction generates electronhole pairs Carriers are generated in the depletion region as well as n doped and pdoped quasineutral regions. The carriers that are generated in the quasineutral regions diffuse into the depletion region, together with the carriers generated in the depletion region, are swept across the junction by the electric field Example: Photodiode n intrinsic region is placed between the ptype and ntype regions W j W iregion, so that most of the electronhole pairs are generated in the depletion region faster response time (~ GHz operation) I D () This results in an additional component of current flowing in the diode: q kt I D D I ( e ) I S optical where I optical is proportional to the intensity of the light operating point in the dark with incident light D () Slide 353 Slide 354 Planck Constant Planck s constant h J s Ehνhc/λ C is speed of light and hν is photon energy The first type of quantum effect is the quantization of certain physical quantities. Quantization first arose in the mathematical formulae of Max Planck in 9. Max Planck was analyzing how the radiation emitted from a body was related to its temperature, in other words, he was analyzing the energy of a wae. The energy of a wae could not be infinite, so Planck used the property of the wae we designate as the frequency to define energy. Max Planck discoered a constant that when multiplied by the frequency of any wae gies the energy of the wae. This constant is referred to by the letter h in mathematical formulae. It is a cornerstone of physics. Si andgap ersus Lattice Constant Slide 355 Slide 356

90 Principle of Laser How to build up photon energy? Confine the light using mirrors Structure of Semiconductor Diode Laser PIN diode with DHS (Double Hetero Junction) configuration P I N Spontaneous Emission Laser Engineering Stimulated Emission dantages!! Confines both the carriers the photons efractie Index profile Suitable Gain Medium ight Choice of Mirrors Slide 357 Slide 358 What is a Laser? Laser is a deice that produces monochromatic, coherent radiation Could be ery Hazardous!! When does the laser action happen? ound trip gain in the caity should exceed the losses (absorption, leakage etc) The phase matching condition decides the possible caity modes 99.4% 5x 6nm QWs (3 nm) Hence, the laser has a threshold!! 99.75% Edge Emitting Diode Laser Slide 359 Surface Emitting Slide 36 PowerCurrent Characteristics

91 pplications of iolet LDs Higher density optical storage with shorter waelength High brightness applications like projection displays High efficiency solidstate lighting with isible phosphors Medical/nalytical applications Insulating sapphire substrate requires deep mesa etch and lateral ntype contact High electrical drie power requires a ery narrow ridge to reduce thermal resistance High current density requires thick metal electrodes to reduce sheet resistance Difficulty of cleaing GaN on sapphire makes etched facets attractie Laser Fabrication Slide 36 Slide 36 lue Diode Laser Looking through the transparent sapphire substrate Week MOSFET (Lec..4.) OUTLINE The MOSFET as a controlled resistor Pinchoff and current saturation MOSFET ID s. GS characteristic NMOS and PMOS I characteristics Loadline analysis; Q operating point; ias circuits Smallsignal equialent circuits Small signal model and Qpoint analysis Common source amplifier Source follower Common gate amplifier Commonsource amplifiers Source followers Commonsource amplifiers Input and output impedances Gain eading Supplementary Notes Chapter 4 Hambley: Chapter..5 Slide 363 Slide 364

92 MOSFET Terminals The oltage applied to the GTE terminal determines whether current can flow between the SOUCE & DIN terminals. For an nchannel MOSFET, the SOUCE is biased at a lower potential (often ) than the DIN (Electrons flow from SOUCE to DIN when G > T ) For a pchannel MOSFET, the SOUCE is biased at a higher potential (often the supply oltage DD ) than the DIN (Holes flow from SOUCE to DIN when G < T ) MOSFET Structure DEICE IN COSSSECTION Metal Semiconductor Oxide G Metal gate (l or Si) S n gate oxide insulator P n D The ODY terminal is usually connected to a fixed potential. For an nchannel MOSFET, the ODY is connected to For a pchannel MOSFET, the ODY is connected to DD In the absence of gate oltage, no current can flow between S and D. boe a certain gate to source oltage t (the threshold ), electrons are induced at the surface beneath the oxide. (Think of it as a capacitor.) These electrons can carry current between S and D if a oltage is applied. Slide 365 Slide 366 MOSFET Circuit Symbols The MOSFET as a Controlled esistor NMOS G G The MOSFET behaes as a resistor when DS is low: n polysi Drain current I D increases linearly with DS n n ptype Si S S esistance DS between SOUCE & DIN depends on GS DS is lowered as GS increases aboe T oxide thickness t ox NMOSFET Example: PMOS G G I D p polysi GS p p S S GS > T ntype Si I DS if GS < T DS Inersion charge density Q i (x) C ox [ GS T (x)] where C ox ε ox / t ox Slide 367 Slide 368

93 Sheet esistance eisited Consider a sample of ntype semiconductor: s I W t homogeneously doped sample L ρ t σt qµ nt µ Q where Q n is the charge per unit area n _ n n MOSFET as a Controlled esistor (cont d) I D DS DS DS ( L / W ) s L / W µ Q We can make DS low by n W L i µ C ( L / W applying a large gate drie ( GS T ) making W large and/or L small n ox GS DS I D ncox ( GS T ) µ T DS DS ) aerage alue of (x) Slide 369 Slide 37 GS < T : Charge in an NChannel MOSFET depletion region (no inersion layer at surface) GS > T : DS GS T What Happens at Larger DS? Inersionlayer is pinchedoff at the drain end GS > T : DS DS > (small) Slide 37 I D WQ WQ WQ erage electron elocity is proportional to lateral electric field E in in µ in n E µ n L DS DS > GS T s DS increases aboe GS T DST, the length of the pinchoff region L increases: extra oltage ( DS Dsat ) is dropped across the distance L the oltage dropped across the inersionlayer resistor remains Dsat the drain current I D saturates Note: Electrons are swept into the drain by the Efield when they enter the pinchoff region. Slide 37