MAX4617/MAX4618/ MAX4619 High-Speed, Low-Voltage, CMOS Analog Multiplexers/Switches

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1 // General Description The // are high-speed, lowvoltage, MOS analog Is configured as an 8-channel multiplexer (), two 4-channel multiplexers (), and three single-pole/double-throw (SPDT) switches (). These MOS devices can operate continuously with a +2V to +5.5V single supply. Each switch can handle Rail-to-Rail analog signals. The off-leakage current is only 1n at T = +25 and n at T = +85. ll digital inputs have.8v to 2.4V logic thresholds, euring TT/MOS-logic compatibility when using a single +5V supply. pplicatio attery-operated Equipment udio/video Signal Routing ow-voltage Data-cquisition Systems ommunicatio ircuits Features Fast Switching Times 15 t ON t OFF Pin ompatible with Industry-Standard 74451/74452/7445 and M4581/M4582/M458 Guaranteed On-Resistance Ω max (+5V Supply) 2Ω max (+V Supply) Guaranteed 1Ω On-Resistance Match etween hannels (single +5V supply) Guaranteed ow Off-eakage urrent: 1n at +25 Guaranteed ow On-eakage urrent: 1n at V to +5.5V Single-Supply Operation TT/MOS-ogic ompatible ow rosstalk: <-96d igh Off-Isolation: <-9d ow Distortion: <.17% (6Ω) Ordering Information PRT TEMP RNGE PIN-PKGE UE+T to TSSOP SE+T to Narrow SO PE+T to Plastic DIP +Denotes a lead(pb)-free/ros-compliant package. T = Tape and reel. Ordering Information continued at end of data sheet. Pin onfiguratio/functional Diagrams TOP VIEW Y Y Y Y 2 15 Y 14 1 Y 14 1 Z Y 4 1 Z Y Z N.. 7 OGI N.. 7 OGI N DIP/SO/TSSOP Rail-to-Rail is a registered trademark of Nippon Motorola, td. DIP/SO/TSSOP DIP/SO/TSSOP For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at ; Rev ; 12/12

2 // SOUTE MIMUM RTINGS Voltages Referenced to,,,, or Enable...-.V to +6V Voltage into ny nalog Terminal (Note 1)...-.V to ( +.V) ontinuous urrent into ny Terminal...±75m Peak urrent, _, Y_, Z_ (pulsed at 1ms, % duty cycle)...±2m ontinuous Power Dissipation (T = +7 ) TSSOP (derate 9.4mW/ above +7 )...755mW Narrow SO (derate 8.7mW/ above +7 )...696mW Plastic DIP (derate.5mw/ above +7 )...842mW Operating Temperature Ranges M to +7 M461_E...-4 to +85 Storage Temperature Range to +15 ead Temperature (soldering, sec)...+ Soldering Temperature (reflow) Note 1: Voltages exceeding or on any analog signal terminal are clamped by internal diodes. imit forward-diode current to maximum current rating. Stresses beyond those listed under bsolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of the specificatio is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. EETRI RTERISTISSingle +5V Supply ( = +4.5V to +5.5V, V _ = 2.4V, V _ =.8V, T = T MIN to T M, unless otherwise noted. Typical values are at T = +25.) (Note 2) PRMETER SYMO ONDITIONS MIN TYP M UNITS NOG SWIT nalog-signal Range V, V Y, V Z, E V Switch On-Resistance R ON = 4.5V; I, I Y, I Z = m; T = V, V Y, V Z = V, E 1 Ω Switch On-Resistance Match etween hannels (Note ) Switch On-Resistance Flatness (Note 4) ΔR ON R FT(ON) = 5V; I, I Y, I Z = m; V, V Y, V Z = V = 5V; I, I Y, I Z = m; V, V Y, V Z = 1V, 2V, V T = +25, E, E Ω Ω _, Y_, Z_ Off-eakage urrent (Note 5) I _(OFF), I Y_(OFF), I Z_(OFF) = 5.5V; V _, V Y_, V Z_ = 4.5V, 1V; V, V Y, V Z = 1V, 4.5V T = , E - n, Y, Z Off-eakage urrent (Note 5) I (OFF), I Y(OFF), I Z(OFF) = 5.5V; V EE = -5.5V; V _, V Y_, V Z_ = 4.5V, 1V; V, V Y, V Z = 1V, 4.5V T = , E - n, Y, Z On-eakage urrent (Note 5) I (ON), I Y(ON), I Z(ON) = 5.5V; V, V Y, V Z = 1V, 4.5V; V _, V Y_, V Z_ = 1V, 4.5V or unconnected T = , E - n DIGIT I/O V, V, Input Voltage igh V,, E 2.4 V V, V, Input Voltage ow V, V, E.8 V V 2 Maxim Integrated

3 // EETRI RTERISTISSingle +5V Supply (continued) ( = +4.5V to +5.5V, V _ = 2.4V, V _ =.8V, T = T MIN to T M, unless otherwise noted. Typical values are at T = +25.) (Note 2) PRMETER SYMO ONDITIONS MIN TYP M UNITS Input urrent igh µ I, I, I, V, V, V = V =, E I Input urrent ow µ I, I, I, V, V, V = V =, E I SWIT DYNMI RTERISTIS Enable Turn-On Time Enable Turn-Off Time ddress Traition Time reak-efore-make Time t ON t OFF t TRNS t M V _, V Y_, V Z_ = V; R = Ω; = 5pF; Figure V _, V Y_, V Z_ = V; R = Ω; = 5pF; Figure V _, V Y_, V Z_ = V; R = Ω; = 5pF; Figure 2 V _, V Y_, V Z_ = V; R = Ω; = 5pF; Figure 4 T = , E 18 T = , E 1 T = , E 18 T = harge Injection Q = 1nF, R S =, V S =, Figure 5 T = +25 p Input Off-apacitance Output Off-apacitance (OFF), 27 V Y(OFF), _, V Y_, V Z_ = ; f = 1Mz; T = Figure 7 Z(OFF) 8.5 Output On-apacitance (ON), 2 V Y(ON), _, V Y_, V Z_ = ; f = 1Mz; T = Figure 7 Z(ON) 15.5 Off-Isolation V ISO R = 5Ω, f = kz, Figure 6 T = hannel-to-hannel rosstalk Total armonic Distortion _(OFF), Y_(OFF), Z_(OFF) TD V _, V Y_, V Z_ = ; f = 1Mz; Figure 7 T = V T R = 5Ω, f = kz, Figure 6 T = R = 6Ω, 1Vp-p, f = 2z to 2kz T = POWER SUPPY Power-Supply Range, E V Power-Supply urrent I = 5.5V; V, V, V, V = or T = , E - µ pf pf pf d d % Maxim Integrated

4 // EETRI RTERISTISSingle +.V Supply ( = +V to +.6V, V _ = 2.V, V _ =.5V, T = T MIN to T M, unless otherwise noted. Typical values are at T = +25.) (Note 2) PRMETER NOG SWIT nalog-signal Range Switch On-Resistance SYMO V _, V Y_, V Z_, V, V Y, V Z R ON = V; I, I Y, I Z = m; V, V Y, V Z = 1.5V ONDITIONS MIN TYP M UNITS, E V T = , E 25 Ω _, Y_, Z_ Off-eakage urrent (Note 5) I _(OFF), I Y_(OFF), I Z_(OFF) =.6V; V _, V Y_, V Z_ = 1V, V; V, V Y, V Z = V, 1V T = , E - n, Y, Z Off-eakage urrent I (OFF), I Y(OFF), I Z(OFF) =.6V; V _, V Y_, V Z_ = 1V, V; V, V Y, V Z = V, 1V T = , E - n, Y, Z On-eakage urrent I (ON), I Y(ON), I Z(ON) =.6V; V, V Y, V Z = V, 1V; V _, V Y_, V Z_ = V, 1V, or unconnected T = , E - n DIGIT I/O Input Voltage igh V, V, V, V, E 2. V Input Voltage ow V, V, V, V, E.5 V Input urrent igh Input urrent ow I, I, I, I I, I, I, I V, V, V = V =, E µ V, V, V = V =, E µ SWIT DYNMI RTERISTIS Enable Turn-On Time t ON V _, V Y_, V Z_ = 1.5V; R = Ω; = 5pF; Figure T = +25, E Enable Turn-Off Time t OFF V _, V Y_, V Z_ = 1.5V; R = Ω; = 5pF; Figure T = +25, E ddress Traition Time t TRNS V _, V Y_, V Z_ = 1.5V/; R = Ω; = 5pF; Figure 2 T = +25, E reak-efore-make Time t M V _, V Y_, V Z_ = 1.5V; R = Ω; = 5pF T = harge Injection Q = 1nF, R S =, V S =, Figure 5 T = +25 p POWER SUPPY Power-Supply urrent I =.6V, V, V, V, V = or T = +25, E 1 µ 4 Maxim Integrated

5 // EETRI RTERISTISSingle +2.5V Supply ( = +2.5V, T = T MIN to T M, unless otherwise noted. Typical values are at T = +25.) (Note 2) PRMETER NOG SWIT SYMO ONDITIONS MIN TYP M UNITS Switch On-Resistance R ON = 2.5V; I, I Y, I Z = m; V, V Y, V Z = 1.2V T = +25 6, E Ω SWIT DYNMI RTERISTIS Enable Turn-On Time t ON V _, V Y_, V Z_ = 1V; R = Ω; = 5pF; Figure T = Enable Turn-Off Time t OFF V _, V Y_, V Z_ = 1V; R = Ω; = 5pF; Figure T = +25 ddress Traition Time t TRNS V _, V Y_, V Z_ = 1V; R = Ω; = 5pF; Figure T = Note 2: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column. Note : ΔR ON = R ON(M) - R ON(MIN). Note 4: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal ranges; i.e., V _, V Y_, V Z_ = V to and to -V. Note 5: eakage parameters are % tested at maximum-rated hot operating temperature, and guaranteed by correlation at T = +25. Note 6: Guaranteed by design, not production tested. Maxim Integrated 5

6 // ( = +5V, =, T = +25, unless otherwise noted.) Typical Operating haracteristics 25 2 ON-RESISTNE vs. V, V Y, V Z = +2V toc ON-RESISTNE vs. V, V Y, V Z ND TEMPERTURE toc2 OFF-EKGE vs. TEMPERTURE toc ON-RESISTNE (Ω) 15 = +2.5V = +V = +5V RON (Ω) T = +85 T = +7 T = +25 T = T = -4 OFF-EKGE (p) 1 I, I Y, I Z I _, I Y _, I Z _ V, V Y, V Z (V) V, V Y, V Z (V) TEMPERTURE ( ) ON-EKGE vs. TEMPERTURE RGE INJETION vs. V, V Y, V Z toc toc5 ON-EKGE (p) 1 RGE INJETION (p) TEMPERTURE ( ) V, V Y, V Z (V), SUPPY URRENT vs. TEMPERTURE V, V, V, V =, 5V toc SUPPY URRENT vs. OGI VOTGE = +5V toc7 I (p) I (m) = +V.5 = +2V TEMPERTURE ( ) V, V, V, V (V) 6 Maxim Integrated

7 // Typical Operating haracteristics (continued) ( = +5V, =, T = +25, unless otherwise noted.) V, V, V, V (V) INPUT IG OGI TRESOD vs. SUPPY VOTGE (V) toc8 GIN (d) FREQUENY RESPONSE toc9 IN = OUT = 5Ω ON-OSS ON-PSE OFF-ISOTION k k 1M M M 5M FREQUENY (z) PSE ( ).25.2 TOT RMONI DISTORTION vs. FREQUENY = 2.5V, 1Vp-p SIGN toc SWITING TIME vs. VOTGE toc11 TD (%).15. = +V, 1Vp-p SIGN IN = OUT = 6Ω = +.V, 1Vp-p SIGN = +5V, 1Vp-p SIGN SWITING TIMES () FREQUENY (kz) V+ (V) Maxim Integrated 7

8 // Pin Description PIN NME FUNTION 1, 14, 15, 12, 1, 5, 2, 4 7 nalog Switch Inputs 7 nalog Switch Output 12, 14, 15, 11, 1, 2, nalog Switch Inputs 1 14 nalog Switch Output 1 1 nalog Switch Normally Open Input 12 nalog Switch Normally losed Input 1 Y1 nalog Switch Y Normally Open Input 2 Y nalog Switch Y Normally losed Input Digital Enable Input. Normally connect to. an be driven to logic high to set all switches off N.. No onnection. Not Internally connected Ground Digital ddress Input 9 Digital ddress Input 9 9 Digital ddress Input 1, 5, 2, 4 Y, Y1, Y2, Y nalog Switch Y Inputs 15 Y nalog Switch Y Output 5 Z nalog Switch Z Normally losed Input Z1 nalog Switch Z Normally Open Input 4 Z nalog Switch Z Output Positive nalog and Digital Supply Voltage Input Note: Input and output pi are identical and interchangeable. ny may be coidered an input or output; signals pass equally well in both directio. pplicatio Information Power-Supply oideratio Overview The // cotruction is typical of most MOS analog switches. They have two supply pi: V and. V and are used to drive the internal MOS switches and set the limits of the analog voltage on any switch. Reverse ESD-protection diodes are internally connected between each analogsignal pin and both V and. If any analog signal exceeds V or, one of these diodes conducts. During normal operation, these and other reversebiased ESD diodes leak, forming the only current drawn from V or. Virtually all the analog leakage current comes from the ESD diodes. lthough the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either or and the analog signal. This mea their leakages will vary as the signal varies. The difference in the two diode leakages to the V and pi cotitutes the analog-signal-path leakage current. ll analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of either the same or opposite polarity. V and power the internal logic and set the input logic limits. ogic inputs have ESD-protection diodes to ground. 8 Maxim Integrated

9 // The logic-level thresholds are TT/MOS compatible when is +5V. s rises, the threshold increases; as falls, the threshold decreases. For example, when = +V the guaranteed minimum logic-high threshold decreases to 2.V Power Supply These devices operate from a single supply between +2.5V and +5.5V. ll of the bipolar precautio must be observed. t room temperature, they actually work with a single supply near or below +2V, although as supply voltage decreases, switch on-resistance becomes very high. Overvoltage Protection Proper power-supply sequencing is recommended for all MOS devices. Do not exceed the absolute maximum ratings because stresses beyond the listed ratings can cause permanent damage to the devices. lways sequence V on first, followed by the logic inputs and analog signals. If power-supply sequencing is not possible, add two small signal diodes (D1, D2) in series with the supply pi for overvoltage protection (Figure 1). dding diodes reduces the analog-signal range to one diode drop below and one diode drop above, but does not affect the devices low switch resistance and low leakage characteristics. Device operation is unchanged, and the difference between and should not exceed 6V. These protection diodes are not recommended if signal levels must extend to ground. igh-frequency Performance In 5Ω systems, signal respoe is reasonably flat up to 5Mz (see Typical Operating haracteristics). bove 2Mz, the on-respoe has several minor peaks that are highly layout dependent. The problem is not turning the switch on, but turning it off. The off-state switch acts like a capacitor and passes higher frequencies with less attenuation. t Mz, off-isolation is about -5d in 5Ω systems, becoming worse (approximately 2d per decade) as frequency increases. igher circuit impedances also degrade off-isolation. djacent channel attenuation is about d above that of a bare I socket and is entirely due to capacitive coupling. Pin Nomenclature The // are pin compatible with the industry-standard 74451/74452/ 7445 and the M4581/M4582/M458. In single-supply applicatio, they function identically and have identical logic diagrams, although these parts differ electrically. The pin designatio and logic diagrams in this data sheet conform to the original 1972 specificatio published by R for the D451/D452/D45. These designatio differ from the standard Maxim switch and mux designatio found on other Maxim data sheets (including the M451/M452/M45) and may cause confusion. Designers who feel more comfortable with Maxim s standard designatio are advised that the pin designatio and logic diagrams on the M451/M452/M45 data sheet may be freely applied to the //. *, Y, Z _, Y_, Z_ * V EE D1 ETERN OKING DIODE * * D2 ETERN OKING DIODE *INTERN PROTETION DIODES Figure 1. Overvoltage Protection Using External locking Diodes Maxim Integrated 9

10 // Table 1. Truth Table/Switch Programming SEET INPUTS ON SWITES INPUT * ll switches open ll switches open, Y Y ll switches open, Y Y, Z Z 1 1, Y Y1 1, Y Y, Z Z 2 2, Y Y2, Y Y1, Z Z, Y Y 1, Y Y1, Z Z 4, Y Y, Y Y, Z Z1 5 1, Y Y1 1, Y Y, Z Z1 6 2, Y Y2, Y Y1, Z Z1 7, Y Y 1, Y Y1, Z Z1 = Don t care * not present on. Note: Input and output pi are identical and interchangeable. Either may be coidered an input or output; signals pass equally well in either direction. Maxim Integrated

11 // Test ircuits/timing Diagrams V, V, V 5Ω 1 7 V, V, V V 5% 9% Ω 5pF V 7 9% t TRNS t TRNS V, V 5Ω, Y 1, 2, Y1, Y2., Y V, V V, V Y 5% 9%, Y Ω 5pF V, 9% V Y t TRNS t TRNS V, V, V,, 1, Y1, Z1 V, V, V 5% 5Ω 2, Y2, Z2 V, V Y, V Z 9%, Y, Z Ω 5pF V 1, V Y1, V Z1 9% t TRNS t TRNS TEST E SETION INDIVIDUY. Figure 2. ddress Traition Times Maxim Integrated 11

12 // Test ircuits/timing Diagrams (continued) 1 7 V V 5% 9% V 5Ω Ω 5pF 9% t ON t OFF, Y 1, Y1 Y V V, V Y 5% 9% V 5Ω, Y Ω 5pF 9% t ON t OFF V 5Ω 1, Y1, Z1, Y, Z, Y, Z Ω 5pF V V, V Y, V Z V 1, V Y1, V Z1 t ON 5% 9% 9% t OFF TEST E SETION INDIVIDUY. Figure. Enable Switching Times 12 Maxim Integrated

13 // Test ircuits/timing Diagrams (continued) V, V, V 5Ω 7 V, V 5Ω, Y Y Ω 5pF, Y Ω 5pF V, V, V 5Ω,,, 1, Y, Y1, Z, Z1, Y, Z Ω 5pF V+ V, V, V V, V Y, V Z 5% 8% t R < 2 t F < 2 TEST E SETION INDIVIDUY. t M Figure 4. reak-efore-make Interval NNE SEET V 5Ω _, Y_, Z_, Y, Z pf V Δ Δ VOUT IS TE MESURED VOTGE DUE TO RGE- TRNSFER ERROR Q WEN TE NNE TURNS OFF. TEST E SETION INDIVIDUY. Q = Δ Figure 5. harge Injection Maxim Integrated 1

14 // Test ircuits/timing Diagrams (continued) nf NNE SEET _, Y_, Z_, Y, Z V IN NETWORK NYZER 5Ω 5Ω MES. REF. 5Ω 5Ω OFF-ISOTION = 2log ON-OSS = 2log ROSSTK = 2log V IN V IN V IN NOTES: MESUREMENTS RE STNDRDIZED GINST SORT T SOKET TERMINS. OFF ISOTION IS MESURED ETWEEN OM ND "OFF" NO TERMIN ON E SWIT. ON OSS IS MESURED ETWEEN OM ND "ON" NO TERMIN ON E SWIT. ROSSTK (/) IS MESURED FROM ONE NNE (,, ) TO OTER NNES. SIGN DIRETION TROUG SWIT IS REVERSED; WORST VUES RE REORDED. Figure 6. Off-Isolation, On-oss, and rosstalk NNE SEET _, Y_, Z_, Y, Z 1Mz PITNE NYZER Figure 7. apacitance 14 Maxim Integrated

15 // Ordering Information (continued) PRT TEMP RNGE PIN-PKGE EUE+T -4 to TSSOP ESE+T -4 to Narrow SO EPE+T -4 to Plastic DIP UE+T to TSSOP SE+T to Narrow SO PE+T to Plastic DIP EUE+T -4 to TSSOP ESE+T -4 to Narrow SO EPE+T -4 to Plastic DIP UE+T to TSSOP SE+T to Narrow SO PE+T to Plastic DIP EUE+T -4 to TSSOP ESE+T -4 to Narrow SO EPE+T -4 to Plastic DIP +Denotes a lead(pb)-free/ros-compliant package. T = Tape and reel. hip Information PROESS: imos Package Information For the latest package outline information and land patter (footprints), go to Note that a +, #, or - in the package code indicates RoS status only. Package drawings may show a different suffix character, but the drawing pertai to the package regardless of RoS status. PKGE TYPE PKGE ODE OUTINE NO. ND PTTERN NO. 16 TSSOP U Narrow SO S PDIP P Maxim Integrated 15

16 // REVISION NUMER REVISION DTE DESRIPTION Revision istory PGES NGED 7/99 Initial release 1 8/1 hange specificatio 2, 7 2 4/2 dded QFN package 1, 2, 5, 15 12/12 dded lead-free information to data sheet, removed QFN package 1, 2, 5, 15 Maxim Integrated cannot assume respoibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licees are implied. Maxim Integrated reserves the right to change the circuitry and specificatio without notice at any time. The parametric values (min and max limits) shown in the Electrical haracteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. 16 Maxim Integrated 16 Rio Robles, San Jose, 9514 US Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.