RS-232 Tra ns ce ive r. COM1 RS-485 Drive r. 2.9V < -- 5V Le ve l s hifter. Re v.a to Re v.b Cha nge s. Te chnologic Sys tems
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1 R- Tra ns ce ive r C V. uf.v < -- V Le ve l s hifter C. uf R.K U E_BAT-CC_OT IR 0.V OE CPU_.V COM_RX_V EBU_TX UART_TX MUX U AN_0 AN_ COM EL NCBP_C0 CPU_.V C. uf C. uf COM_RT_V COM_TX_V COM_TX_V 0 U Vcc C+ V+ C- V- C+ C- T T T T R C. uf C. uf COM_TX COM_RT COM_TX COM_TX COM_RX COM_RX_V COM_CT_V COM_RX_V LC_BIA RX0_ IRQ IRQ IRQ A B A B A B A B A B A B A B A B 0 LVC_TOP LC_BIA_PWM RX0 V IA_IRQ IA_IRQ IA_IRQ MUX COM_RX_V R.K OFF_B_REET# R R R R EN_RX # 0 P_OP COM_CT COM_RX COM_RX V U EBU_RX AN_0 CPU_.V UART_RX AN_ COM COM_RX_V EL NCBP_C0 Force Cons ole CPU_.V R.K CPU_.V TX0_ COM R- rive r R0.K TX U V R.K C. uf Re v.a to Re v.b Cha nge s a dde d C (0 uf 0V) for EMI RX0 V TXEN_0 RX TXEN X+ X- COM_+ COM_- R0.K RXEN# PEEN_OIC R.K April, 0 Re v: T-0 R-, R- B e s igne r he e t of
2 COM Conne ctors a nd He a de rs COM J COM_TX COM_RT COM_RX COM_CT B-M TX+ _(C) TX-_(R) RX+ _(TR) RX-_(RI) TX RT RX FRAME CT FRAME CON-B 0 BM COM_TX COM_TX COM He a de r TX TR RT H 0 COM_+ COM_- TX TR RT RX R CT C RI H 0 COM He a de r COM_RX RX R COM_RX CT C RI H_X_COM_PORT Be wa re Non-s tanrd pin-out H_X_COM_PORT April, 0 T-0 B, COM He a de rs Re v: B e s igne r he e t of
3 Ethe rne t Ports Port # ig Ma gja ck Port # 0/00 Ma gja ck T ETH_ACT_LE R 0 Left LE T re e n Alignme nt Pe gs ETH_RX_P ETH_RX_M ETH_CT C RX+ RX- RX_CT ALIN ALIN MI0_P + TX+. uf ETH_CT C. uf C. nf MI0_M MI_P MI_M MI_P MI_M MI_P MI_M Right LE Ye llow ohm Re s. a nd 000 pf KV hie ld TX_CT POE_RX POE_TX TX+ TX- POE_ POE_ LLE+ re e n LLE- H H RLE+ Ye llow RLE- TX- RX+ RX- ETH_TX_P ETH_TX_M ETH_ACT_LE ETH_RIHT_LE# R 0 CPU_.V R 0 MAJACK_POE_0_00 0 MAJACK_I ETH_PEE_LE R 0 Note: Pin not conne cted for this T-0 la yout only be ca us e both Ma gja cks s ha re a hole ETH_CT C C C C C C. nf. nf. nf. nf. nf. nf The s e ca ps tie ETH_CT pla ne to pla ne T-0 Ethe rne t Ports April, 0 Re v: B e s igne r he e t of
4 UB Ports Externa l ua l UB Externa l PF PTC_00MA_ FB EN_UB_V UB Powe r witch V R.K R.K Q-A C0. nf R 0 Q UB_V UB_OT_V UB_OT_M UB_OT_P UB_V C. uf TV BX0A_OT UB_V UB_HOTA_M UB_HOTA_P UB_V C0. uf Bottom Port TV Top Port BX0A_OT 0 ohm FB 0 ohm J ua l UB FRAME 0 FRAME FRAME FRAME CONN_UB_UAL_RA Q-B April, 0 T-0 UB Port s Re v: B e s igne r he e t of
5 a nd LC Jumpe rs la be le d "IC" on PCB a nd "" CPU_.V R.K R0.K Port CN0 CPU_.V PI_CLK PI_MOI _PIN_[0:] _PIN PIN PIN_ LC_ LC_ LC_ LC_ LC_ LC_ LC_ LC_0 PI_MIO_V 0 BE# A0 A A A A A A A A A U0 NC B0 B B B B B B B B B 0.V PI_MIO LC Port CN PI_MIO_V 0 _PIN_0 0 _PIN IC_AT PI_C# _PIN_0 _PIN_0 _PIN_0 _PIN_0 Q_QOP Provide s V tole ra nce LC_BIA R 0 R 0 LC_WR# C WR# R LC_R V R LC_EN H_X_.MM. uf H_X_.MM IC_CLK 0V Wa rning: All LC pins a re EN_FET Q-A LC_0 thru LC_ a re V tole ra nt bi-dire ctiona l R.K LC_WR#, LC_R, a nd LC_EN a re not! 0V EN_FET Q-B R0.K CPU_.V R.K R.K _PIN PIN_ Wa rning: a re not V tole ra nt!.v upply R _PIN_ Only PI_MIO is V tole ra nt.k V R0 _PIN_0 Q.K.V R _PIN_0.K C. uf R.K R _PIN_0.K R _PIN_0.K R _PIN_0.K April, 0 Re v: T-0, LC B e s igne r he e t of
6 V Powe r upply (.0 Amps ) Input Powe r.0v to 0V VIN C mus t be ve ry ne a r U Powe r VIN C0 Conn. CN + - CONN_PWR_PO_MM C 0 uf 0V FB 0 ohm C0. uf PF PTC_.A_V FB 0 ohm C 0 uf 0V C. uf R 00K U VIN.V-V AJ RT FET_ATE. uf V C. nf R0.K Q C. uf C mus t be ve ry ne a r Q V TV_V_UNI_MB FB 0 ohm PA CUR_ENE.V FB RE_LM0MY_OIC R.K C L uh C. nf R.K. 0V nomina l C 0 uf.v V. uf R0.K CPU_. V CPU_.V C. uf C. uf C. uf C0. uf C. uf C. uf C. uf C. uf C. uf C. uf C. uf C. uf C. uf C. uf April, 0 Re v: T-0 V Powe r B e s igne r he e t of
7 Boa rd I = U.V R.K R.K Y0 Y Y Y Y Y Y Y OUT.V B_I_ATA JP JP R0.K JP# CPU_.V RE_LE# 0 OUT# REEN_LE# 0 BU_IR EN# HC_OIC AC, AC, HC a re nd s ource s in OIC Force Boot to ca rd BU_IR R 0 OFF_B_REET#.K s hould be ne a r CN LEs CPU_.V LE re e n LE RE R0 0 RE_LE# RTC Ba ttery R 0 REEN_LE# Pus h witch R0.K CPU_.V V_BAT W PUH_W# K E_BAT-CC_OT PUHW_RT_TH R 0 R 0 MT MT MT MT April, 0 T-0 Ba ttery, Boa rd I, LEs Re v: B e s igne r RLM he e t of
8 Inputs on Le ft PL Outputs on Right PC/0 MUXe d Addre s s a nd a ta Bus IA Addre s s (Outputs) A_[00:] A_ A_ A_ A_ A_ A_0 A_0 A_0 A_0 A_0 A_0 A_0 A_0 A_0 A_0 A_00 A A PL_JTA_TCK PL_JTA_TI PL_JTA_TO PL_JTA_TM _B _A _A _A _A _A OFF_B_REET# IA_WAIT# BU_ALE# BU_C# BU_IR PL_.MHZ TCK TI TO TM CLK CLK U 0 INT INT INT/ INT/ CLK CLK / / 0 0 CPU_.V LC_[0:] LC_ LC_ LC_ LC_ LC_ LC_ LC_ LC_0 LC_WR# LC_R LC_EN LC_BIA_PWM IA_REET _A _A _A _A _A0 _A _B _B IA_R# IA_W# IA_C# BU_WAIT# A A0 IA_A_[0:] IA_A_ IA_A_ IA_A_ IA_A_ IA_A_ IA_A_ IA_A_ IA_A_ IA_A_ IA_A_0 U CPU_.V 0 IR OE A_0 B A A_0 B A A_0 B A A_0 B A A_0 B A A_0 B A A_0 B A A_00 B A 0 A_[00:] LVC_TOP Provide s V tole ra nce BU_IR IA_C# -pin Conne ctor CN BU_BHE# A B CHK# REET B A + V A IRQ B B A B -V A B RQ A B -V A B ENX# A A B + V 0 (KEY) B0 IA_WAIT# A0 RY B A MEMW# R AEN B CPU_.V MEMR# 0 _A _A _A _A _A _A _A _A _A _A0 _A IA_A_ IA_A_ IA_A_ IA_A_ IA_A_ IA_A_ IA_A_ IA_A_ IA_A_ IA_A_0 IA_A_[0:] W# A A R# A A A A ACK# A A RQ A A ACK# A A RQ A A RFRH# A A A0 A BCLK A A0 IRQ IRQ IRQ IRQ A A IRQ A A A A ACK# A A TC A A A A BALE A A + V A A A0 A OC A A0 A B B B B B B B B0 B B B B B B B B B B0 B B IA_REET V A_0 CPU_.V VIN _B _B IA_W# IA_R# A_0 A_0 _B A_ A_ A_ A_ A_ V IA_.MHZ R.K R.K R.K IA_IRQ IA_IRQ IA_IRQ -bit a nd -bit I/O Re a d a nd Writes s upported ove r a ddre s s ra nge 000-FF Addre s s ra nge 00-FF drive s PC/0 bus 0 0 MAX_0_.V_TQFP00 MAX0 Outputs _A thru _A a nd LC_EN s hould de fa ult to logic ze ro Inputs LC_WR#, LC_R a nd LC_0 thru LC_ s hould de fa ult a s Inputs PC0_-PIN_HORT Addre s s ra nge 000-0FF Wa rning: _B a nd _B s hould de fa ult to logic "" is interna l PL re gis ters Ma ke s ure PL pins a nd a re Inputs April, 0 T-0 PL, PC/ 0 bus Re v: B e s igne r he e t of
9 Two 00-pin Module Conne ctors Le ft Right OFF_B_REET# is a n Out put from CN CN the BC us e d to re s e t a ll pe riphe ra ls OFF_B_REET# POWER FB V 0 ohm C. uf _PIN_0 _PIN_0 TXEN_0 _PIN_0 _PIN_0 PUH_W# _PIN_0 _PIN_ R _PIN_ IA_.MHZ B_I_ATA _PIN_ IRQ R IRQ PL_.MHZ IRQ BU_WAIT# BU_BHE# NC NC NC EN_UB_V POWER V_BAT BU_ALE# BU_IR BU_C# A_ A_ A_ A_ A_ A_0 A_0 A_0 A_0 A_0 A_0 A_0 A_0 A_0 A_0 A_00 A_[00:] CPU_.V FB 0 ohm UB Ports Ethe rne t Port ETH_CT MI_P MI_M C. uf MI_P MI_M UB_HOTA_M UB_HOTA_P UB_OT_M UB_OT_P PI_C# PI_MOI PI_MIO PI_CLK Cons ole ETH_RIHT_LE# MI0_P MI0_M ETH_CT MI_P MI_M EBU_TX EBU_RX ETH_ACT_LE ETH_PEE_LE RE_LE# REEN_LE# ETH_ACT_LE ETH_RX_P ETH_RX_M ETH_CT ETH_TX_P ETH_TX_M JP# IC_CLK IC_AT PL_JTA_TM PL_JTA_TCK PL_JTA_TO PL_JTA_TI UB_OT_V COM_TX_V COM_RX_V EN_FET EN_FET COM_TX_V COM_RX_V TX0_ Ethe rne t Port IC RX0_ UART_TX UART_RX COM_RT_V COM_CT_V CN- = Hos t Mode B TYCO_00PIN_BAEBOAR TYCO_00PIN_BAEBOAR Boot tra p BC BU_IR Boot s from NAN Fla s h _PIN R0.K CPU_.V 0 Ca rd E_BAT-CC_OT BU_IR s tate is la tche d prior to OFF_B_REET# de a s s e rted BU_IR ha s a K pull-up re s is tor on the BC module Us e.k ohm re s is tor to OFF_B_REET# to s tra p logic low April, 0 T-0 T-ocke t Conne ct ors Re v: B e s igne r he e t of
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