A Unified Compact Model for Depletion MOSFETs in Smart Power Applications

Transcription

1 A Uifie Compact Moel for Depletio MOSFE i Smart Power Applicatio Lutz Göhler Uiverität er Buewehr Müche Werer-Heieberg-Weg 39 D Neubiberg, Germay el.: Fax: Lutz.Goehler@UiBw-Mueche.De Klau Keltig Sieme AG, HL PSE CAD P.O. Box Balatraße 73 D Muich, Germay el.: Fax: Klau.Keltig@Hl.Sieme.De Keywor Deig, Device moellig, Device, MOS evice, Semicouctor evice, Simulatio, Smart Power Abtract hi paper preet a compact epletio MOSFE (DMOSFE) moel primary applicable i mart power circuit imulatio. For the firt time, a complete ecriptio of all iteral tate a the tore charge i both o - tate a ubthrehol operatio of a DMOSFE i give. Depite thee avatage the equatio et require 25 parameter oly. trouctio the begiig of circuit itegratio epletio MOSFE were ofte ue a loa elemet i iverter. Although CMOS techology replace NMOS procee i may applicatio there i till a wie fiel of ue for thee traitioal olutio. Obviouly thi evelopmet reult from a high cot preure o prouct the power coumptio of which i a rather o - critical value. Eve i mart power techology thee coitio are give, becaue the logic part caue a mall fractio of the total power loe oly. A few moel of DMOSFE are to be fou i literature, but ufortuately the they o ot cover all operatio moe. Furthermore, ome of them ugget implicit equatio ytem, which ormally lea to umerical problem urig imulatio. [1] for example, the ubthrehol moe i ot coiere a the yamic moel rely o a capacitace etwork, wherea [5] preet a implicit ytem with a icomplete yamic ecriptio the followig, a moel proviig iformatio o all moe i preete. Charge aige to each evice termial allow the calculatio of iplacemet curret for yamic imulatio. Depletio MOSFE A - type epletio MOSFE coit of a - type ehacemet MOSFE with a aitioal - implatatio (burie chael). Fig. 1 how the typical tructure of a logic voltage level (e.g. 5V) elemet. he opig profile i the chael () a the bulk (p) i aume to be homogeeou, thu formig a abrupt p - juctio. Sice the implatatio etablih a couctig layer alreay at V GS = 0V the evice i ormally o.

2 Figure 1. Structure of a - type epletio MOSFE. he three poible moe at the oxie uerie (accumulatio, epletio, iverio) combie to ix ifferet iteral tate a how i the followig figure (Fig. 2-8). Figure 2. Accumulatio at the emicouctor urface. Figure 3. Accumulatio a epletio at the emicouctor urface.

3 Figure 4. Accumulatio at the emicouctor urface a puch - through of bulk pace - charge regio. Figure 5. Depletio at the emicouctor urface. Figure 6. Depletio a iverio at the emicouctor urface. Figure 7. verio at the emicouctor urface.

4 With exceptio of the firt cae aturatio may occur at the rai e of the chael. Fig. 8 illutrate thi behaviour aumig a combiatio of accumulatio a epletio (ee alo Fig. 3). t ca be ee, that the pace charge regio from the bulk a gate cut off the chael by touchig each other. Figure 8. Saturatio for accumulatio a epletio at the emicouctor urface. he everal combiatio of local moe are the mai ifferece to ehacemet MOSFE, where there i oly iverio i the o - tate poibly turig ito aturatio. With eglectio of Fig. 4 all moe combiatio occur i the metioe equece, whe the gate ource voltage V GS chage from poitive to egative value for fixe V a V SB. ubthrehol operatio the chael i cut off over it whole legth. Hece, the very few remaiig electro ca couct the curret by iffuio oly. he oet of iverio at certai termial coitio lea to a lower limitatio of the rai - ource curret. Each of the four termial ca get a charge aige (Fig. 9), o that iplacemet curret flow urig traiet imulatio. he gate charge i imply the um over all charge particle o the gate metallizatio, wherea opig io i the p - regio form the bulk charge. Source a rai charge i total equal the chael charge icluig accumulate electro. Figure 9. Charge i a epletio MOSFE. Bae o thee coieratio a et of moel equatio will be erive i the ext ectio. Moel Decriptio he key to a imple moel formulatio i the efiitio of a electrotatic potetial Φ i the chael a alreay raw above (Fig. 2-8). o - tate curret flow ue to carrier rift, a the eparatio ito four poible ectio (accumulatio ( a ), accumulatio puch - through ( ap ), epletio ( ), iverio ( i)) with charge per area aige accorigly yiel w µ = L acc. a + acc. pt. ap wµ + L ep. + iv. i, (1)

5 where w a L i the with a legth of the chael, repectively. he variable µ a µ eote the electro mobility at the urface a i the chael. Both borer of each ectio, i.e. both limit of each itegral, ca be calculate i relatio to Φ. A et of witchig coitio aig the proper value. he itetio i, that oly the itegral applicable to a particular termial voltage coitio have to be olve. A a reult, all other term of (1) vaih. A approach like thi ratically reuce the umber of equatio, becaue oly four itegral have to be olve for ix ifferet tate. hi alo affect the charge moel, the equatio of which are otherwie very log. All charge calculatio require iformatio o the patial exteio of the particular local moe. Uig the kow curret the legth epeece ca be traforme ito a potetial epeece i term of Φ. Chael ( ) a bulk charge ( B ) for rift reult i: 2 w µ V 0, (2) B 2 w µ V 0 B. (3) Note that * wa writte itea to itiguih betwee the two mobilitie. Agai, itegratio ha to be performe over all four ectio. he ource charge erive from a moifie approach of [4] a require more calculatio effort: S 3 w 2 2 µ L V 0 Φ 0. (4) total, all charge um up to zero 0 = + +, (5) G B i with qww LN. (6) i i N ame the chael opig with a epth of w i.(ee Fig. 1) he cotat q repreet the elemetary charge. verio excepte (6) provie the gate charge. Coequetly, a term coierig the hole cotributio ha to be ae i the moel. ubthrehol moe the curret aume a expoetial form: = w L V exp 1 exp. (7) V V i a curret parameter, V the thermal voltage a Φ the Potetial Φ i the chael uer ubthrehol coitio. t lower limit i give by the oet of iverio. Equatio (7) ee 2 parameter le tha the olutio i [3]. he expoetial form follow from Boltzma tatitic with the aumptio of a cotat electrotatical but a varyig electrochemical potetial betwee ource a rai. Sice iffuio preomiate gra() oe ot chage. hi kowlege implifie charge calculatio igificatly. For, B a S oe get:

6 1 wl 2 µ V exp V + V 1 exp V, (8) 2q Si N a N B wl ε 0ε V D + V N a + N ( + ) SB (9) a S 1 wl 6 µ V exp V V 2 + exp V. (10) N a eote the bulk opig a V D i calle iffuio voltage (of the chael - bulk juctio). aitio to thi tatic a yamic ecriptio our moel iclue: chael legth moulatio breakow paraitic ioe forme by the ource/rai - bulk juctio ( + - p) temperature epeece of all curret a charge (e.g. = f(), µ, µ = f()). he parameter et coit of 25 value, the etermiatio of which will be explaie i [2]. Not all of them ee to be kow for each evice. A a example, the paraitic ioe are egligible i a log chael DMOSFE. Reult We tete the moel for a log chael elemet with w/l = 1. Fig. 10 how the output characteritic. Goo agreemet betwee meaure a imulate behaviour coul be achieve. hi i alo prove by the trafer characteritic (Fig. 11) plotte i a emilogarithmic cale. Deviatio are maily ue to the aumptio of a homogeeou opig profile, which ifluece the reprouctio of the boy effect (i.e. = f(v SB )). Figure 10. Output characteritic ( - - meaure, imulate; V GS = (-3...3)V, V SB = 0V).

7 Figure 11. rafer characteritic ( - - meaure, imulate; V = 5.1V, V SB = (0...5)V). Capacitace compario provie a tet for the charge moel. We etermie the gate - gate capacitace G C GG = (11) V GS V, V = cot. SB DB by imulatio a experimet for V SB = V DB = 0V (Fig. 12). he ifferece betwee both curve are caue o oe ha by the alreay metioe opig profile approximatio a o the other ha by a harp traitio betwee the emicouctor urface tate. hi lat implificatio i abolutely eceary to obtai itegrable expreio for the iiviual charge i (1) a hece a explicit equatio ytem. Fially, Fig. 13 iplay the ormalize ource charge for a igle output curve ( S / 100% = f(v ) at cotat V GS ). he correpoig output curve i alo to be ee. For V = 0 ource a rai charge are equal, ice there i o chage of the bulk pace charge regio with a the emicouctor urface tate alog the chael. With icreaig rai - ource voltage the rai e of the chael get ito epletio a fially i aturatio. herefore there are fewer electro ear the rai tha at the ource. hi reult i a icreae of the ource a rai charge ratio. aturatio thi value reache approximately S / D 1.5. Figure 12. Gate - gate capacitace ( - - meaure, imulate; V = V SB = 0V).

8 Cocluio Figure 13. Drai curret ( - - ) a ource charge i per cet of chael charge ( ) (V SB = 0V, V GS = 3V). thi paper a epletio MOSFE moel for mart power circuit imulatio wa preete. he moel excel by a complete ecriptio of all iteral tate icluig ubthrehol operatio a a charge moel for traiet imulatio. Meauremet prove the valiity of the moel. All 25 parameter ca be etermie automatically, o that practical uefule i guaratee. Referece 1. Youef A. El-May. Aalyi a Characterizatio of the Depletio-Moe GFE, EEE raactio o Electro Device, pp , Lutz Göhler, Klau Keltig. A Scalable Depletio MOSFE Moel Allowig Efficiet Parameter Determiatio, to be publihe at ESSDERC homa E. Hericko. A Simplifie Moel for Subpichoff Couctio i Depletio-Moe GFE, EEE raactio o Electro Device, pp , Soo-Youg Oh, Doal E. War, Robert W. Dutto. raiet Aalyi of MOS raitor, EEE raactio o Electro Device, pp , Clauio urchetti, Guio Maetti. Aalyi of the Depletio-Moe MOSFE cluig Diffuio a Drift Curret, EEE raactio o Electro Device, pp , 1985.