BENGALI, SAURABH SUNIL. Vedic Mathematics and Its Applications in Computer Arithmetic. (Under the direction of Dr. Paul Franzon).

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1 ABSTRACT BENGALI, SAURABH SUNIL. Vedic Mathematics and Its Applications in Computer Arithmetic. (Under the direction of Dr. Paul Franzon). Multiplication and Division are most basic and frequently used operations in a CPU. These operations also form the basis for other complex operations. With ever increasing need for faster clock frequency it becomes imperative to have faster arithmetic unit. In this work a new system of Mathematics Vedic Mathematics is used to implement operations. Vedic Mathematics is based on 16 formulas with the purpose of simplification of lengthy and cumbersome mathematics. Vedic mathematics contains multiple algorithms for one operation. In the current work these algorithms are evaluated for their suitability in binary arithmetic. Suitable algorithms are implemented for Multiplication, Squaring and Division in Verilog. Multiplication and Squaring are further used in design of Sine and Cosine function implementations..

2 Vedic Mathematics and Its Applications in Computer Arithmetic by Saurabh Sunil Bengali A thesis submitted to the Graduate Faculty of North Carolina State University in partial fulfillment of the requirements for the degree of Master of Science Computer Engineering Raleigh, North Carolina 2011 APPROVED BY: Dr. Alexander Dean Dr. Eric Rotenberg Dr. Paul Franzon Committee Chair

3 DEDICATION This thesis is dedicated to my parents. ii

4 BIOGRAPHY Saurabh Sunil Bengali was born on 18 th December 1985, in Nashik, India. He received his Bachelor of Engineering degree from Pune University in After working in IIT, Mumbai as Research Assistant, he joined North Carolina State University for Graduate Studies. He is pursuing his research under Dr. Paul Franzon. iii

5 ACKNOWLEDGMENTS First and foremost, I would like to thank my parents, sister and brother-in-law for their constant encouragement. I would also like to thank Prachiti Sakhalkar, without her support it would have been impossible to reach where I stand today. It was great experience to work with Dr. Paul Franzon. I would like to thank him for the faith he showed in my work. I would also like to thank Dr. Eric Rotenberg and Dr. Alexander Dean for their support not only as committee member but also as great instructors. I would also like to thank Sagar Chinchani, Nidhi Pathak and Swanand Patil for their support and encouragement. iv

6 TABLE OF CONTENTS LIST OF TABLES. viii LIST OF FIGURES... ix Chapter 1 1 Introduction Motivation Goal of this Work Related Work Organization 3 Chapter 2 4 Vedic Mathematics Revival Sutras and Up-sutras Decimal Multiplication Nikhilam Sutra Anurupyena Urdhva-tiryagbhyam Decimal Squaring Decimal Division Nikhilam Dhwajanka 26 Chapter 3 30 Multiplication and Squaring Binary Multiplication - Urdhva-tiryagbhyam Algorithm Comparison of Vedic and Conventional Multiplier Combining Partial Products Wallace Tree Vedic Wallace Vedic Vedic Comparison with DesignWare DesignWare Implementation Timing Area Comparison Power Comparison Analysis Critical Path Analysis for 4 bit Multiplier Binary Squaring Dwandwayoga Algorithm Example of Squaring Comparison with DesignWare Multiplier v

7 3.6.1 Timing Area Comparison Power Comparison.. 53 Chapter 4 42 Division Binary Nikhilam Binary Dhwajanka Algorithm Limitations and Solutions Negative Subtraction Correct Remainder Partial remainder overflow Comparison with DesignWare Timing Area Power.. 65 Chapter 5 51 Trigonometric Functions Taylor Series CORDIC Algorithm Polynomial Approximation and Interpolation. 70 Chapter 6 56 Polynomial Approximation and Interpolation Newton Interpolation First-order Newton Polynomials Second-order Newton Polynomials Lagrange Interpolating Polynomials Lagrange First order Lagrange Second order Approximation Legre Chebyshev Polynomials Minimax Polynomial Polyfit function Comparison of methods for Sine Comparison of methods for Cosine Comparison with DesignWare Timing Area Comparison Power Comparison.. 82 Chapter 7 85 Summary and Future Work vi

8 7.1 Summary Future Work 85 REFERENCES. APPENDIX APPENDIX A Verilog Code for Multiplication APPENDIX B Verilog Code for Squaring 126 APPENDIX C Verilog Code for Sine and Cosine 164 APPENDIX D Verilog Code for Division 237 APPENDIX E MATLAB codes for coefficient comparison vii

9 LIST OF TABLES Table 2.1 Duplexes of Numbers 19 viii

10 LIST OF FIGURES Figure 2.1 Example of Nikhilam Figure 2.2 Example of Nikhilam 8 Figure 2.3 Example of Nikhilam 9 Figure 2.4 Example of Nikhilam... 9 Figure 2.5 Example of Nikhilam 9 Figure 2.6 Example of Nikhilam 10 Figure 2.7 Example of Nikhilam 10 Figure 2.8 Normal Example of Nikhilam Figure 2.9 Sub-Normal Example of Nikhilam Figure 2.10 Super-Normal Example of Nikhilam.. 12 Figure 2.11 First Example of Anurupyena. 13 Figure 2.12 Second Example of Anurupyena 14 Figure 2.13 Third Example of Anurupyena Figure 2.14 Forth Example of Anurupyena Figure 2.15 Multiplication of two fourth degree polynomials.. 15 Figure 2.16 Vertically Crosswise First Cross Product Figure 2.17 Vertically Crosswise Intermediate Cross Product.. 16 Figure 2.18 Vertically Crosswise Intermediate Cross Product.. 16 Figure 2.19 Different Cross Products of Two Numbers 18 Figure 2.20 Addition of Cross Products 18 Figure 2.21 Complete Example of Squaring.. 20 Figure 2.22 Process of Nikhilam for Division Figure 2.23 Process of Nikhilam for Division Figure 2.24 Process of Nikhilam for Division Figure 2.25 Process of Nikhilam for Division Figure 2.26 Process of Nikhilam for Division Figure 2.27 Another method to get quotient.. 24 Figure 2.28 Example of Nikhilam for Non Suitable Numbers Figure 2.29 Setup for Division Figure 2.30 Complete Example of Dhwajanka.. 26 Figure 2.31 Complete Example of Dhwajanka.. 27 Figure 2.32 Complete Example of Dhwajanka.. 28 Figure 2.33 Complete Example of Dhwajanka.. 29 Figure 3.1 Urdhva-tiryagbhyam Complete Example. 31 Figure 3.2 Conventional Cross Product Addition.. 33 Figure 3.3 Full Adder. 34 Figure 3.4 Wallace tree reduction.. 35 Figure 3.5 Comparison of Multiplication for delay ix

11 Figure 3.6 Improvement over DesignWare Figure 3.7 Comparison of Multiplier Area (Minimum Delay).. 40 Figure 3.8 Area for 8 bit multiplier relaxed designs.. 40 Figure 3.9 Area for 16 bit multiplier relaxed designs 41 Figure 3.10 Area for 23 bit multiplier relaxed designs.. 41 Figure 3.11 Comparison of Total Power for multipliers 42 Figure 3.12 Power dissipation for 8 bit multiplier relaxed designs Figure 3.13 Power dissipation for 16 bit multiplier relaxed designs Figure 3.14 Power dissipation for 23 bit multiplier relaxed designs Figure x4 Multiplication using Wallace tree Addition 45 Figure 3.16 Block level structure of a 4x4 multiplier by Wallace tree reduction.. 46 Figure 3.17 Multiplication by Vedic Mathematics Figure 3.18 Figure Block level structure of a 4x4 multiplier by Vedic reduction.. 48 Figure 3.19 Cross Product for Multiplication 50 Figure 3.20 Cross Product for Squaring 50 Figure 3.21 Comparison of Square for delay 51 Figure 3.22 Comparison of Area for Square (Minimum Delay).. 51 Figure 3.23 Area comparison for relaxed 8 bit designs of square Figure 3.24 Area comparison for relaxed 16 bit designs of square.. 52 Figure 3.25 Area comparison for relaxed 23 bit designs of square.. 53 Figure 3.26 Comparison of Power for Square.. 54 Figure 3.27 Total Power comparison for relaxed 8 bit designs of square Figure 3.28 Total Power comparison for relaxed 16 bit designs of square.. 55 Figure 3.29 Total Power comparison for relaxed 23 bit designs of square.. 55 Figure 4.1 Complete Example of Nikhilam for Division.. 57 Figure 4.2 Complete Example of Dhwajanka 58 Figure 4.3 Dhwajanka Problem of recalculation 59 Figure 4.4 Dhwajanka Solution of recalculation 60 Figure 4.5 Dhwajanka Problem of Negative Quotient Figure 4.6 Dhwajanka Solution for Negative Quotient.. 62 Figure 4.7 Comparison of Division for Delay Figure 4.8 Comparison of Division for Area Figure 4.9 Area comparison of relaxed division Figure 4.10 Comparison of Division for Power Figure 4.11 Comparison of Power for relaxed designs.. 65 Figure 5.1 Terms Required by Taylor Series. 67 x

12 Figure 6.1 First Order Newton Polynomial. 72 Figure 6.2 First Order Lagrange Polynomial. 74 Figure 6.3 Comparisons of Sine and Cosine with DesignWare for Cycle Time Figure 6.4 Comparison of Sine with DesignWare for Area Figure 6.5 Comparison of Cosine with DesignWare for Area Figure 6.6 Area Comparison for Relaxed designs of 8 bit Sine 80 Figure 6.7 Area Comparison for Relaxed designs of 16 bit Sine.. 81 Figure 6.8 Area Comparison for Relaxed designs of 8 bit Cosine... Figure 6.9 Area Comparison for Relaxed designs of 16 bit Cosine.. 82 Figure 6.10 Comparison of Sine with DesignWare for Area Figure 6.11 Comparison of Cosine with DesignWare for Area. 82 Figure 6.12 Area Comparison for Relaxed designs of 8 bit Sine.. 83 Figure 6.13 Area Comparison for Relaxed designs of 16 bit Sine Figure 6.14 Area Comparison for Relaxed designs of 8 bit Cosine.. 84 Figure 6.15 Area Comparison for Relaxed designs of 16 bit Cosine 84 xi

13 Chapter 1 Introduction 1.1 Motivation As a student in India, Vedic Mathematics is a name which is heard many times with reference to the techniques for solving mathematics problem mentally. One of the main purposes of Vedic mathematics is to transform the tedious calculations into simpler, orally manageable operation without much help of pen and paper. Any ordinary human can perform mental operations for very small magnitude of numbers and hence Vedic mathematics provides techniques to solve operations with large magnitude of numbers easily. Vedic mathematics provides more than one method for basic operations like multiplication and division. For each operation there is at least one generic method provided along with some methods which are directed towards specific cases simplifying the calculations further. Today s CPUs are increasingly working on higher frequencies with reduction in size of transistor. Arithmetic and Logic Unit - ALU is one of the most important and critical blocks in CPU. Hence it is imperative to have fast and efficient ALU. Division is the most time consuming amongst the basic mathematical calculation. In today s computing technology functions like Sine and Cosine are also frequently required and are implemented in hardware. With these considerations, it is always important to have fast and efficient mechanism to implement mathematical functions. Vedic mathematics provides algorithms to simplify the mathematics and hence is perfect solution for the problem stated. 1

14 1.2 Goal of this work The goal of this work is to understand and implement the formulas of Vedic Mathematics for binary numbers and assess their use in Computer Arithmetic. The different mathematical functions explored are Multiplication 8 bit, 16 bit and 23 bit multiplication are implemented and synthesized, timing, area and power of the hardware designed is evaluated. Squaring Similar to multiplication 8 bit, 16 bit and 23 bit i.e. single precision squaring hardware design are implemented and evaluated. Sine and Cosine functions are implemented by polynomial approximation and interpolation method and performance is observed. Division algorithm for a 16 by 8 bit division is implemented in Verilog and performance is evaluated. All the above implementations are compared against Synopsys DesignWare blocks which are highly optimized, ready to use functional block. 45nm PDK is used to implement both Vedic designs and DesignWare blocks. 1.3 Related Work Many have proposed the use of Vedic mathematics methods for multiplication, but many of them restrict the implementation to 8 bits. [15] Implements a 2, 3, 4 and 8 bit multipliers by Nikhilam formula and also concludes that multiplication by generic formula Urdhvatiryagbhyam is slower because of the structure. [16] Argues that there is no difference between multiplication done by Vedic and conventional method. [17] Implements Complex 2

15 number multiplier using Vedic mathematics methods and concludes that it is suitable for high speed complex arithmetic circuits. [18] Implements cubing circuit by Anurupyena formula by different structures for 8 bit and infers Vedic carry save cubing is best. [13] Uses Vedic Mathematics formula for 2 2 multiplication and uses it as a block in higher width multiplication, for synthesis XC2S100-5tq144 was used. It can be observed that all the previous work is related to only multiplication and most of the multipliers are implemented using formula Nikhilam or Anurupyena a corollary of Nikhilam with all multiplier implementation done for 8 bits or lower. [19] And [20] use multiplication in applications such as FFT and elliptic curve cryptography. 1.4 Organization This thesis is divided in to 7 chapters. Chapter 2 discusses different Vedic mathematics algorithms available for Multiplication, Squaring and Division for decimal numbers. Then next chapters focus on each of the function. Chapter 3 focuses on multiplication and squaring as they are closely related. Chapter 4 talks about binary division and problems associated with implementation of algorithms in hardware. Chapter 5 discusses methods available for Sine and Cosine and concludes Polynomial Approximation and Interpolation is better suited for implementation of Sine and Cosine functions. Chapter 6 introduces to different methods for Polynomial Interpolation and Approximation and also results obtained in comparing those methods. Chapter 7 is dedicated for summary and future work. 3

16 Chapter 2 Vedic Mathematics The word Vedas which literarily means knowledge has derivational meaning as principle and limitless store-house of all knowledge. The word Veda also refers to the sacred ancient Hindu literature which is divided into four volumes. Vedas are considered to be one of the oldest forms of written records by man. Vedas initially were passed from previous generations to next orally. Later they were transcribed in Sanskrit. A survey of all scripts available of Vedas across different part of India showed no slightest difference in them. Vedas include information from many subjects from religion, medicine, architecture, astronomy, mathematics etc. 2.1 Revival A scholar from India Shri Bharati Krishna Tirthaji after careful study of appix of one of the Vedas Atharvaveda, reconstructed a mathematical system based on the formulas in it. The main purpose of the system was to use some techniques to solve the lengthy mathematics orally or with minimum space utilization on paper. The system of Vedic mathematics is based on 16 Sutras formulas and 13 Up-sutras or Corollaries sutras and Up-sutras Entire mechanics of Vedic mathematics is based on 16 sutras formulas and 13 up-sutras meaning corollaries. Sutras 4

17 1. Ekadhikena Purvena 2. Nikhilam Navatascharamam Dashatah 3. Urdhva-tiryagbhyam 4. Paravartya Yojayet 5. Shunyam Samyasamucchaye 6. Anurupye Sunyamanyat 7. Sankalana vyavakalanabhyam 8. Puranaprranabhyam 9. Calana Kalanabhyam 10. Yavadunam 11. Vyastisamashtih 12. Sheshanynkena Charmena 13. Sopantyadvayamantyam 14. Ekanyunena Purvena 15. Ginitasamucchayah 16. Gunaksamucchayah Up-sutras 1. Anurupyena 2. Shishyate Sheshsamjnah 3. Adyamadye Nantyamantyena 4. Kevalaih Saptakam Gunyat 5. Vestanam 5

18 6. Yavadunam Tavadunam 7. Yavadunam Tavadunikutya Varganka ch Yojayet 8. Antyayordhshakepi 9. Antyatoreva 10. Samucchayagunitah 11. Lopanasthapanabhyam 12. Vilokanam 13. Gunitasamucchyah Samucchayagunitah 2.3 Decimal Multiplication In Vedic mathematics there are 3 methods to implement multiplication. Out of three there is one generic method which can be applied to all cases whereas other two are for special cases which are simpler to deal with. As the main purpose of Vedic Mathematics is to be able to solve complex calculations by simple techniques which can be done mentally, these Vedic formulas require dealing with very small numbers. The formulas being very short their practical application becomes very simple Nikhilam Sutra First formula under consideration is Nikhilam Navatascharam Dashtah which means all from 9 and last from 10. The detailed explanation for the procedure is as follows. We will start from the simple multiplication of 7 x 8 and then move to gradually move towards bigger numbers. 6

19 / 6 Figure Example of Nikhilam 1. Take the base of calculation as power of 10 which is nearest to the multiplicands say M and N. In case considered above it is, say B, Subtract base B from each multiplicand and note two remainders as say m and n. In this case they are -3 and -2 respectively. 3. The product will have two parts. Here they are shown by separator /. Right part is obtained by multiplication of two remainders namely m and n R = m x n Here 2 x 3 = 6 4. Left part can be obtained by various methods as follows. a. Subtract base B from the sum of two multiplicands M and N L = M + N -10 Here = 5 b. Add the sum of two remainders, m and n from base B L = 10 + m + n Here = 5 c. Cross add remainder with multiplicand which is either M+n or N+m L = M + n or L = N + m 7

20 Here 8-3 = 5 or 7 2 = 5 5. The answer is obtained by just concatenating left and right part as LR, here 56. Though this method is applicable to all cases its improvement over conventional multiplication largely deps on closeness of multiplicands to the power of 10. The algebraic illustration of this method is as follows Here x acts as base B which is decided at the start of process. In this method product ab is restricted to the number of digits equal to the power by which 10 has to be raised to get base. If the product has more digits then the extra digits are added to the left had side. In the following illustration as the base in 10, hence allowed digits on right is limited to 1. But as there are 2 digits extra digit is added on left side to get the correct answer = / 0 = 30 Figure Example of Nikhilam Nikhilam Sutra can be used for numbers which are more than base without any limitation. An illustration is as follows 8

21 = Figure Example of Nikhilam In above two cases product ab is positive and hence if it has more digits then the extra digits are added to the left part. This can be further exted to multiply two numbers which are on opposite sides of base. In this scenario product is negative and hence correct carry has to be subtracted from left side to make right side positive within the digit limit according to the base. In the illustration below left product is -15; to make it positive 1 is shifted from right. Another illustration of similar case = 97 / = 9785 Figure Example of Nikhilam = 112 / = 112 / 53 = Figure Example of Nikhilam 9

22 One more case needs to be considered, just as the process multiplication of remainders constituting the right part of the product could contain more digits than permissible, and it may similarly yield a product of remainders with digits less than specified digits. This could be easily dealt with by adding appropriate number of zeros. Illustration = 103 / 02 = Figure Example of Nikhilam Here product has only one digit which is less that the required digits as 2. One 0 is added to the product to make it a 2 digit number and correct answer is obtained by combining two products. Another illustration is shown below = 94 / 09 = 9409 Figure Example of Nikhilam 10

23 The formula becomes more evident when used for numbers containing larger digits. All the digits from 9 and last from 10 help us to find the remainders quickly. Deping upon the digits in remainder which can fall in any one category of normal, sub-normal and supernormal any case can be solved to get the correct answer. Normal In the following illustration remainder for first multiplier is obtained by subtracting all digits from 9 but last digit from = Figure Normal Example of Nikhilam Sub-Normal Multiplication of remainders contains fewer digits Figure Sub-Normal Example of Nikhilam 11

24 Super-Normal Multiplication of remainders contains more digits = / 776 = Figure Super-Normal Example of Nikhilam Anurupyena The reduction in calculation for the multiplication by Nikhilam solely deps on closeness of multiplicands, if not both at least one, to the base which has to be power of 10. In case both the multiplicands are not near power of 10, two large remainders are obtained and their multiplication is not a straightforward task. Vedic mathematics has a corollary Anurupyena to deal with such cases. Anurupyena means proportionality. In application sense it means while consideration the base and calculation of left part of multiplication, a rational proportionality can be used to reduce the calculations. In other words, while calculating the remainders from multiplicands a base can be chosen as some rational multiple of power of 10 such that multiplication of remainders becomes simple. In turn, while calculating the right part of multiplication same proportionality needs to be considered to calculate correct answer. For example, if a suitable base was found to be k times power of 10, right part has to be multiplied by k times to calculate answer. Suppose we have to multiply 43 by 49, by Nikhilam formula, this multiplication translates into multiplication for the left part and right part also has two bigger numbers to deal with. This happens as both multiplicands 12

25 are far away from power of 10, here 100. With some observation we can say that base 50 could be effective as it is closer to at least one of the multiplicand, here it is closer to both. With this corollary we make the base suitable by some multiple of power of 10. Here the multiple is ½. While calculating left part this constant has to be multiplied with number obtained by cross adding multiplicand with remainder. Illustration The procedure is as follows 43 x 49 Base 100 ½ = 50 Initial Base = = 42 ½ / 07 = 2107 Figure First Example of Anurupyena 1. Choose working base conveniently by multiplying power of 10 by a rational number, say k. Here k = 100 / 50 = 1/2 2. Calculate remainders using the base as numbers minus base = = Cross add number and remainder to get the left part of product = Multiply k to this obtained left part to get the final left part of the answer 42 ½ = 21 13

26 5. Concatenate left part with right part which is obtained by multiplication of remainders 21 / 07 = 2107 Note While concatenation all rules stated in previous section arding sub-normal, supernormal product should be followed. Correct answer can be obtained by different choices of base. If we assumed initial base as 10, and base for calculation as 50 then k = 50 / 10 = 5 Base = 10 5 = 50 k = 5 Initial Base = = 42 5 / 7 = 210 /7 = 2107 Figure Second Example of Anurupyena Base = 10 4 = 40 k = 4 Initial Base = = / 7 = /7 = 2107 Figure Third Example of Anurupyena 14

27 Note If multiplication of proportionality constant and left part of product does not result in whole number fraction is shifted to right part by multiplying it to original base. Illustration: Original Base: 1000 New Base = 1000 /4 = = 243 / 4 / 010 = / 010 = 60 / = Figure Forth Example of Anurupyena Urdhva-tiryagbhyam As seen in previous two sections the Nikhilam and Anurupyena are for special cases, whereas Urdhva-tiryagbhyam is general formula applicable to all. Its algebraic principle is based on multiplication of polynomials. Consider we want to multiply two 4 th degree polynomials Ax 4 + Bx 3 + Cx 2 + Dx + E Zx 4 + Yx 3 + Xx 2 + Wx + V AZ x 8 + (AY+BZ) x 7 + (AX+BY+CZ) x 6 + (AW+BX+CY+DZ) x 5 + (AV+BW+CX+DY+EZ) x 4 + (BV+CW+DX+EY) x 3 + (CV+DW+XE) x 2 + (DV+EW) x + EV Figure Multiplication of two fourth degree polynomials 15

28 Highest degree coefficient can be obtained by multiplication of two highest degree coefficients of individual polynomial namely A and Z. A next degree coefficient is obtained by addition of cross multiplication of coefficients of 4 th degree and 3 rd degree of other polynomials. It means A which is 4 th degree coefficient of polynomial-1 is multiplied by 3 rd degree coefficient of polynomial-2 is added to 4 th degree coefficient of polynomial-2 multiplied by 3 rd degree coefficient of polynomial-1 to get (AY+BZ). A B C D E Z Y X W V Figure Vertically Crosswise First Cross Product Similar logic of cross multiplication and addition can be exted till all 5 coefficients of both polynomials are used as follows. Every iteration gives a coefficient of product. A B C D E Z Y X W V Figure Vertically Crosswise Intermediate Cross Product In this iteration, coefficient of degree 4 of product is obtained. For next iteration we drop A and Z which are the highest degree polynomial coefficients. The resulting operation gives coefficient of the degree 3 of multiplication of polynomials. As follows A B C D E Z Y X W V Figure Vertically Crosswise Intermediate Cross Product 16

29 Continuing with this process last coefficient is obtained by multiplication of 0 th degree terms of both polynomials as E*V. This process can be done is both ways as it is symmetric. In summary the process can be stated as, process of addition of product of coefficients of two polynomials in crosswise manner with increase and then decrease in number of coefficients from left to right with crosswise meaning product of coefficients for one polynomial going rightwards while for other leftwards. Any decimal number can be thought as a polynomial with unknown or x equal to 10. Being said that, formula stated above can be utilized to calculate product of two decimal numbers. Each digit of decimal number is though as coefficient of power of 10. Only restriction in this case is each cross product should be only one digit, if not it is added to the next power of 10. Below illustration will make this point clear. Suppose we want to multiply two numbers 3451 and Cross-products are obtained as follows. 17

30 Cross product 1 = 18 Cross product 2 = = Cross product 3 = = 64 Cross product 4 = = Cross product 5 = = 29 Cross product 6 = = Cross product 7 = Figure Different Cross Products of Two Numbers All cross products are combined as follows 18 / 45 / 64 / 58 / 29 / 12 / 3 = Figure Addition of Cross Products As each cross product field can contain only one digit, extra digit is passed to next cross product field. If the addition of cross product and borrowed digit in more than 9, again the extra digit is passed to next cross product. Here if we start from right, 3 is kept as it is. Out of 12, 2 is kept and 1 is passed to next cross product where = 30; out of which 0 is kept and 3 is passed = 61, 1 is kept and 6 is passed = 70; 0 is kept and 7 is passed. 18

31 = 52. After keeping 2, 5 passed to next cross product. 18 being last 5 is added to it and that forms the highest 2 digits of number. Hence the product is Also same answer can be obtained if normal addition of two numbers is done after arranging cross products as shown on right. 2.4 Decimal Squaring Decimal squaring is achieved very quickly for formula Dwandwayoga which means duplex. Duplex of a digit is obtained by multiplication with itself, i.e. duplex of a will be a 2. Duplex of two digit numbers is obtained by doubling their product, duplex of ab is 2 a b. Duplex of three digit number is obtained by addition of square of middle digit and twice product of first and second. So abc will have duplex (2 a c + b 2 ). Illustration: Number Table Duplexes of Numbers 4 16 Duplex 43 2*4*3 = *1* = *3*4 + 2*8*2 = *1*4 + 2*0* = = *2*9 + 2*3*8 + 2*4*7 + 2*5*6 = = *3*3 = 18 It can be observed that calculating duplex is based on Urdhva-tiryagbhyam. To obtain the square of a number, duplexes are calculated starting from a digit on right or left then 19

32 proceeding leftwards or rightwards to add digits while determining duplex and adding the duplexes similar to the addition of cross-products described. Figure 2.21 shows complete illustration = Duplexes No Duplex = = = = = /12/28/46/42/44/33/10/1 = Figure Complete Example of Squaring 2.5 Decimal Division In this section techniques arding division will be discussed. Similar to multiplication Vedic mathematics has 3 different formulas to make division simpler. First formula Nikhilam is a special case formula for numbers which are near power of 10. Paravartaya improves over Nikhilam to solve a larger class of problem, whereas Dhwajanka is a generic method applicable to all. 20

33 2.5.1 Nikhilam The process for Nikhilam Sutra is as follows 1. Calculate base as power of 10 and nearest to divisor, say base B. 2. Subtract divisor from base calculated above, say deficit D. 3. As division yields remainder with maximum number of digits same as number of digits in divisor, represent divid in two different numbers separated by a separator / with right part containing number of digits equal to number of digits in divisor from unit place and left part consisting rest of the digits. 4. Now multiply deficit with first digit of divid from left say M1, call product as P1 and place it below starting from second digit towards right. Add second digit of divid with the digit below it of multiplication M1. 5. Now multiply deficit D with M1 and align the product, say P2, starting from third digit of divid. To get next multiplier digit add third digit of divid second digit of first product P1 and first digit of product P2. 6. Repeat this procedure for number of times equal to digits in left part of the divid. 7. Add Products P x with divid to get quotient and remainder on left and right hands side of separator respectively. Addition should be carried out separately for left and right part separated by separator. Illustration: / 89 = 123 Remainder Base B = 100 (Power of 10 nearest to 89) 2. Deficit D = = 11 21

34 3. As divisor is 2 digits wide, we separate divid in 2 parts. Right part contain 2 digits same as digits of divisor and rest in left part = 110 / 23 M1 = = / P1 2 2 Figure Process of Nikhilam for Division 4. In this step multiply D = 11 to 1 which is first digit from left of divid. Product is aligned from the second digit of divid as shown. Next multiplier m1 is obtained by adding 1 second digit of divid and 1 first digit of product P1 M1 = = 2 5. P2 = M1 * divisor. And aligned with third digit of divid. M1 = = / Figure Process of Nikhilam for Division 6. Continue with the procedure till product of divisor and multiplier align with right part. This matches with correct answer. 22

35 / M2 = = Quotient = 123 Remainder = 76 Figure Process of Nikhilam for Division Additional Notes If after addition right part which is remainder is more than the divisor, subtract divisor from right part to make it below divisor and add 1 to left part. Illustration / Quotient = = 124 Remainder = = Figure Process of Nikhilam for Division A carry generated at right part can be treated in two ways. 1. Subtract divisor as shown above. 2. Add deficit corresponding to the carry and add carry to left part. 23

36 / Quotient = = 124 Remainder = = Figure Process of Nikhilam for Division Figure Another method to get quotient Further Note If addition of divid digit and multiplication digits is more than 10 then the extra carry goes to higher digits.these digits needs to be taken care of as if they are part of divid. Following example will make it clear. 24

37 Quotient = = /41 = 2 R 14 Figure Example of Nikhilam for Non Suitable Numbers It can be observed that if the procedure becomes extra-ordinarily long which is even more than the conventional method. In such cases Anurupyena Proportion formula seen in multiplication can be utilized. Vedic mathematics provides another formula Paravartaya which can deal with such scenario. 25

38 2.5.2 Dhwajanka Vedic mathematics describes a method called Dhwajanka On the top of the flag which is a generalized formula for division. It is based on the formula Urdhva-tiryagbhyam. As seen earlier any decimal number can be represented as polynomial with variable x substituted for 10. Suppose we want to divide by 234 both numbers can be represented in polynomial form as 6x 4 + 4x 3 + x 2 + x + 9 and 2x 2 + 3x + 4 respectively. In the first step to match 6x 4, 2x 2 is multiplied with 3x 2. Other terms in divisor polynomial are multiplied with 3x 2 which is subtracted from divid polynomial. Again after subtraction divisor is multiplied with -2x to make cubic term 0. In this process it can be observed that divisor and quotient coefficients are multiplied and added similar to Urdhva-tiryagbhyam. Dhwajanka process is based on this fact. The actual process of division is performed as follows 1. The divisor and divid are arranged in the form shown below. Only leftmost digit of divisor is left aside. Divid is separated in two sections right part consisting number of digits equal to digits in divisor. Divisor is represented by d, divid by X and quotient by A. d n-1 d n-2. d 1 d 0 X k X k-1 X k-2 X n X n-1.. X 1 d n A k-n A k-n-1 A 1 A 0 Figure Setup for Division 26

39 2. Only first digit of divid is divided by the left out digit, quotient and remainder of this division are noted. 3. During next iteration remainder from previous iteration is used with next digit of divid. Quotient digits and divid digits without leftmost digit are multiplied in vertically and crosswise manner. This product is subtracted from number formed by combination of remainder and digit of remainder. 4. Number left after subtraction in step 3 is divided by left out digit of divisor quotient is noted and remainder is prefixed with rest of the digits of divid. 5. This process is continued till same number of quotient digits equal to digits in left part of divid is obtained. 6. Remainder is obtained by subtraction of right part of divid prefixed by last remainder and cross multiplication of quotient and divisor. Illustration: / 52 = 1446 Remainder = = Figure Complete Example of Dhwajanka 1. Divisor 52 is separated as leftmost digit 5 and rest digits, here 2. As rest digits in divisor contain only one digit, divid is represented as 7512 left /quotient part and 8 as right/remainder part. 27

40 2. First digit of divid 7 is divided by 5, quotient 1 is represented as first digit of quotient with remainder 2 as prefix of other divid digits. 3. Next iteration combination of remainder 2 and second digit of divid which 5 as 25 is formed. Cross multiplication of quotient and rest digits of divisor is calculated which 1 2 = 2 is subtracted from = are divided by 5 giving quotient 4 and remainder Next iteration = / 5 = quotient 4 remainder Next iteration = / 5 = quotient 6 remainder Remainder = 26 7 / 3 = 2 R = / 3 = 4 R = 4 4 / 3 = 1 R Figure Complete Example of Dhwajanka Remainder = ( ) 2 1 = = 47 Illustration Figure Complete Example of Dhwajanka 28

41 In the example above as first digit of divid 1 is smaller than 4, first digit of quotient is 0. Also during calculation of third digit of quotient yields = -7 which is not acceptable. Hence correct way to solve this is during previous division quotient should be taken as 2 which results in remainder of 7 and forms next divisor as 78 instead of 38 and hence can proceed with normal procedure Figure Complete Example of Dhwajanka Remainder = ( ) 7 8 = = 84 Also while calculation of last digit of quotient = / 4 = 10 R1 but with 1, remainder of division would be negative. To keep the legal remainder, quotient is taken as 8 with which correct quotient and remainder are obtained. 29

42 Chapter 3 Multiplication and Squaring After dealing with algorithms available in Vedic mathematics for decimal numbers, this chapter will consider multiplication of binary number system. Vedic Mathematics, as described previously, has three methods Nikhilam, Anurupyena and Urdhva-tiryagbhyam. Considering the binary number system, Nikhilam is not universal method for binary numbers similar to decimal numbers as one multiplier has to be near power of 2. Anurupyena, which gives solution of this problem, is again not a good choice for binary numbers. Anurupyena requires multiplication or division of divisor by a suitable proportionality constant to make it closer to base which is power of 2 in binary number system. Hence proportionality constant has to other than power of 2, and division of this number with one multiplier makes this process unrewarding over conventional methods. Hence, Urdhva-tiryagbhyam, which is universal method for multiplication is chosen for implementation. 3.1 Binary Multiplication - Urdhva-tiryagbhyam Algorithm In binary system only 0 and 1 are used hence multiplication in Urdhva-tiryagbhyam or vertically-crosswise formula is replaced by AND logic. Each AND will be a bit wide and these bits are added together to generate cross-product. Rules for vertically-crosswise multiplication remains same as starting from MSBs Most Significant Bit, of both multiplicands considered for first cross product. Then increasing one bit in each further 30

43 calculation with cross product taken for bits of multiplicands till all bits are used. Further dropping bits from MSB process of cross-product is continued till only LSB is used for cross-product. In binary number system the maximum width of cross-product deps on width of multiplicands. For example, in 8 bit multiplication maximum cross-product width will be log = 4. In 16 bit it will be 5 and in 23 bits it will be 5 again Cross products Combining Cross Products Figure Urdhva-tiryagbhyam Complete Example 31

44 3.1.2 Comparison of Vedic and Conventional Multiplier In this section comparison between Vedic multiplier by Urdhva-tiryagbhyam and conventional multiplier is made. Conventional multiplier of width N x N will generate N number of partial products with each product containing N bits with 0 to 7 zeros added at the. Vedic method generates (2N - 1) cross products of different widths which when combined forms (log 2 N + 1) partial products for N bit multiplier. In case of number of partial products there is significant decrease in number for Vedic Mathematics. But partial products generated in case of conventional multipliers are just by AND one multiplier by digits of another multiplier, whereas in case of Vedic, partial products are obtained after cross products are generated which requires some logic. Hence in Vedic mathematics delay for partial products is equal to adder delay. Critical path would consist of adders adding maximum number of bits in cross product. In all cases it will be the cross product in which all bits of multipliers are considered. Different techniques are used to combine these partial products efficiently to reduce the total time required for multiplication. One such technique Wallace tree addition is discussed in next section Figure Conventional Cross Product Addition 32

45 3.2 Combining Partial Products Combining partial products is the most critical part in any multiplier which decides the performance of it. Different types of adders like Carry Save adders (CSA) or Carry Lookahead Adders (CLA) are used frequently. To further improve the performance more parallelism is achieved by combining three or more partial products at a time until two are left and then to add these two partial products to get the final answer. This technique is called as Wallace tree adder Wallace tree Wallace tree in simplest sense is a full adder which combines 3 bits to produce a carry and a sum which can be seen as a 3 bit to 2 bit reduction. The 3 bits added are at the same power of 2 in any binary number whereas the two bit output produced has one bit at same power of 2 as input but one bit is at 1 power above. In combining large partial products this technique is used in which 3 bits at same power of 2 of different partial products can be combined in parallel. With these techniques 3 partial products can be combined to form 2. If there are more than 3 partial products then multiple stages Wallace adder has to be used. 33

46 Figure Full Adder Consider a 4x4 multiplier, which will have 4 four bit wide partial products. In the diagram below we can see that 3 partial products are combined to form 2 and later again combined with 4 th to make 2 partial products. It can also be observed that in all cases a full adder cannot be used hence a half adder has to be used to combine partial products. Full adder which is a 3:2 -reduction, half adders and 4:2 compressors are common in different configurations of Wallace tree. x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Figure Wallace tree reduction 34

47 In Vedic mathematics sutra Urdhva-tiryagbhyam for N N multiplier, 2N -1 cross-product are generated. As seen earlier, cross-products process is similar to first AND logic and then addition of these bits to form cross-product. Starting from first number of bits is cross product increases till N and then again decreases to 1. Hence these products have widths from l to (log 2 N + 1). Partial products are formed by combining bits at same power of 2 of all cross-products. This forms (log 2 N + 1) partial products. There are two ways by which these partial products can be combined Vedic Wallace If Wallace tree structure with full and half adder is used then the class of multiplier is named as Vedic Wallace multiplier. This type of multiplier essentially defers from conventional multiplier in the way the different bits are combined to form the final answer. 8, 16, and 23 bit multiplier are designed in Verilog with Vedic Wallace structure with each of them customized to that particular width of multiplication to achieve high performance. These multipliers are designed as combinational blocks similar to equivalent DesignWare blocks. Each of these designed are synthesized with Synopsys in two ways 1. To achieve the highest possible clock frequency with which they work 2. Relaxed clock frequency to check the area generated. Power analysis is done in both cases. Results are as follows Vedic Vedic Another way to combine the cross-products is to continue the methodology described in Urdhva-tiryagbhyam. In this all the bits which are at same power of 2 are combined until 35

48 each addition of bits result into two bit numbers which results in two partial products. This class of multipliers is named as Vedic-Vedic multipliers. Similar to previous class of multipliers 8, 16, and 23 bit multiplier are designed in Verilog and synthesized with Synopsys. Each of these designed are synthesized with Synopsys in two ways 1. To achieve the highest possible clock frequency with which they work 2. Relaxed clock frequency to check the area generated. Power analysis is done in both cases. Results are discussed in next sections. 3.3 Comparison with DesignWare DesignWare Implementation DesignWare uses AND logic for generating partial products, sometimes different algorithms of Booth encoding is used. Carry-save addition or Cary-Propagate addition is used deping on the constraints. If Radix-4 Booth encoding is used it is used on one of the multipliers to reduce partial products. Area of medium to large sized multipliers is reduced due to small adder tree also delay is marginally affected but can only improve slightly [27]. Radix-8 encoding further helps to reduce area in case of large multipliers but delay slightly increases due to complexity. Deping on constraints 4 to 2 Compressor Cells, Carry Select Adder cells etc. are used Timing Timing analysis was done by Synopsys tools. Design was compiled by reducing the clock period by 0.4ns, 0.2ns or 0.1 ns successively to achieve fastest possible clock speed. 36

49 Delay ns Following graph shows the minimum clock period achieved for 8, 16 and 23 bits of multiplication for Vedic Mathematics and DesignWare. Vedic mathematics designs had 2 different structures as discussed previously, namely Vedic-Wallace and Vedic-Vedic VedicVedic VedicWallace DesignWare bit 16bit 23bit Multiplication Width Figure Comparison of multiplication for delay It can be observed that both the Vedic methods have less delay than corresponding DesignWare block. Except for 16bit multiplication Vedic-Vedic structure has lower cycle time than Vedic-Wallace. The percentage improvement can be seen in following graph. The analysis for improvement over DesignWare is presented in section

50 PERCENTAGE VedicVedic VedicWallace 2 0 8bit 16bit 23bit Figure Improvement over DesignWare Area Comparison Following graph compares the area of DesignWare, Vedic-Wallace and Vedic-Vedic multiplier for 8, 16, and 23 bits at maximum possible clock frequency. Scatter plots of area for 8 bit, 16 bit and 23 bit multipliers is shown in Figure - 3.8, Figure and Figure respectively. 8 bit multiplier Vedic-Vedic structure results in maximum area for minimum delay and DesignWare results in least. But as the designs are relaxed all the area approaches same value. In contrary 16 bit and 23 bit area of DesignWare is significantly lower than Vedic-Vedic or Vedic-Wallace structures. 38

51 Area square um Area square um VedicVedic VedicWallace DesignWare bit 16bit 23bit Multiplication Width Figure Comparison of Multiplier for Area (Minimum Delay) Delay ns VedicWallace VedicVedic DesignWare Figure Area for 8 bit multiplier relaxed designs 39

52 Area square um Area square um Delay ns VedicWallace DesignWare VedicVedic Figure Area for 16 bit multiplier relaxed designs Delay ns VedicWallace DesignWare VedicVedic Figure Area for 23 bit multiplier relaxed designs 40

53 Power uw Power Comparison Following graph depicts the total power dissipation for different configurations, except 16 bit multiplication where power dissipation is almost same for all, Vedic-Vedic shows more power dissipation than Vedic-Wallace and DesignWare VedicVedic VedicWallace DesignWare bits 16 bits 23 bits Bit Width Figure Comparison of Total Power for multipliers Following figure shows scatter plots for total power dissipation for relaxed designs for 8, 16 and 23 bits. For all three cases of bit width, at minimum delay Vedic algorithms shows more dissipation but relaxed designed approach to one value. 41

54 Power uw Area uw Delay ns VedicVedic VedicWallace DesignWare Figure Power dissipation for 8 bit multiplier relaxed designs Delay ns VedicWallace DesignWare VedicVedic Figure Power dissipation for 16 bit multiplier relaxed designs 42

55 Power uw Delay ns VedicWallace DesignWare VedicVedic Figure Power dissipation for 23 bit multiplier relaxed designs 3.4 Analysis Wallace tree addition makes use of full adder extensively for reducing partial products. Figure 3.3 shows a gate level diagram of a full adder. It can be observed that to generation of sum has to pass through two XOR gates and is inherently slower than generation of carry Critical Path Analysis of a 4 bit multiplier In this section comparison between critical path in 4 bit conventional and Vedic multiplier is done. In a 4 bit multiplier 4 partial products will be generated, in the diagram below named as P0 to P3. 43

56 x x x x x x x x P0 x x x x P1 x x x x P2 x x x x P3 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Figure x4 Multiplication using Wallace tree Addition In above multiplier a 3:2 reduction is used. After first level of Wallace tree 4 partial products are reduced to 3 partial products. As there are 4 bits to combine at power 2 3, in first level only 3 can be combined leaving fourth for next level. It is shown in blue background. This extra bit is combined in next level of reduction. After this level only 2 partial products are left and hence added together to get final answer. The block level diagram of the process is shown below with critical path marked in red. Delay in critical path in terms of half and full adder delays are as follows. Delay = FAS + FAS + HAC + FAC + FAC + FAS = 3 FAS + 2 FAC + HAC Where FAS = Full Adder Carry, FAC = Full Adder Carry, HAC = Half Adder Carry, HAS = Half Adder Sum, FA = Full Adder and HA = Half Adder. 44

57 Figure Block level structure of a 4x4 multiplier by Wallace tree reduction In case of Vedic mathematics as bits at same power of two are added in one level. Hence 4 bits which are at power 2 3 are added together to get a 3 bit sum. The MSB of this sum is at power 2 5. If we compare the combination of partial product in Vedic and conventional the extra bit is at power 5 in Vedic compared to at power 3 for conventional. This carry forwarding is achieved with extra delay of a Half Adder Sum (HAS). Multiplication with Vedic structure is shown below. Figure 3.16 shows the critical path in red. 45

58 x x x x x x x x P0 x x x x P1 x x x x P2 x x x x P3 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Figure Multiplication by Vedic Mathematics Critical Delay = HAS + HAC + HAS + HAS + HAS + FAC + FAC + FAS = 2 FAC + FAS + 3HAS + HAC After comparing this with critical delay of conventional multiplier and cancelling equal terms we get 2 FAS Full Adder Sums for conventional against 3 HAS - Half Adder Sums for Vedic. In terms of XOR gate this delay corresponds to 2 2 = 4 XOR gate delay for conventional against 3 1 = 3 XOR gate delay for Vedic multiplier. This analysis shows that 4 bit Vedic multiplier has less carry propagation delay than Wallace tree multiplier. Also for 46

59 4 bit design there is no difference between Vedic-Vedic and Vedic-Wallace structures. Deping upon the number of bits in multiplication Vedic mathematics structure and Wallace tree structure critical path varies and hence there is variable improvement in Vedic- Vedic and Vedic-Wallace structure over DesignWare. Figure Block level structure of a 4x4 multiplier by Vedic reduction 47