TRANSITION CONFLICTS DETECTION IN BINARY MODULAR STATECHART DIAGRAMS 1. Grzegorz Łabiak

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1 TRANSITION CONFLICTS DETECTION IN BINARY MODULAR STATECHART DIAGRAMS 1 Grzegorz Łabiak Computer Engineering & Electronics Department, University of Zielona Góra, Podgórna 50, Zielona Góra, Poland. G.Labiak@iie.uz.zgora.pl Abstract: Statechart diagrams are graphic formalism for modelling digital controller behaviour. Statecharts employ notion of traditional state transition graph enhanced with concurrency, hierarchy and broadcast communication. One of undesirable problem which arises in specifying behaviour in this way is undeterministic situation, where at given instant of time, two or more transitions can move activity from one state. If this happens, the transitions are said to be in conflict. Conflicts can be both horizontal and, because of hierarchy, vertical. In the paper two methods of searching for conflicting transitions are presented: static based on hierarchy diagram and dynamic using characteristic function of space of global states. Keywords: Statecharts, Hierarchical control, Modelling, Behaviour, Deterministic behaviour, State-space method 1. INTRODUCTION The statecharts formalism was developed as a visual formalism for complex systems (Harel 1987). It is a state-base graphical notation which can be perceived as extension of state transition graph of traditional finite state machine. In comparison with FSM they are enhanced with concurrency, hierarchy and broadcasting mechanism. A the present time statecharts are mainly used in UML technology (Booch et al. 1999), (UML 2003) where are exploited in behaviour modelling of program object (in sense of C++ or Java language). Since recently, UML is gaining in popularity as tool for hardware design (Balzarini et al. 2003), (Marchetti and Oliver 2003) and system HiCoS is an author s proposition of a CAD program (Łabiak 2004), which directly transforms behaviour specified with statecharts into Register Transfer Level VHDL. The 1 The scientific work is sponsored by State Committee for Scientific Research in the years as a research project number 4 T11C transformation is realized as one-hot mapping (Łabiak 2003a), that means one state responds to one flip-flop. The system implemented in programmable device reacts to the set of incoming events through transitions executions. So, statechart diagram serving as a model behaviour must be deterministic. This can be assured by finding conflicting transitions and next by solving the conflicts. 2. SYNTAX OF STATECHARTS The big problem with statecharts is syntax and semantics. A variety of applications domain caused that many authors proposed their own syntax and semantics (von der Beeck 1994), sometimes differing significantly. Syntax and semantics presented in this paper are intended for specifying the behaviour of binary digital controllers which would satisfy as much as possible the UML statndard (UML 2003). Not every element of UML statechart syntax is supported in HiCoS approach. The selection of language characteristic was

&' ) %( $ (#("!, - * + 0 -. / Fig. 1. Example of Statechart diagram made based on application domain and the technical constrains of programmable logic devices.

2 &' ) %( $ (#("!, - * / Fig. 1. Example of Statechart diagram made based on application domain and the technical constrains of programmable logic devices. As a result of those considerations it was assumed that system HiCoS is to be intended for untimed control systems which operate on binary values. Moreover, the research was divided into two stages, delimiting them with a modular paradigm (Łabiak 2003b). Hence, HiCoS statecharts characterize by hierarchy and concurrency, simple state, composite state, end state, discrete events, actions assigned to state (entry, do, exit), simple transitions, history attribute and logic predicates imposed on transitions. Another very essential issue is to allow the use of feedbacks, it means that events generated in a circuit can affect its behaviour. The role of an end state is to prevent removing away an activity from a sequential automaton before the end state became active. Such elements as factored transition paths and time were rejected, whereas others as cross-level and composite transitions, synch states have been shifted to the second stage of the research. An example of statechart is depicted in figure 1, where event a is an input to the system and event b is an output. Events b and c are of local scope. Fig. 2. Simple diagram and its waveform called a step and additionally it is assumed that during a step no events can come from the outside world. A step is said to be finished when there is no enabled transitions. Figure 2 depicts a step which consists of two simple microsteps. After the step is finished the system is in state STOP. Summarizing, dynamic characteristics of hardware implementation are as follows: system is synchronous, system reacts to the set of available events through transition executions, generated events are accessible to the system during next tick of the clock. In figure 2 a simply diagram and its waveforms illustrate the assumed dynamics features. When transition t 1 is fired (T = 350) event t 1 is broadcast and becomes available to the system at next instant of discrete time (T = 450). The activity moves from state START to state ACTION. Now transition t 2 becomes enabled. Its source state is active and predicates imposed on it (event t 1 ) is met. So, at instant of time T = 450 the system transforms activity to the state STOP and triggers event t 2, which does not affect any other transition. The step is finished. 3. SEMANTICS A digital controller specified with a Statechart and realized as an electronic circuit is meant to work in an environment which prompts the controller by means of events. It is assumed that every event (incoming, outgoing and internal) is bound with a discrete time domain. The controller is reacting to the set of accessible events in the system through firing a set of enabled transitions called a microstep. Because of feedback, execution of a microstep entails generating farther events and causes firing subsequent microsteps. Events triggered during a current microstep do not influence transitions being realized, but are only allowed to affect behaviour of a controller in the next tick of discrete time, that is, in the next microstep. A sequence of subsequently generated microsteps is 4. HARDWARE MAPPING The main assumption of a hardware implementation behaviour described with statechart diagrams is that the systems specified in this way is to be directly mapped into the programmable logic devices. This means that elements from a diagram (for example states or events) are to be in direct correspondence with resources available in a programmable device mainly flip-flops and programmable combinatorial logic. Based on that assumption and taking into account the assumed dynamic characteristics, the following principles of hardware implementation have been formulated: each state is assigned one flip-flop activity means that the state associated with the flip-flop can be active or in the case of a state with a

3 history attribute its past activity is being remembered; an activity of state is established on the basis of activity of flip-flops assigned to superordinate states (in the sense of a hierarchy tree), each event is also assigned one flip-flop activity means the occurrence of an associated event and is sustained to the next tick of discrete time when the event becomes available to the system, based on the diagram topography and rules of transition executions, excitation functions are created for each flip-flop in a circuit. 5. GLOBAL STATE, STATE ACTIVITY, CHARACTERISTIC FUNCTION AND ENABLING TRANSITIONS To investigate symbolically dynamic characteristics of digital controllers specified with statechart diagrams it is necessary to introduce notions of global state (also called marking (Biliński 1996)), activity condition, characteristic function and to define transition enabling condition. Definition 1. Global state G is a set of all flip-flops in the system, bound both with local states and with distributed events, which can be generated in several parts of the diagram and separately memorized. The diagram from figure 1 consists of 10 state flipflops (s 1, s 11, s 12, s 2, s 3, s 4, s 5, s 6, s 7, es) and 3 event flip-flops (e 1, e 2, e 3 ). The flip-flop denoted as e 1 corresponds to the exit event a assigned to state s 2, e 2 corresponds to the entry action (b) to state s 5, and e 3 corresponds to the transition action (broadcasting of event b) bound with transition t 5 firing (from state s 7 to state s 6 ). Global states comprise all information about the statechart both about currently active states and their past activity. An activity of a state flip-flop does not mean activity of a state bound with the flip-flop. Logic 1 on flip-flop output means actual or recent state activity. Hence, state activity is established on the basis of activity of flip-flops assigned to the superordinate states. The state is said to be active when every flip-flop bound with the states belonging to the path (in the sense of hierarchy tree) carried from the state to the root state (located on top of a hierarchy) is asserted. Formally, a state activity condition is calculated according to the following definition: Definition 2. State activity condition, denoted as activecond(s), is calculated as follows: activecond (s) = s i (1) s i path(root z,s) where s i is a signal from the flip-flop s output and path(root z, s) is a set of states belonging to the path carried between root z and s in hierarchy tree. Fig. 3. Hierarchy graph (a.k.a. AND-OR tree) for the diagram from figure 1 For example, activecond(s 6 ) = s 1 s 11 s 3 s 6 (cf. figure 3 where this path is thickened). The sets of global states and operations on them can efficiently be represented in computer memory by means of Binary Decision Diagram (BDDs) (Minato 1996) (Somenzi 2004) and characteristic functions (Biliński 1996). Definition 3. A characteristic function χ A of a set of elements A U is a Boolean function χ A : U {0, 1} defined as follows: { 1 x A X A (x) = (2) 0 x A. The characteristic function is calculated as a disjunction of all elements of A. Operations on sets are in direct correspondence with operations on their characteristic functions. Thus: X (A B) = X A + X B, X (A B) = X A X B, X ( A ) = X A, X ( ) = 0. (3) For example characteristic function of the set of all global states for the diagram from figure 2 is as follows: χ [G0 = start t 1 action entr d ext t 2 stop + + start t 1 action entr d ext t 2 stop + + start t 1 action entr d ext t 2 stop + + start t 1 action entr d ext t 2 stop. The characteristic function allows sets to be represented by BDDs. BDDs are very convenient means for the sets of global states to act on them (Somenzi 2004), for example to generate state space of global states of the statechart or to find conflicting transitions. For these reasons transition enabling condition is defined: Definition 4. Transition enabling condition, denoted as encond(t), is calculated in following way:

4 encond (t) = activecond (out (t)) intcond (out (t)) trigger (t). (4) In the definition (def. 4) activecond(out(t)) is a state activity condition of a transition t source state; intcond(out(t)) is a preemption internal condition of a transition t source state, which is fulfilled when every subordinate end states (if exist) are active; trigger(t) is a predicate imposed on transition, which is Boolean expression composed of names of events. For example for transition t 4 from the diagram from figure 1 encond(t 4 ) = s 1 s 11 s 3 s 6 a b, for whom activecond(t 4 ) = s 1 s 11 s 3 s 6, intcond(t 4 ) = 1, trigger(t 4 ) = a b. 6. THE CONFLICTS Two transitions are in conflict if there is some common state that would be exited if any one of them were to be fired (Harel and Naamad 1996). In distinction from FSM and Petri nets statecharts conflicting transitions can be grouped into three categories: horizontal, vertical, mixed. The first case takes place when the transitions in conflict are on the same level of hierarchy tree. In figure 4 horizontally conflicting transitions are t 2 and t 3 and the common state is s 3. The second case holds when conflicting transitions are located on different levels of hierarchy tree. In figure 4 vertically conflicting transitions are transitions t 1 and t 2 and also t 1 and t 3, whereas the common state is again s 3. The case of transition t 1, t 2 and t 3 from figure 4 at the same time combine features horizontally and vertically conflicting transitions, so the conflict of those three is of mixed type at once. Having established transitions or a group of transitions in conflict, it is desirable from hardware implementation point of view to solve the conflicts. In HiCoS approach conflicts between transitions are being resolved by means of predicates, where predicates are Boolean expression made of logic operators and Fig. 4. The example of transitions in conflict names of events. For example the diagram from figure 1 is conflict-free, because predicates imposed on potentially conflicting transitions (t 4, t 5, t 6 ) are orthogonal. Moreover, predicates are constructed in such way that transition t 6 has priority over two remaining transitions. The triggering three events (a, b, c) at same time while active states are s 6 or s 7 will always result in firing transition t 6 whose predicate is bound with event b. The effect is achieved by use of negated event (!b). 7. TRANSITION CONFLICT DETECTION Conflict between transitions can be solved by means of predicates, but before this can be done conflicting transition have to be detected. This can be conducted in two manner: statically and dynamically. 7.1 Static Conflict Detection Static conflict detection consist in searching through hierarchy tree. The goal of searching is to establish the sets potentially conflicting transitions related to each leaf state s. The potentially conflicting transitions are those transitions, which are outgoing transitions from states belonging to the path carried from leaf node s to the root node: T s = s i path(root,s) s i. (5) Next, having found the sets potentially conflicting transitions related to each leaf state, following condition must be met for each pair of the transitions to be conflict-free: t i,t j T s trigger(t i ) trigger(t j ) = 0 and i j (6) where card(t s ) > 1. For example for the leaf states for the diagram from figure 1 T s6 = {t 4, t 6 } and T s7 = {t 5, t 6 }. The conflictfree condition for transitions related to state s 6 is a!b b = 0 and for transitions related to state s 7 is c!b b = 0. The computational complexity of this method depends on the size of hierarchy tree rather than on behavioural properties. Every diagram tested with this method will always be conflict-free. But sometime there are some diagrams, which are tested positively in this way turns out not to be conflicting. Logic related to transitions of such simpler predicates (not orthogonal) consumes less hardware resources of the target programmable devices. So new method of findings conflicts is required, more precise and hence more time consuming.

5 Fig. 5. The example of conflict-free diagram 7.2 Dynamic Conflict Detection Dynamic conflict detection is a methodology based on symbolic state space exploration algorithm. Global states space of a controller is traversed and for every global state the sets of potentially conflicting transitions are being checked against conflicts. Because statecharts diagrams are enhanced with broadcast communication, there are some situation which are positively tested in static way, in fact they are not the conflict. The example is depicted on figure 5. The set of events in the system is E z = {a, b, c}. An event a is the event coming from an surrounding environment, events b and c are internal events, generated within the scope of the diagram and the event c is additionally visible to the outside world. The sets of potentially conflicting transitions (eq. 5) are T s3 = {t 1, t 2 } and T s5 = {t 1, t 3 }. As it is can be concluded from the diagram (figure 5) the condition 6 is not met for the transitions sets but the transitions are not in conflict. Transition t 1 will only be fired after transitions t 2 and t 3, in turn, are realized. This is because internal event c, which is triggering part of t 1, is action part of transition t 3. Similar reasoning can be carried out for an end state. To prove that diagram is conflict-free, in this paper is proposed to check for every set of potentially conflicting transitions and for every global state of statechart whether each pair of transitions in the set are in conflict. This can be conducted by means of modified symbolic state space generation algorithm (figure 6). Figure 6, in C++ language style, depicts the algorithm of dynamic conflict detection. Variables in italic reps y m b t r a v o f S t a t e c h a r t ( Z, i n i t m a r k ) { 2 χ [G0 = curr mark = i n i t m a r k ; while ( c u r r mark!= 0) { 4 f o r each l e a f s t a t e s i n Z f o r each p a i r t i, t j T s, where i j 6 i f ( curr m a r k encond(t i ) encond(t j )!= 0) throw C C o n f l i c t ( s ) ; 8 n e x t m a r k = im comp ( Z, c u r r m a r k ) ; c u r r m a r k = n e x t m a r k χ [G0 ; 10 χ [G0 = c u r r m a r k + χ [G0 ; } 12} Fig. 6. The algorithm of dynamic conflict detection resent characteristic functions of corresponding sets of global states and operations on the set are carried out according to the equations number 3. The algorithm starts from initial global state (init mark, line no. 2) and next in one iteration generates in breadthfirst manner a set of all possible next states (line no. 8). In line number 9 set of next states (next mark) is compared with the set of all global states reached so far (χ [G0 ) and the new global states are remembered in variable curr mark. In line 10 newly generated states are being added to the set of all so far generated states. The im comp function in one formal step performs a computation of a set of global states which can be reached from curr mark in one iteration, according to the following formula: next mark = s x (curr mark n [s i (curr mark δ i(s, x))]) (7) i=1 next mark = next mark s s (8) where s, s, x denote,respectively, the present global state, the next global state and the input event variables; s and x represent existential quantifications of the present state and the input event variables; symbols and represent logic operators XNOR and AND respectively. In lines 4 7 for each leaf state s and for each pair of transitions from the set of potentially conflicting transitions T s is being checked whether these two transitions are conflict-free against the set of current global states represented by curr mark. When conflict holds the condition in line 6 is not equal 0 and an exception CConflict with the name of leaf state is being thrown. The algorithm breaks. Let diagram depicted in figure 5 serves as an example. The leaf states to whom the sets of potentially conflicting transitions are assigned are s 3 and s 5. The statechart starts from initial marking init mark = s 1 s 2 s 3 s 4 s 5 s 6 b c. In this initial global state the only enabled transition is t 2, so at this stage the situation is conflict-free. The condition from line 6 from algorithm in figure 6 for both leaf states is equal 0. Table 1 shows detailed description of each iteration of the diagram for state s 3. Table 1. Iterative execution of the diagram from figure 5 and the calculation for the leaf state s 3. No. E curr curr mark encond(t 1 ) encond(t 2 ) 1 {a} s 1 s 2 s 3 s 4 s 5 s 6 b c s 1 c s 1 s 3 a = 0 2 {b} s 1 s 2 s 3 s 4 s 5 s 6 b c s 1 c s 1 s 3 a = 0 3 {c} s 1 s 2 s 3 s 4 s 5 s 6 b c s 1 c s 1 s 3 a = 0 4 s 1 s 2 s 3 s 4 s 5 s 6 b c s 1 c s 1 s 3 a = 0 E curr the set of currently accessible events, support of curr mark is {s 1, s 2, s 3, s 4, s 5, s 6, b, c}, activecond(t 1 ) = s 1, intcond(t 1 ) = 1, trigger(t 1 ) = c, activecond(t 2 ) = s 1 s 3, intcond(t 2 ) = 1, trigger(t 2 ) = a.

6 The space of all global states consist of 4 states, which in case of this diagram corresponds to 4 iterations. In iterations 1, 2 and 4 the condition (figure 6, line 6) equals to 0, because in characteristic function of current global states event c is negated (c this means that event c is absent), whereas in enabling condition of transition t 1 the event is in normal form (c). In case of iterations number 3 event c is present, but the condition (figure 6, line 6) is zeroed by activity condition of transition t 2 source state (s 3 ). This condition is s 1 s 3 but in global state in iteration 4 the state s 3 is not active and flip-flops bound with this activity have zeros on their outputs (s 1 s 3 in curr mark). The diagram is conflict-free. 8. SUMMARY The conflict (both horizontal, vertical and mixed) takes place if there is a common state such that firing two or more transition outgoing from this state, at the same instance of time, makes that activity is removed from this state. Before behaviour modelled with statecharts is implemented in digital circuit the conflicts must be detected and next with predicates solved. Detecting a conflict can be carried out statically or dynamically. The former method consists in searching through hierarchy tree, whereas the latter one uses modified symbolic state space generation algorithm. Dynamic detecting, in comparison with static detection, is more precise and more computationally complex, but computation can efficiently be conducted with BDDs. The use of dynamic detection can lead to simplifying transition related logic. on specification & Design Languages FDL 03. Frankfurt am Main. pp Łabiak, G. (2003b). The use of hierarchical model of concurrent automaton in digital controller design. PhD thesis. Warsaw University Of Technology, Faculty of Electronics and Information Technology. Warsaw. in polish. Łabiak, G. (2004). HiCoS Homepage. glabiak. Marchetti, M. and I. Oliver (2003). Towards a Conceptual Framework for UML to HardwareDescription Language Mappings. In: Proceedings of Forum on specification & Design Languages FDL 03. Frankfurt am Main. pp Minato, S.-I. (1996). Binary Decision Diagrams and Applications for VLSI CAD. Kluwer Academic Publishers. Boston. Somenzi, F. (2004). CUDD: CU Decision Diagram Package Release WWW. Department of Electrical and Computer Engineering University of Colorado at Boulder. UML (2003). OMG Unified Modeling Languag Specification Version 1.5. von der Beeck, M. (1994). A Comparison of Statecharts Variants. In: Proc. of Formal Techniques in real-time and Fault-Tolerant Systems, Third International Symposium. pp LNCS. Springer-Verlag. REFERENCES Balzarini, F., A. Kostadinov, M. Prevostini, A. Minosi, S. Mankan and A. Martinola (2003). UMLbased Specifications of an Embedded System oriented to HW/SW partitioning: a case study. In: Proceedings of Forum on specification & Design Languages FDL 03. Frankfurt am Main. pp Biliński, K. (1996). Application of Petri Nets in parallel controllers design. PhD thesis. University of Bristol, Electrical and Electronic Engineering Department. Bristol. Booch, G., J. Rumbaugh and I. Jacobson (1999). The Unified Modeling Language User Guide. Addison Wesley Professional. Harel, D. (1987). Statecharts: A Visual Formalism for Complex Systems. Science of Computer Programming 8, Harel, D. and A. Naamad (1996). The STATEMATE Semantics of Statecharts. ACM Trans. Soft. Eng. Method. Łabiak, G. (2003a). From UML statecharts to FPGA - the HiCoS approach. In: Proceedings of Forum

MOST today s embedded real-time systems, e.g. telephone,

MOST today s embedded real-time systems, e.g. telephone, INTL JOURNAL OF ELECTRONICS AND TELECOMMUNICATIONS, 2012, VOL. 58, NO. 4, PP. 411 418 Manuscript received October 31, 2012; revised Decemer, 2012. DOI: 10.2478/v10177-012-0056-9 The Problems of Transition