Design Tools for Oscillator-based Computing Systems

Transcription

1 Design Tools for Oscillator-base Computing Systems Tianshi Wang an Jaijeet Roychowhury Department of Electrical Engineering an Computer Science, The University of California, Berkeley, CA, USA Contact author. ABSTRACT Recently, general-purpose computing schemes have been propose that use phase relationships to represent Boolean logic levels an employ self-sustaining nonlinear oscillators as latches an registers. Such phase-base systems have superior noise immunity relative to traitional level-encoe logic, hence are of interest for next-generation computing using nanoevices. However, the esign of such systems poses special challenges for existing tools. We present a suite of techniques an tools that provie esigners with efficient simulation an convenient visualization facilities at all stages of phase logic system esign. We emonstrate our tools through a case stuy of the esign of a phase logic finite state machine (FSM). We buil this FSM an valiate our esign tools an processes against measurements. Our plan is to release our tools to the community in open source form. 1. INTRODUCTION For ecaes, Moore s law [13] has been the riving force behin the growth of the semiconuctor inustry an the rapi progress of computing power. However, serious esign an manufacturing roablocks are starting to slow own this tren [22]. For example, noise an variability are having an ever-greater impact on system performance as transistors are further miniaturize; power consumption has also been of serious concern for many years. With such obstacles impeing progress in computing, there has been a search for alternative computing paraigms. One broa irection being explore is alternatives to conventional planar silicon CMOS transistors, e.g., new evice structures such as multigate transistors [10], new materials incluing graphene [14] an carbon nanotubes [16], an new evices in alternative omains such as optics an spintronics [2, 3]. In another irection, novel systemlevel esigns are being explore to alleviate power consumption concerns, e.g., improve micro-architectures, avance power management, multi-core chip esigns with multi-threae software [8], etc. Most explorations of alternatives have concentrate on the evice an architectural levels. Another irection, alternative low-level physical representations of abstract logic, has also attracte attention recently. In conventional computing systems, binary logic is typically encoe as two stable voltage levels; CMOS technology provies an excellent substrate for such level-base computation. However, an alternative low-level mechanism for encoing logic, using relative phase ifferences from a reference signal (REF), has been shown to hol consierable promise. The notion of phase-encoe computing ates back to ecaes ago. In the 1950s, Eiichi Goto an John von Neumann propose schemes for implementing computation with phase logic as alternatives to the vacuum tube technology then use in computers [19, 21, 9]. They evise resonant circuits, riven by AC power sources, that oscillate at integer sub-multiples of the AC riving frequency an feature multiple stable phase states, which they use for logic encoing. Goto s resonant circuit was terme the Parametron; in 1958, he use it to buil the PC-1, a computer base on the Parametron. Comput- Permission to make igital or har copies of all or part of this work for personal or classroom use is grante without fee provie that copies are not mae or istribute for profit or commercial avantage an that copies bear this notice an the full citation on the first page. Copyrights for components of this work owne by others than ACM must be honore. Abstracting with creit is permitte. To copy otherwise, or republish, to post on servers or to reistribute to lists, requires prior specific permission an/or a fee. Request permissions from Permissions@acm.org. DAC 15, June 07-11, 2015, San Francisco, California, USA. Copyright 2015 ACM /90/01...$ DOI: ers base on Parametrons were once popular in Japan but quickly gave way to transistor-base computers with level-base logic encoing. Later versions of Goto s Parametron employe superconucting Josephson junctions to improve spee an energy consumption; however, they still remaine unsuitable for large-scale integration an have been limite in application. Recently, the phase logic iea has been revisite with new mechanisms an schemes propose in [18, 15]. The new phase logic framework is terme PHLOGON: PHase-base LOGic using Oscillatory Nano-systems. Instea of passive resonant circuits riven by AC power, PHLOGON uses DC-powere self-sustaining nonlinear oscillators as phase logic components. When perturbe with a synchronization signal (SYNC) that oscillates at integer multiples of its natural frequency, such oscillators feature Sub-Harmonic Injection Locking (SHIL), a phenomenon via which the oscillator s phase can lock to SYNC s in multiple ways. These multiple sub-harmonic phase locks can then be use to encoe logic bits. With SHIL as the central mechanism, a broa choice of nonlinear oscillators become potential caniates for implementing PHLOGON systems, incluing many that can be integrate an consume very little power. Moreover, phase encoing offers better noise immunity compare with levelbase encoing [18, 15]. With noise an power acting as toay s central barriers impeing the progress of computing, these features of PHLOGON have mae it an interesting an promising alternative to conventional level-base logic computation. However, the esign of PHLOGON systems poses new challenges to existing tools. PHLOGON systems use nonlinear oscillators as unerlying logic components. The simulation of even a single oscillator is often non-trivial, to say nothing of many of them connecte together for logical computation. In particular, stanar SPICE transient simulation is often not well suite for capturing oscillator phases, central to phase-base logic encoing, accurately an efficiently. These challenges are etaile in Section 2; no existing tools with emphasis on phase-base computation are conveniently available to esigners. In this paper, we present a set of esign tools that can overcome these ifficulties. The tools use phase-macromoel-base techniques (etaile in Section 2) that enable irect simulation an visualization of the phases of oscillatory signals in a PHLOGON system. In particular, the tools can preict whether SHIL will happen, an when it oes, estimate the locking range an locking phase error key properties to assess the latch s ability to store a bit. They also provie convenient simulation an visualization of the logic bit s flipping behaviour uner the control of logic inputs. These features are of key importance uring the esign of oscillator latches; our tools have mae their characterization convenient. Once iniviual oscillator latches have been esigne, the tools perform full system simulation using phase macromoels for efficiency an improve visualization. We emonstrate the capabilities of our tools by using them to esign example ring-oscillator-base latches an a proof-of-concept FSM, showing how the tools are useful at every stage in the esign of a PHLOGON system. Using the esign tools, we have built a phase logic FSM on breaboars an verifie its logical operation through oscilloscope measurements. This state machine, to our knowlege, is the first one built with DC-powere oscillators an phase-base logic encoing. Without the esign tools, esigning, builing an ebugging even this simple state machine woul have been much more ifficult, perhaps impossible. The rest of this paper is organize as follows. In Section 2, we etail the challenges pose by the esign of PHLOGON systems, an the contributions of our esign tools in overcoming these ifficulties. In

2 Section 3, we provie backgroun on oscillator PPVs an the Aler equation, concepts central to our tools. Then, in Section 4, we present our tools an emonstrate their use for the esign of a ring-oscillatorbase phase logic computation system, illustrating their mechanisms an capabilities along the way. Using insights an results from the esign tools, we have built a ring-oscillator-base PHLOGON state machine; in Section 5, we valiate the accuracy an efficiency of the esign tools against both stanar transient simulations an measurements of actual circuit implementations. 2. PHLOGON DESIGN CHALLENGES AND OUR CONTRI- BUTIONS The general esign flow of a PHLOGON system is shown in Fig. 1. Designers start from a self-sustaining nonlinear oscillator, attach SYNC an logic control inputs to make it a phase logic latch, then construct state machines with latches an logic gates 1. The effective an efficient esign of such a system requires simulation tools that can conveniently assist esigners in the following esign stages: Figure 1: Design flow of PHLOGON systems an esign tools require. Tools in re bol fonts are ones currently not conveniently available to esigners. 1. Attaching SYNC for bit storage: simulation shoul be able to preict whether SHIL will occur given a esign. It shoul estimate the locking range with respect to system parameters an inputs. 2. Attaching logic inputs for bit flip: simulation shoul be able to capture the transient behaviour of phases shifting from one locke state to another. This is central to the timing analysis of phasebase logic latches. 3. Full system simulation for PHLOGON: efficient simulation that irectly captures phase transitions is neee to simulate the logic operation as well as timing of the final system. At these esign stages, stanar SPICE-level transient simulation is not suitable ue to accuracy an efficiency reasons [5, 20]. Oscillators feature phase stability, causing numerical errors in phase to accumulate without boun. This reners the SPICE-level transient simulation results meaningless for systems that operate base on phase logic. For acceptable accuracy, tiny time steps are neee in each oscillation cycle, making computation very expensive for PHL- OGON systems, where thousans of cycles are often simulate for phase transitions to perform logic operation. Also, the occurrence of IL/SHIL is often har to estimate by eye from SPICE-level transient results. Apart from all these, even if such a long transient simulation is performe accurately, it oesn t provie much insight into the improvements of the system, so the esign will be largely base on trial-an-error. Therefore, as shown in Fig. 1, more efficient an convenient tools that can irectly aress the nees of PHLOGON esigners are highly esire. In comparison, our esign tools implement techniques base on Perturbation Projection Vector (PPV) macromoels [6, 7, 23, 17] an the Generalize Aler s Equation (GAE) [4]. They provie esigners 1 Majority an Not operations constitute a logically complete set [18] an they are use in PHLOGON to buil combinational logic blocks with all the capabilities shown in Fig. 1, incluing many that are not currently conveniently available. 1. For bit storage in latches: the esign tools can automatically extract PPV macromoels from an oscillator using both time-omain [7, 23] an frequency-omain [17] methos, erive the GAE from the PPV an calculate its equilibrium state to provie convenient visualization of locking range when sweeping system parameters. 2. For bit flip in latches: with the presence of logic control inputs, through the calculation of the GAE s equilibrium state, the esign tools can irectly return the phase error of a locke state with respect to a reference phase. This can be use to visualize a latch s logic function, i.e., verify its truth table with logic inputs. Also, the transient solutions of GAE macromoel are also available with the esign tools to visualize the bit flip transient behaviour irectly in phase omain. 3. Full system transient simulation with phase macromoels: after constructing PPV macromoels, the esign tools can irectly simulate the transient behaviour of the phases of the oscillators in a PHLOGON system. The results can be use not only to reprouce SPICE-level transient results more efficiently, but also to provie visualization of the system s logic operation in the phase omain. The techniques use in the esign tools, although the theory of them has been establishe ([6, 7, 23, 17, 4]), o not have open-source or commercial implementations conveniently available to esigners, nor have they ever been applie to the esign an analysis of phase logic computation systems before. Our esign tools implement the simulation techniques, an also inclue visualization moules associate with them that are specially esigne for phase logic operations. We expect to release the simulation an visualization tools as well as examples of PHLOGON systems implemente using them freely as open-source software to facilitate the exploration of phase-base logic computation. 3. PPV MACROMODEL AND GAE A nonlinear self-sustaining oscillator uner perturbation can be escribe mathematically as a set of Differential Algebraic Equations (DAEs): t q( x)+ f( x)+ b(t) = 0 (1) where x R n are the unknowns in the system, b(t) is a small timevarying input. The oscillator s response can be approximate well as x(t) = x s(t+α(t)) (2) where x s(t) is the oscillator s steay state response without perturbation ( b(t) 0); α(t) is the phase shift cause by the external input an is governe by the following ifferential equation: t α(t) = vt (t+α(t)) b(t) (3) where the vector v(t) is known as the Perturbation Projection Vector (PPV) [6] of the oscillator. Assume the oscillator s natural frequency is f 0 = 1/T 0. Then v(t) is a T 0-perioic vector that can be extracte numerically from the DAEs of the oscillator without knowing any information about the input b(t). Put in other wors, it is a property intrinsic to the oscillator that captures its phase response to small external inputs. PPV can be use to moel an preict injection locking effectively [11]. Base on it people have evelope a simplifie approximation of (3) known as the Generalize Aler s Equation (GAE) [4]. It governs theynamicsoftheoscillator sphasewithspecificperioicinputs b(t) an its equilibrium states provie goo approximations to injectionlocke solutions of (3). GAE has the following form: φ(t) = (f 1 f 0)+f 0 g( φ(t)) (4) t where φ(t) = f 0t+f 0α(t) f 1t is phase ifference between the oscillator an the perturbation signal; f 1 is the funamental frequency of perioic input b(t) an f 1 f 0; function g is erive from (3) an can be evaluate numerically base on the formulation in [4].

3 When injection locking happens, the phase ifference φ(t) between oscillator an injecte signal becomes constant, i.e. f 1 f 0 f 0 = g( φ ) (5) By plotting the LHS an RHS of (5) an looking for intersections, esigners can preict whether IL or SHIL will happen given a esign [1] without running long an expensive transient simulations. 4. DESIGN TOOLS FOR OSCILLATOR-BASED COMPUT- ING SYSTEMS As an overview, Fig. 2 illustrates the mechanisms an usage of our esign tools. All the operations shown in Fig. 2 are automatically performe to guie the esign of oscillator latches an the full PHL- OGON system. Figure 3: Diagram of a 3-stage ring oscillator. Figure 4: PSS reponse of the free-running ring oscillator. Figure 2: Overview of the mechanism of the esign tools. The key of the operation of the esign tools is to transform the oscillator moels to phase omain. Using phase macromoels, instea of simulating oscillating voltages an currents in the system, we can irectly calculate the responses of phases. In the rest of the section, we follow the esign proceures of a ring oscillator phase logic FSM example, an show how the simulation an visualization provie by the esign tools can be helpful in every stage in the esign. 4.1 Simulation of Bit Storage in Oscillator Latches As escribe in Section 1, bit storage in an oscillator latch is achieve through Sub-harmonic Injection Locking (SHIL). But what are the conitions for SHIL to happen? How the ajustments on circuit structures affect SHIL s locking range? An when SHIL happens, how to preict the exact phase values of the locke states such that they can be use as references in phase-base logic encoing? These questions are har to answer by trial-an-error approaches with only the traitional SPICE-level transient simulation tools. In comparison, our esign tools can automatically extract the ring oscillator s PPV macromoel as in (3), perform Generalize Alerization an erive the oscillator s GAE equilibrium formula shown in (5). By plotting the LHS an RHS of (5), the solution of it, preicting the occurrence of SHIL, can be easily visualize. As illustration, we apply our tools on a ring oscillator example shown in Fig. 3 an show how they can be use to answer these questions from esigners. To store a phase-base binary bit, we perturb the ring oscillator with an external current source SYNC with I SYNC = A cos(2π 2f 1 t), where f 1 is close to its natural frequency f 0. In this oscillator, we choose C to be 4.7nF an assume that each CMOS inverter consists of 1 ALD1106 NMOS an 1 ALD1107 PMOS for the convenience of breaboar prototyping later on. In Fig. 5 we show the plot of the LHS an RHS of (5) at f 1 = 9.6kHz with various magnitues A of SYNC prouce by our esign tools on this oscillator. From Fig. 5 we can see that when A is larger than 70µA, there are four intersections of LHS an RHS, two of them representing stable DC solutions of (4) ([4]). Although Fig. 5 provies a goo visualization of the existence an stability of the solutions of (5), it is not necessary to plot LHS an RHS across the entire range of φ in orer to preict the occurrence of SHIL numerically. Instea, after formulating GAE in our esign tools, DC operating point solving will be attempte with ifferent initial guesses. If no solution is foun, the locking conition in (5) is not satisfie with any φ an SHIL won t happen; if a solution φ is foun, the erivative of g( φ ) is calculate. Base on Lyapunov s Figure 5: Graphical solutions of (5) in the ring oscillators with sinusoial SYNC of various magnitues. Stability Theorem [12] in the scalar case, if the erivative is negative, the solution is stable an SHIL will happen. Such operation points can be calculate in a DC sweep on parameters A an f 1 to give esigners a more comprehensive iea of the locking range. Consiering that GAE is a scalar ODE, this metho is robust an efficient. Figure 6: PPVs extracte by the e-figursign tools from ring oscillator latches by the esign tools on ring oscillator 7: Locking range returne with 2N1P an 1N1P inverters. latches with 2N1P an 1N1P inverters. Applying this DC-sweep-base metho on the GAE of the ring oscillator, the locking range for SHIL can be visualize as in Fig. 7. As a comparison, we perform the same analysis on another ring oscillator esign with inverters mae of 2 NMOS evices an 1 PMOS (2N1P). We overlay their PPVs an locking ranges in Fig. 6 an Fig. 7. The comparison reveals that after asymmetrizing the inverters (changing to 2N1P), the secon harmonic component of the PPV becomes larger, resulting in a larger locking range for SHIL. Such insight in esign is ifficult to get without facilities mae available by our tools base on PPV/GAE macromoels. Apart from the locking range, in orer to use the bi-stable phases to encoe logic bits in an oscillator latch, esigners also nee to know the exact phase value of the oscillator s response uner SHIL, i.e., where the peak of the oscillatory signal lies within a cycle. To analyze this property, we first normalize the time axis in the oscillator latch s T 0-perioic PSS response x s(t) an efine a 1-perioic function: x s(1) (t) = x s(t 0t) (6) Assume that the peak of the output V(n 1) is at position φ peak in this 1-perioic function, e.g., φ peak 0.21 in Fig. 4. Then a cos function shifte by φ peak V peak (t) = cos(2π (t φ peak )) (7) will have peaks aligne with those in the 1-perioic PSS x s(1) (t). When SHIL happens in the latch, assume the two stable solutions of the GAE in equilibrium (5) are φ 0 an φ 1, separate by 0.5. To

4 represent 1 an 0 in phase-encoing, we efine reference signals: V REF(t) = V 2 + V 2 cos(2π(f1t φ peak φ 0)) (8) V REF (t) = V 2 + V 2 cos(2π(f1t φ peak φ 1)) (9) such that when SHIL happens in the latch, the peaks of the output V(n 1) will be bi-stably aligne with those of either V REF or V REF, representing either phase-base 1 or 0. Ieally, esigners woul like to operate the latch with f 1 = f 0 such that the locking range is maximize (Fig. 7). However, when etuning happens, i.e., f 1 f 0, even though the latch may still stay in lock with a large enough SYNC, its locking phases ˆφ i may eviate from references φ i, an their quality as logic bits may egenerate. For this esign spec, our tools offer a goo visualization by calculating the DC solutions of GAE an plotting the magnitues of locking phase errors ˆφ i φ i across the locking range. is implemente with ALD1106 NMOS at the output stage with typical output impeance of 10MΩ. Uner these conitions, what s an appropriate value for A D such that the logic bit in the latch can be flippe by I D when EN=1, but retains its value when EN=0? To answer this question, esigners can again ask our tools to visualize the solutions of GAE, but this time with both SYNC an D as inputs. For example, Fig. 10 plots the LHS an RHS of GAE equilibrium equation (5) with EN=1, SYNC=100µA an various A D values. From it, we observe that when A D is larger than approximately 50µA, one of the stable phase states in SHIL vanishes an the output s phase is controlle by input D only. Figure 8: Locking phases errors ˆφ i φ i within the locking range. 0 means the signal uner injection locking has the same phase as the reference. The same proceures that calculate an plot GAE s DC solutions can beapplietoanyoscillatorfortheanalysisofbitstorageinphaselogic latches. With their help, esigners are able to gain comprehensive knowlege on the locking range, locking phases as well as the effects of circuit structure an parameters on them. 4.2 Simulation of Bit Flip in Oscillator Latches After attaching SYNC to the latch an efining phase-logic references base on its SHIL properties, esigners then attach logic inputs to the latch to control the bit store in it. But where to attach these inputs? An given a certain topology, what are the appropriate input magnitues? Similar to the bit storage scenario, the visualization of GAE solutions in our tools can be useful in etermining these esign specs. Figure 9: Diagram of a ring-oscillator D latch with phase-base D an levelbase EN. As an example, Fig. 9 shows the iagram of a simple D latch where EN is a level-base logic input that controls the on or off state of a switch, D input is an oscillatory current source with a certain output impeance: I D(t) = A Dcos(2π(f 1t φ peak φ i)),i = 0,1 (10) such that when EN = 1, i = 0, it enforces V(n 1) to be aligne with V REF; when EN = 1, i = 1, it enforces V(n 1) to be aligne with V REF ; when EN = 0, no matter what I D s phase is, V(n 1) shoul hol on to its original logic value. In this way, it achieves the functionality of a D latch. Assume that the switch is implemente using a transmission gate mae of ALD1106/7 long-channel MOSFET evices with a typical on-resistance of 1kΩ an off-resistance of 100GΩ. The current source Figure 10: Graphical solutions of (5) in the D latch with 100µA SYNC an various magnitues of D signals when EN=1. As D increases, one stable solution vanishes. Similar to the calculation of locke phases in bit storage scenario, instea of visualizing LHS an RHS at each input value, the esign tools can sweep the magnitue of D an return all stable solutions of (5) that preict the stable phases uner lock. Fig. 11 shows all these locke phase solutions preicte by the tools with various magnitues of D when EN=0 an 1. From it, esigners are able to get a comprehensive iea on how the choice of parameter A D can affect the logic operation of the latch. Figure 11: GAE equilibrium solutions with ifferent D magnitues when EN=1 an EN=0. Furthermore, after ajusting parameters to make the circuit behave as a D latch uner steay state, esigner also have to meet certain timing specifications, i.e., they have to make sure that the phase can flip to these esire steay states quickly enough. To simulate this bit flipping behaviour efficiently, our esign tools can irectly run transient simulation on the latch s GAE macromoel in (4) an the waveform of φ(t) transiting from φ 0 to φ 1 offers irect phaseomain visualization of the latch s timing properties. We use the D latch example in Fig. 9 again as illustration. Base on just the GAE DC solutions shown in Fig. 11, any D signal with a magnitue larger than 50µA seems suitable in the esign. However, results from transient simulations on the GAE (in Fig. 12) reveal more valuable information. They not only confirm that 30µA is not sufficient for the latch s response to catch up with D for logic operation, but also preict that even though 50µA D signal will flip the phase eventually, the bit flipping spee is probably not esirable. It is much slower than the flipping with 100µA, an the ifference in timing is much larger than that between 100µA an 150µA. It is worth mentioning that transient simulations run on a scalar phase omain ifferential equation as in (4) are much more efficient than those run irectly on the DAEs of oscillators. Their results are also more straightforwar in visualizing the latch s operation. With such

5 facility mae available by our esign tools, esigners can then ajust their phase-base latch esign accoringly to meet timing specs neee for logic computation. Figure 16: Transient simulation of the serial aer in Fig. 15 with oscillator latches replace by their PPV macromoels. φ = 0.5 inicates opposite phase w.r.t. REF, thus encoing phase-base 0, while φ = 1 encoes 1. Figure 12: Transient simulations on GAE preict the bit flipping timing behaviours. While Fig. 9 emonstrates a D latch with level-base EN, with the help of the esign tools, more complicate oscillator latches with logic inputs completely encoe in phases can be esigne. Fig. 13 shows our esign of an SR latch an a D latch. Although their logic operations (truth tables in Fig. 13) are straightforwar to unerstan from their structures, their practical implementations rely heavily on the esign tools. Figure 13: Diagrams of completely phase-base SR an D latches. One esign consieration in such an SR latch is that the latch shoul tolerate certain amount of mismatch between S an R. More specifically, when S an R have opposite phases but slightly ifferent magnitues, the logic value in the latch shoul still hol. Put in other wors, the resiue after cancelling opposite S an R shouln t flip the bit store in the latch. Similar to the example in Fig. 11, we use the esign tools to sweep the magnitues of S an R an plot all the stable solutions of (5) in Fig. 14. From it we conclue that a conventional majority gate that as its inputs with equal weights w 1 = w 2 = w 3 = 1 (black line in Fig. 14) is not suitable for SR latch esigns like Fig. 13. As an improvement, changing the weights of the majority gate to w 1 = w 2 = 0.01,w 3 = 1 (re lines) will make the latch tolerant more mismatch between S an R while still securely flip to esire logic state when S an R have the same phase with the magnitue of V/2 = 1.5V. Figure 14: GAE equilibrium solutions of an SR latch as in Fig. 13. The left an right subfigures plot solutions with ifferent magnitues of S an R signals, encoing the same an opposite phase logic values respectively. 4.3 Full System Transient Simulation with Phase Macromoels With oscillator latches an logic gates, phase-base general-purpose computing can be implemente by assembling them into FSMs. In the operation of a phase logic FSM, when the logic values of inputs change over time, i.e., their phase ifferences with respect to the reference signal shift back an forth between 0 an 180, esigners nee to know whether the system is inee performing computation properly with phase-base logic. For this purpose, traitional transient simulation can be performe on the DAE of the full system: t q full( x full )+ f full ( x full )+ b full (t) = 0 (11) However, if we separate system unknowns x full into x osci an x other, where x osci,i = 1,2,,k represents unknowns insie each of the k oscillator latches, we know x osci can be approximate well with its steay state response x osci (s) an its phase α i as in (2). As α i is unboune in simulation, similar to the formulation of GAE, we use the locking phase error φ i = f 0t+f 0α i(t) f 1t instea, such that x osci (t) = x osci (s)((f 1t+ φ i(t))/f 0) (12) where φ i is governe by t φi(t) = f0 f1 +f0 vt i (T 1 φ i(t)+t) b i(t) (13) where external b i(t) can be calculate from x other base on circuit connections. The formulation in (13) is slightly ifferent from the GAE in (4) in that the fast varying moe is preserve instea of average out [4]. In this way, the full system can be formulate as t q ( x other, φ)+ f ( x other, φ)+ b(t) = 0 (14) where φ represents all φ is. For each oscillator latch, all its voltage an current unknowns are now represente by only one scalar. Therefore, the system size is reuce. Instea of formulating(14) analytically, our esign tools allow users to ientify subcircuits that escribe oscillator latches an replace them with their PPV macromoels as in (13). Since the PPV of the latch has alreay been calculate in previous stages of esign, little computation is introuce in reformulating the full system into (14). Such reformulation with PPV macromoels results in an equation system not only with less unknowns, but also with unknowns that are more irectly relate to the phase operation of the system. As illustration, in Fig. 15 we show a simple FSM with 1-bit state: a serial aer with inputs a, b an CLK all encoe in phase logic. The D latches in Fig. 15 are the same as in Fig. 13 an their PPV macromoels have alreay been constructe in the previous stage of esign in Section 4.2. Our esign tools then use the macromoels to replace the latches an run transient simulation on the resulting system. From the transient results in Fig. 16, we observe the Figure 15: Serial aer. phase transition of the two latches ( φ of Q1 an Q2) when aing a=b=101 sequentially, in particular how Q2 follows Q1 s phase in the master-slave flip-flop. 5. EXPERIMENTS AND VALIDATION The esign an simulation of oscillator latches as well as the FSM mae from them have alreay emonstrate the mechanisms an capabilities of our esign tools in every stage of the implementation of oscillator-base computing systems. In this section, using stanar transient simulation an breaboar circuit experiments, we further valiate that the system esigne with our tools can behave as pre-

6 icte. 5.1 Bit Flip Transient Simulation Firstly, we simulate the transient behaviour of a phase-base logic bit switching states in the oscillator latch as in Fig. 9. As iscusse in Section 4.2, our esign tools can efficiently preict this key feature of a given oscillator latch. As an experiment, we run SPICE-level transient simulation with the same magnitue of SYNC (100µA) as chosen in Section 4.2 an flip D signal s phase (with magnitue 150µA) when EN=1. To stuy the phase transition of the latch, we plot the output of the latch in Fig. 17. We also measure its zero crossings 2, calculate their ifferences between those of the reference signal, an plot the ifferences also in Fig. 17. Then we overlay the preictions by GAE from our esign tools (black curve) to compare against the phase transition represente by zero crossings. From the comparison, we observe that even though they on t exactly overlap ue to ifferent efinitions of phase, they show similar results in the amount of time neee for the latch to settle at the new phase state, verifying the capability of the esign tools in efficiently analyzing the timing of oscillator latches. Figure 19: Test results of the master-slave D flip-flop as shown in the green block of Fig. 18. The blue, green, yellow signals represent REF, Q1, Q2 respectively. As CLK shifts between logic 1 an 0, Q1 (green) always follows input D at falling eges of CLK, while Q2 (yellow) follows Q1 at rising eges of CLK. This valiates the simulation results shown in Fig. 16. Figure 20: Selecte test results of the serial aer as in Fig. 18. REF, sum, cout are isplaye in blue, green, yellow respectively. With the same inputs: a=0 an b=1, the left subfigure shows sum=1, cout=0 when the state machine is at carry=0 state; the right one shows sum=0, cout=1 when the state machine is at carry=1 state. Figure 17: SPICE-level transient simulation results of bit flipping in D latch shown in Fig. 9: waveforms (top subfigure) an zero crossing ifferences between V(out) an V(ref) compare with preiction from GAE in Fig. 12 (bottom subfigure). 5.2 Breaboar Experiments Valiating FSM s Operation With the help of the esign tools, we have followe the esign proceures of a phase-base FSM in Section 4. It s logic operation as a serial aer has been preicte to be vali base on full system simulations with PPV macromoels. To emonstrate that such a computing system preicte to be working in our esign tools will also work in reality, we buil an FSM as in Fig. 15 on breaboars (Fig. 18). In the actual implementation, the majority an not gates are implemente with op-amps with resistive feebacks. Figure 18: Breaboar implementation of the serial aer in Fig. 15. The green blocks highlight the flip-flop mae from two D latches; the yellow block is the combinational logic block that has the functionality of a full aer. Fig. 19 an Fig. 20 show snapshots of test results seen from an oscilloscope. With thorough testing with various input combinations an sequences, we conclue that the circuit in Fig. 18 implements a phasebase serial aer. It is worth mentioning that to our knowlege, this is the first phase-base state machine mae with DC-powere oscillators, an a lot more trial an error woul have been require without the help of the esign tools escribe in this paper. 2 With single-ene power supply we consier crossings with the offset V/2 on the rising slopes as zero crossings. 6. CONCLUSIONS In this paper we introuce esign tools base on PPV an GAE macromoels of oscillators for implementing oscillator-base computing systems. Following the esign proceures of an example phasebase FSM, we emonstrate the usage an capabilities of the tools in all the stages of esign, from preicting an oscillator latch s bit storage an flipping properties to the efficient simulation of the full FSM system. With the help of the esign tools we were able to implement a phase-base state machine on breaboars. We plan to release the esign tools as open-source software to facilitate the esigners in the exploration of oscillator-base general-purpose computing. 7. REFERENCES [1] A. Neogy an J. Roychowhury. Analysis an Design of Sub-harmonically Injection Locke Oscillators. In Proc. IEEE DATE, Mar [2] H. Arsenault. Optical processing an computing. Elsevier, [3] B. Behin-Aein, D. Datta, S. Salahuin, an S. Datta. Proposal for an all-spin logic evice with built-in memory. Nature nanotechnology, 5(4): , [4] P. Bhansali an J. Roychowhury. Gen-Aler: The generalize Aler s equation for injection locking analysis in oscillators. In Proc. IEEE ASP-DAC, pages , January [5] P. Bhansali an J. Roychowhury. Injection locking analysis an simulation ofâăweakly couple oscillator networks. In P. Li, L. M. Silveira, an P. Felmann, eitors, Simulation an Verification of Electronic an Biological Systems, pages Springer Netherlans, [6] A. Demir, A. Mehrotra, an J. Roychowhury. Phase Noise in Oscillators: a Unifying Theory an Numerical Methos for Characterization. IEEE Trans. Ckts. Syst. I: Fun. Th. Appl., 47: , May [7] A. Demir an J. Roychowhury. A Reliable an Efficient Proceure for Oscillator PPV Computation, with Phase Noise Macromoelling Applications. IEEE Trans. on Computer-Aie Design, pages , February [8] H. Esmaeilzaeh, E. Blem, R. St. Amant, K. Sankaralingam, an D. Burger. Dark silicon an the en of multicore scaling. SIGARCH Comput. Archit. News, 39(3): , June [9] E. Goto. New Parametron circuit element using nonlinear reactance. KDD Kenyku Shiryo, October [10] D. Hisamoto, W.-C. Lee, J. Kezierski, H. Takeuchi, K. Asano, C. Kuo, E. Anerson, T.-J. King, J. Bokor, an C. Hu. Finfet-a self-aligne ouble-gate mosfet scalable to 20 nm. Electron Devices, IEEE Transactions on, 47(12): , [11] X. Lai an J. Roychowhury. Capturing injection locking via nonlinear phase omain macromoels. IEEE Trans. Microwave Theory Tech., 52(9): , September [12] A. M. Lyapunov. The general problem of the stability of motion. International Journal of Control, 55(3): , [13] G. E. Moore et al. Cramming more components onto integrate circuits, [14] K. S. Novoselov, V. Fal, L. Colombo, P. Gellert, M. Schwab, K. Kim, et al. A roamap for graphene. Nature, 490(7419): , [15] J. Roychowhury. Boolean Computation Using Self-Sustaining Nonlinear Oscillators. arxiv: v1 [cs.et], Oct arxiv: v1http://arxiv.org/abs/ v1/. [16] M. M. Shulaker, G. Hills, N. Patil, H. Wei, H.-Y. Chen, H.-S. P. Wong, an S. Mitra. Carbon nanotube computer. Nature, 501(7468): , [17] T. Mei an J. Roychowhury. PPV-HB: Harmonic Balance for Oscillator/PLL Phase Macromoels. In Proc. ICCAD, pages , Nov [18] T. Wang an J. Roychowhury. PHLOGON: PHase-base LOGic using Oscillatory Nanosystems. In Proc. Unconventional Computation an Natural Computation: 13th International Conference, UCNC 2014, Lonon, ON, Canaa, July 14-18, 2014, LNCS sublibrary: Theoretical computer science an general issues. Springer, [19] J. von Neumann. Non-linear capacitance or inuctance switching, amplifying an memory evices [20] Z. Wang, X. Lai, an J. Roychowhury. PV-PPV: Parameter Variability Aware, Automatically Extracte, Nonlinear Time-Shifte Oscillator Macromoels. In Proc. IEEE DAC, San Diego, CA, June [21] R. L. Wigington. A New Concept in Computing. Proceeings of the Institute of Raio Engineers, 47: , April [22] L. Wilson. International technology roamap for semiconuctors (itrs) [23] X. Lai an J. Roychowhury. TP-PPV: Piecewise Nonlinear, Time-Shifte Oscillator Macromoel Extraction For Fast, Accurate PLL Simulation. In Proc. ICCAD, pages , November 2006.