Pwning ARM Debug Components for Sec-Related Stuff (HardBlare project)
|
|
- Ernest Jacobs
- 5 years ago
- Views:
Transcription
1 Pwning ARM Debug Components for Sec-Related Stuff (HardBlare project) HITB COMMSEC Muhammad Abdul WAHAB, Pascal COTRET April 14, 2017 CentraleSupélec
2 Who am I? 2 nd year PhD Student at CentraleSuplec muhammadabdul.wahab@centralesupelec.fr HardBlare project 1 funded by CominLabs and Brittany region 1 0
3 Outline
4 Outline Motivation ARM CoreSight components Software Security Conclusion 1
5 Motivation
6 Software Security SoC = Hardcore CPU + FPGA (+ Peripherals) Figure 1: Zynq SoC Source: Xilinx 2
7 Software Security SoC = Hardcore CPU + FPGA (+ Peripherals) Figure 1: Zynq SoC Source: Xilinx 2
8 Dynamic Information Flow Tracking (DIFT) Information flow Information flow is the transfer of information from an information container c 1 to c 2 in a given process P. c 1 P c 2 3
9 Dynamic Information Flow Tracking (DIFT) Information flow Information flow is the transfer of information from an information container c 1 to c 2 in a given process P. c 1 P c 2 Example int a, b, w, x; a = 11; b = 5; w = a * 2; x = b + 1; 3
10 DIFT: Dynamic Information Flow Tracking Principle We attach labels called tags to such containers and specify an information flow policy, i.e. relations between tags At runtime, we propagate tags to reflect information flows that occur and detect any policy violation 4
11 DIFT: Dynamic Information Flow Tracking Principle We attach labels called tags to such containers and specify an information flow policy, i.e. relations between tags At runtime, we propagate tags to reflect information flows that occur and detect any policy violation 4
12 DIFT Example: Memory corruption Attacker overwrites return address and takes control int idx = tainted_input; //stdin (> BUFFER SIZE) buffer[idx] = x; // buffer overflow set r1 &tainted input load r2 M[r1] add r4 r2 + r3 store M[r4] r5 T Data r1:&input r2:idx=input T Data Return Address r3:&buffer r4:&buffer+idx int buffer[size] r5:x 5
13 DIFT Example: Memory corruption Attacker overwrites return address and takes control int idx = tainted_input; //stdin (> BUFFER SIZE) buffer[idx] = x; // buffer overflow set r1 &tainted input load r2 M[r1] add r4 r2 + r3 store M[r4] r5 T Data r1:&input r2:idx=input T Data Return Address r3:&buffer r4:&buffer+idx int buffer[size] r5:x 5
14 DIFT Example: Memory corruption Attacker overwrites return address and takes control int idx = tainted_input; //stdin (> BUFFER SIZE) buffer[idx] = x; // buffer overflow set r1 &tainted input load r2 M[r1] add r4 r2 + r3 store M[r4] r5 T Data r1:&input r2:idx=input T Data Return Address r3:&buffer r4:&buffer+idx int buffer[size] r5:x 5
15 DIFT Example: Memory corruption Attacker overwrites return address and takes control int idx = tainted_input; //stdin (> BUFFER SIZE) buffer[idx] = x; // buffer overflow set r1 &tainted input load r2 M[r1] add r4 r2 + r3 store M[r4] r5 T Data r1:&input r2:idx=input T Data Return Address r3:&buffer r4:&buffer+idx int buffer[size] r5:x 5
16 DIFT Example: Memory corruption Attacker overwrites return address and takes control int idx = tainted_input; //stdin (> BUFFER SIZE) buffer[idx] = x; // buffer overflow set r1 &tainted input load r2 M[r1] add r4 r2 + r3 store M[r4] r5 T Data r1:&input r2:idx=input T Data Return Address r3:&buffer r4:&buffer+idx int buffer[size] r5:x 5
17 DIFT: Dynamic Information Flow Tracking DIFT principle 1. DIFT taints data from untrusted sources Extra tag bit per word marks if untrusted 2. Propagate taint during program execution Operations with tainted data produce tainted results 3. Check for unsafe uses of tainted data 6
18 DIFT: Dynamic Information Flow Tracking DIFT principle 1. DIFT taints data from untrusted sources Extra tag bit per word marks if untrusted 2. Propagate taint during program execution Operations with tainted data produce tainted results 3. Check for unsafe uses of tainted data Motivation Protection from low-level and high-level threats Program understanding Software testing and debugging 6
19 DIFT - overview Constraints Zedboard : Zynq SoC ARM Cortex-A9 dual core CPU Programmable Logic Linux OS Main Goal: DIFT implementation How to recover information about each CPU instruction? 7
20 ARM CoreSight components
21 Coresight components A set of IP blocks providing HW-assisted system tracing Figure 2: ARM Coresight components in Zynq SoC 8
22 Coresight components A set of IP blocks providing HW-assisted system tracing Figure 2: ARM Coresight components in Zynq SoC Source: ARM CoreSight components TRM 8
23 Coresight components Features Trace Filter (all code or regions of code) ELF Header Program header table Section 1 Section Section n Section header table 9
24 Coresight components Features Trace Filter (all code or regions of code) Branch Broadcast (i) MOV PC, LR (ii) ADD R1, R2, R3 (iii) B 0x8084 9
25 Coresight components Features Trace Filter (all code or regions of code) Branch Broadcast Context ID comparator CycleAccurate tracing Timestamping (i) MOV PC, LR (ii) ADD R1, R2, R3 (iii) B 0x8084 9
26 Trace generation Address Instruction Trace, if any, with explanation 0x1000 MOV - 0x1004 ADD - 0x1008 B 0x1100 Direct branch taken. E atom generated. 10
27 Trace generation Address Instruction Trace, if any, with explanation 0x1000 MOV - 0x1004 ADD - 0x1008 B 0x1100 Direct branch taken. E atom generated. 0x1104 LDR - 0x110C CMP - 0x1110 BNE 0x1104 Direct branch taken. E atom generated. 10
28 Trace generation Address Instruction Trace, if any, with explanation 0x1000 MOV - 0x1004 ADD - 0x1008 B 0x1100 Direct branch taken. E atom generated. 0x1104 LDR - 0x110C CMP - 0x1110 BNE 0x1104 Direct branch taken. E atom generated. 0x1104 LDR - 0x1108 ADD - 0x110C CMP - 0x1110 BNE 0x1444 Direct branch not taken. N atom generated. 10
29 Configuration of CoreSight components Fun fact: Unlocking CoreSight components Write 0xC5ACCE55 to Lock Access Register LeetSpeak of CSACCESS (CoreSight Access)! 11
30 Configuration of CoreSight components 1 echo 0 > / s y s / d e v i c e s / system / cpu / cpu1 / o n l i n e 2 cd / s y s / bus / c o r e s i g h t / d e v i c e s / f889c000. ptm0/ 3 # C o n f i g u r e PTM components 4 echo 20 > mode 5 echo 1 > a d d r i d x 6 echo 0 > a d d r a c c t y p e 7 echo 0 > a d d r i d x 8 echo 0 > a d d r a c c t y p e 9 echo > a d d r r a n g e 10 # Enable Sink (ETB or TPIU ) 11 echo 1 > f t p i u / e n a b l e s i n k 12 #echo 1 > f etb / e n a b l e s i n k 13 # Enable Source 14 echo 1 > f889c000. ptm0/ e n a b l e s o u r c e 15 # Launch Program 16. / a p p l i c a t i o n. e l f 17 # Recover t r a c e 18. / r e c o v e r t r a c e f p g a. e l f 19 #dd i f =/dev / f etb o f=t r a c e. b i n 11
31 Configuration of CoreSight components 1 echo 0 > / s y s / d e v i c e s / system / cpu / cpu1 / o n l i n e 2 cd / s y s / bus / c o r e s i g h t / d e v i c e s / f889c000. ptm0/ 3 # C o n f i g u r e PTM components 4 echo 20 > mode 5 echo 1 > a d d r i d x 6 echo 0 > a d d r a c c t y p e 7 echo 0 > a d d r i d x 8 echo 0 > a d d r a c c t y p e 9 echo > a d d r r a n g e 10 # Enable Sink (ETB or TPIU ) 11 echo 1 > f t p i u / e n a b l e s i n k 12 #echo 1 > f etb / e n a b l e s i n k 13 # Enable Source 14 echo 1 > f889c000. ptm0/ e n a b l e s o u r c e 15 # Launch Program 16. / a p p l i c a t i o n. e l f 17 # Recover t r a c e 18. / r e c o v e r t r a c e f p g a. e l f 19 #dd i f =/dev / f etb o f=t r a c e. b i n 11
32 Configuration of CoreSight components 1 echo 0 > / s y s / d e v i c e s / system / cpu / cpu1 / o n l i n e 2 cd / s y s / bus / c o r e s i g h t / d e v i c e s / f889c000. ptm0/ 3 # C o n f i g u r e PTM components 4 echo 20 > mode 5 echo 1 > a d d r i d x 6 echo 0 > a d d r a c c t y p e 7 echo 0 > a d d r i d x 8 echo 0 > a d d r a c c t y p e 9 echo > a d d r r a n g e 10 # Enable Sink (ETB or TPIU ) 11 echo 1 > f t p i u / e n a b l e s i n k 12 #echo 1 > f etb / e n a b l e s i n k 13 # Enable Source 14 echo 1 > f889c000. ptm0/ e n a b l e s o u r c e 15 # Launch Program 16. / a p p l i c a t i o n. e l f 17 # Recover t r a c e 18. / r e c o v e r t r a c e f p g a. e l f 19 #dd i f =/dev / f etb o f=t r a c e. b i n 11
33 Configuration of CoreSight components 1 echo 0 > / s y s / d e v i c e s / system / cpu / cpu1 / o n l i n e 2 cd / s y s / bus / c o r e s i g h t / d e v i c e s / f889c000. ptm0/ 3 # C o n f i g u r e PTM components 4 echo 20 > mode 5 echo 1 > a d d r i d x 6 echo 0 > a d d r a c c t y p e 7 echo 0 > a d d r i d x 8 echo 0 > a d d r a c c t y p e 9 echo > a d d r r a n g e 10 # Enable Sink (ETB or TPIU ) 11 echo 1 > f t p i u / e n a b l e s i n k 12 #echo 1 > f etb / e n a b l e s i n k 13 # Enable Source 14 echo 1 > f889c000. ptm0/ e n a b l e s o u r c e 15 # Launch Program 16. / a p p l i c a t i o n. e l f 17 # Recover t r a c e 18. / r e c o v e r t r a c e f p g a. e l f 19 #dd i f =/dev / f etb o f=t r a c e. b i n 11
34 Configuration of CoreSight components 1 echo 0 > / s y s / d e v i c e s / system / cpu / cpu1 / o n l i n e 2 cd / s y s / bus / c o r e s i g h t / d e v i c e s / f889c000. ptm0/ 3 # C o n f i g u r e PTM components 4 echo 20 > mode 5 echo 1 > a d d r i d x 6 echo 0 > a d d r a c c t y p e 7 echo 0 > a d d r i d x 8 echo 0 > a d d r a c c t y p e 9 echo > a d d r r a n g e 10 # Enable Sink (ETB or TPIU ) 11 echo 1 > f t p i u / e n a b l e s i n k 12 #echo 1 > f etb / e n a b l e s i n k 13 # Enable Source 14 echo 1 > f889c000. ptm0/ e n a b l e s o u r c e 15 # Launch Program 16. / a p p l i c a t i o n. e l f 17 # Recover t r a c e 18. / r e c o v e r t r a c e f p g a. e l f 19 #dd i f =/dev / f etb o f=t r a c e. b i n 11
35 Example Trace Code Source 1 i n t i ; 2 f o r ( i = 0 ; i < 1 0 ; i ++) 12
36 Example Trace Code Source 1 i n t i ; 2 f o r ( i = 0 ; i < 1 0 ; i ++) Assembly 8638 for loop:... b 8654: c: bcc
37 Example Trace Code Source 1 i n t i ; 2 f o r ( i = 0 ; i < 1 0 ; i ++) Assembly 8638 for loop:... b 8654: c: bcc 8654 Trace a 2a 2a 2a 2a 2a 2a 2a 2a 2a
38 Example Trace Code Source 1 i n t i ; 2 f o r ( i = 0 ; i < 1 0 ; i ++) Assembly 8638 for loop:... b 8654: c: bcc 8654 Trace a 2a 2a 2a 2a 2a 2a 2a 2a 2a Decoded Trace A-sync Address , (I-sync Context , IB 21) Address , Branch Address packet (x 10) 12
39 Example Trace Decoded Trace A-sync Address , (I-sync Context , IB 21) Address , Branch Address packet (x 10) Figure 3: Control Flow Graph 13
40 CoreSight components - Performance overhead Average execution time (in µs) 2,000 1, , , ,339 2,340 1,057 1,053 1,160 1, choleski crc dft fir lu matrixnbody radix wht trace disabled trace enabled 14
41 CoreSight components - Summary Brief overview Trace.text section 15
42 CoreSight components - Summary Brief overview Trace.text section Recover all branch addresses 15
43 CoreSight components - Summary Brief overview Trace.text section Recover all branch addresses Reconstruct CFG of the application 15
44 CoreSight components - Summary Brief overview Trace.text section Recover all branch addresses Reconstruct CFG of the application PTM Non-intrusive 15
45 Software Security
46 DIFT How to recover information about each CPU instruction? CFG reconstruction on the FPGA 16
47 DIFT How to recover information about each CPU instruction? CFG reconstruction on the FPGA What happens inside each basic block? 16
48 DIFT How to recover information about each CPU instruction? CFG reconstruction on the FPGA What happens inside each basic block? Static code analysis Example Instructions sub r0, r1, r2 mov r3, r0 str r1, [PC, #4] Output of static analysis r0 = r1 + r2 r3 = = r1 16
49 Overall architecture Processing System (PS) EMIO interface Programmable Logic (PL) CoreSight Components PFT Decoder AXI BRAM ARM Cortex-A9 CPU 0 AXI GP Config interrupt DIFT Coprocessor TRF DDR Memory (used by Linux OS) Tag dependencies Tag space 64 MB 32 MB Heap and Stack (DIFT coproc.) 32 MB 17
50 DIFT example: Data Leakage Prevention (DLP) char buffer[20]; FILE *fs; if(geteuid()!= 0){ // user fs = fopen("welcome", "r"); //public if(!fs) exit (1); } else { // root fs = fopen("passwd", "r"); //secret if(!fs) exit(1); } fread(buffer, 1, sizeof(buffer), fs); fclose(fs); printf("buffer Value: %s \n", buffer); 18
51 DIFT example 1 root@zedboard h a r d b l a r e : c a t welcome 2 WELCOME 3 root@zedboard h a r d b l a r e : c a t passwd 4 MDP 5 root@zedboard h a r d b l a r e :. / u s e c a s e 6 B u f f e r Value : MDP 7 root@zedboard h a r d b l a r e : sudo u n o r m a l u s e r. / u s e c a s e 8 B u f f e r Value : WELCOME 19
52 DIFT example 1 root@zedboard h a r d b l a r e : c a t welcome 2 WELCOME 3 root@zedboard h a r d b l a r e : c a t passwd 4 MDP 5 root@zedboard h a r d b l a r e :. / u s e c a s e 6 B u f f e r Value : MDP 7 root@zedboard h a r d b l a r e : sudo u n o r m a l u s e r. / u s e c a s e 8 B u f f e r Value : WELCOME 19
53 DIFT example 1 root@zedboard h a r d b l a r e : c a t welcome 2 WELCOME 3 root@zedboard h a r d b l a r e : c a t passwd 4 MDP 5 root@zedboard h a r d b l a r e :. / u s e c a s e 6 B u f f e r Value : MDP 7 root@zedboard h a r d b l a r e : sudo u n o r m a l u s e r. / u s e c a s e 8 B u f f e r Value : WELCOME 19
54 DIFT example 1 root@zedboard h a r d b l a r e :. / r e c o v e r t r a c e 2 CPU1 : shutdown 3 c o r e s i g h t t p i u f t p i u : TPIU e n a b l e d 4 c o r e s i g h t r e p l i c a t o r : REPLICATOR e n a b l e d 5 c o r e s i g h t f u n n e l : FUNNEL i n p o r t 0 e n a b l e d 6 c o r e s i g h t etm3x f889c000. ptm : ETM t r a c i n g e n a b l e d 7 B u f f e r Value : MDP 8 c o r e s i g h t etm3x f889c000. ptm : ETM t r a c i n g d i s a b l e d 9 c o r e s i g h t f u n n e l : FUNNEL i n p o r t 0 d i s a b l e d 10 c o r e s i g h t r e p l i c a t o r : REPLICATOR d i s a b l e d 11 c o r e s i g h t t p i u f t p i u : TPIU d i s a b l e d 20
55 DIFT example 1 root@zedboard h a r d b l a r e :. / r e c o v e r t r a c e 2 CPU1 : shutdown 3 c o r e s i g h t t p i u f t p i u : TPIU e n a b l e d 4 c o r e s i g h t r e p l i c a t o r : REPLICATOR e n a b l e d 5 c o r e s i g h t f u n n e l : FUNNEL i n p o r t 0 e n a b l e d 6 c o r e s i g h t etm3x f889c000. ptm : ETM t r a c i n g e n a b l e d 7 B u f f e r Value : MDP 8 c o r e s i g h t etm3x f889c000. ptm : ETM t r a c i n g d i s a b l e d 9 c o r e s i g h t f u n n e l : FUNNEL i n p o r t 0 d i s a b l e d 10 c o r e s i g h t r e p l i c a t o r : REPLICATOR d i s a b l e d 11 c o r e s i g h t t p i u f t p i u : TPIU d i s a b l e d 20
56 DIFT example 1 root@zedboard h a r d b l a r e :. / r e c o v e r t r a c e 2 CPU1 : shutdown 3 c o r e s i g h t t p i u f t p i u : TPIU e n a b l e d 4 c o r e s i g h t r e p l i c a t o r : REPLICATOR e n a b l e d 5 c o r e s i g h t f u n n e l : FUNNEL i n p o r t 0 e n a b l e d 6 c o r e s i g h t etm3x f889c000. ptm : ETM t r a c i n g e n a b l e d 7 B u f f e r Value : MDP 8 c o r e s i g h t etm3x f889c000. ptm : ETM t r a c i n g d i s a b l e d 9 c o r e s i g h t f u n n e l : FUNNEL i n p o r t 0 d i s a b l e d 10 c o r e s i g h t r e p l i c a t o r : REPLICATOR d i s a b l e d 11 c o r e s i g h t t p i u f t p i u : TPIU d i s a b l e d 20
57 DIFT example 1 root@zedboard h a r d b l a r e :. / r e c o v e r t r a c e 2 CPU1 : shutdown 3 c o r e s i g h t t p i u f t p i u : TPIU e n a b l e d 4 c o r e s i g h t r e p l i c a t o r : REPLICATOR e n a b l e d 5 c o r e s i g h t f u n n e l : FUNNEL i n p o r t 0 e n a b l e d 6 c o r e s i g h t etm3x f889c000. ptm : ETM t r a c i n g e n a b l e d 7 B u f f e r Value : MDP 8 c o r e s i g h t etm3x f889c000. ptm : ETM t r a c i n g d i s a b l e d 9 c o r e s i g h t f u n n e l : FUNNEL i n p o r t 0 d i s a b l e d 10 c o r e s i g h t r e p l i c a t o r : REPLICATOR d i s a b l e d 11 c o r e s i g h t t p i u f t p i u : TPIU d i s a b l e d 20
58 DIFT example 1 root@zedboard h a r d b l a r e :. / r e c o v e r t r a c e 2 CPU1 : shutdown 3 c o r e s i g h t t p i u f t p i u : TPIU e n a b l e d 4 c o r e s i g h t r e p l i c a t o r : REPLICATOR e n a b l e d 5 c o r e s i g h t f u n n e l : FUNNEL i n p o r t 0 e n a b l e d 6 c o r e s i g h t etm3x f889c000. ptm : ETM t r a c i n g e n a b l e d 7 B u f f e r Value : MDP 8 c o r e s i g h t etm3x f889c000. ptm : ETM t r a c i n g d i s a b l e d 9 c o r e s i g h t f u n n e l : FUNNEL i n p o r t 0 d i s a b l e d 10 c o r e s i g h t r e p l i c a t o r : REPLICATOR d i s a b l e d 11 c o r e s i g h t t p i u f t p i u : TPIU d i s a b l e d 20
59 DIFT example 1 / dev /mem opened. 2 Memory mapped at a d d r e s s 0 x b 6 f f c c c a4 21
60 DIFT example Processing System (PS) EMIO interface Programmable Logic (PL) CoreSight Components PFT Decoder AXI BRAM ARM Cortex-A9 CPU 0 AXI GP Config interrupt DIFT Coprocessor TRF DDR Memory (used by Linux OS) Tag dependencies Tag space 64 MB 32 MB Heap and Stack (DIFT coproc.) 32 MB 22
61 DIFT example 1 root@zedboard h a r d b l a r e : 2 t r a c e = t r a c e = t r a c e = t r a c e = 1057 c 6 7 tag ( r0 ) = 0 8 tag ( r1 ) = 1 9 tag ( r2 ) = 0 10 tag ( r3 ) =
62 DIFT example 1 root@zedboard h a r d b l a r e : 2 t r a c e = t r a c e = t r a c e = t r a c e = 1057 c 6 7 tag ( r0 ) = 0 8 tag ( r1 ) = 1 9 tag ( r2 ) = 0 10 tag ( r3 ) =
63 DIFT example 1 root@zedboard h a r d b l a r e : 2 t r a c e = t r a c e = t r a c e = t r a c e = 1057 c 6 7 tag ( r0 ) = 0 8 tag ( r1 ) = 1 9 tag ( r2 ) = 0 10 tag ( r3 ) =
64 Preventing ROP attacks 2 On each function call, copy the return address into a special stack (called shadow stack) Obtained with decoded trace 2 Yongje Lee et al. Towards a Practical Solution to Detect Code Reuse Attacks on ARM Mobile Devices. In: HASP
65 Preventing ROP attacks 2 On each function call, copy the return address into a special stack (called shadow stack) On each function return, compare LR register value with one stored in shadow stack Obtained with decoded trace Dedicated component on FPGA 2 Yongje Lee et al. Towards a Practical Solution to Detect Code Reuse Attacks on ARM Mobile Devices. In: HASP
66 Software security - Summary Brief overview Dynamic Information Flow Tracking (DIFT) Overflows Data Leakage Prevention SQL injection 25
67 Software security - Summary Brief overview Dynamic Information Flow Tracking (DIFT) Overflows Data Leakage Prevention SQL injection Code Reuse Attacks ROP JOP 25
68 Conclusion
69 Conclusion Take away CoreSight PTM allows to obtain runtime information (Program Flow) Non-intrusive tracing Negligible performance overhead Improve software security 26
70 Conclusion Take away CoreSight PTM allows to obtain runtime information (Program Flow) Non-intrusive tracing Negligible performance overhead Improve software security Future perspectives Possible to take use of other debug components for security Intel Processor Trace STM (TI) 26
71 Acknowledgments Thanks to CominLabs 3 and Brittany Region Pascal COTRET Mounir NASR ALLAH My PhD supervisors
72 Thank you! Any questions? 27
73 Bibliography Secure Program Execution via DIFT, Suh et Al. RAKSHA, Dalton et Al. FlexiTaint, Venkataramani et Al. Off-core RAKSHA, Kannan et Al. FlexCore, Deng et Al. HARMONI, Deng et Al. PAU, Heo et Al
ELECTROMAGNETIC FAULT INJECTION: TOWARDS A FAULT MODEL ON A 32-BIT MICROCONTROLLER
ELECTROMAGNETIC FAULT INJECTION: TOWARDS A FAULT MODEL ON A 32-BIT MICROCONTROLLER Nicolas Moro 1,3, Amine Dehbaoui 2, Karine Heydemann 3, Bruno Robisson 1, Emmanuelle Encrenaz 3 1 CEA Commissariat à l
More informationAdministrivia. Course Objectives. Overview. Lecture Notes Week markem/cs333/ 2. Staff. 3. Prerequisites. 4. Grading. 1. Theory and application
Administrivia 1. markem/cs333/ 2. Staff 3. Prerequisites 4. Grading Course Objectives 1. Theory and application 2. Benefits 3. Labs TAs Overview 1. What is a computer system? CPU PC ALU System bus Memory
More informationCprE 281: Digital Logic
CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Simple Processor CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Digital
More informationNCU EE -- DSP VLSI Design. Tsung-Han Tsai 1
NCU EE -- DSP VLSI Design. Tsung-Han Tsai 1 Multi-processor vs. Multi-computer architecture µp vs. DSP RISC vs. DSP RISC Reduced-instruction-set Register-to-register operation Higher throughput by using
More informationSystem Data Bus (8-bit) Data Buffer. Internal Data Bus (8-bit) 8-bit register (R) 3-bit address 16-bit register pair (P) 2-bit address
Intel 8080 CPU block diagram 8 System Data Bus (8-bit) Data Buffer Registry Array B 8 C Internal Data Bus (8-bit) F D E H L ALU SP A PC Address Buffer 16 System Address Bus (16-bit) Internal register addressing:
More informationww.padasalai.net
t w w ADHITHYA TRB- TET COACHING CENTRE KANCHIPURAM SUNDER MATRIC SCHOOL - 9786851468 TEST - 2 COMPUTER SCIENC PG - TRB DATE : 17. 03. 2019 t et t et t t t t UNIT 1 COMPUTER SYSTEM ARCHITECTURE t t t t
More informationECE290 Fall 2012 Lecture 22. Dr. Zbigniew Kalbarczyk
ECE290 Fall 2012 Lecture 22 Dr. Zbigniew Kalbarczyk Today LC-3 Micro-sequencer (the control store) LC-3 Micro-programmed control memory LC-3 Micro-instruction format LC -3 Micro-sequencer (the circuitry)
More informationEffective Entropy for Memory Randomization Defenses
Effective Entropy for Memory Randomization Defenses William Herlands, Thomas Hobson, Paula Donovan 7 th Workshop on Cyber Security Experimentation and Test 18 August 2014 This work is sponsored by Assistant
More informationComputer Engineering Department. CC 311- Computer Architecture. Chapter 4. The Processor: Datapath and Control. Single Cycle
Computer Engineering Department CC 311- Computer Architecture Chapter 4 The Processor: Datapath and Control Single Cycle Introduction The 5 classic components of a computer Processor Input Control Memory
More informationCOMPUTER SCIENCE TRIPOS
CST.2016.2.1 COMPUTER SCIENCE TRIPOS Part IA Tuesday 31 May 2016 1.30 to 4.30 COMPUTER SCIENCE Paper 2 Answer one question from each of Sections A, B and C, and two questions from Section D. Submit the
More informationA Control Flow Integrity Based Trust Model. Ge Zhu Akhilesh Tyagi Iowa State University
A Control Flow Integrity Based Trust Model Ge Zhu Akhilesh Tyagi Iowa State University Trust Model Many definitions of trust. Typically transaction level trust propagation/policy. Self-assessment of trust.
More information2. Accelerated Computations
2. Accelerated Computations 2.1. Bent Function Enumeration by a Circular Pipeline Implemented on an FPGA Stuart W. Schneider Jon T. Butler 2.1.1. Background A naive approach to encoding a plaintext message
More informationWorst-Case Execution Time Analysis. LS 12, TU Dortmund
Worst-Case Execution Time Analysis Prof. Dr. Jian-Jia Chen LS 12, TU Dortmund 02, 03 May 2016 Prof. Dr. Jian-Jia Chen (LS 12, TU Dortmund) 1 / 53 Most Essential Assumptions for Real-Time Systems Upper
More informationOperating Systems. VII. Synchronization
Operating Systems VII. Synchronization Ludovic Apvrille ludovic.apvrille@telecom-paristech.fr Eurecom, office 470 http://soc.eurecom.fr/os/ @OS Eurecom Outline Synchronization issues 2/22 Fall 2017 Institut
More informationWorst-Case Execution Time Analysis. LS 12, TU Dortmund
Worst-Case Execution Time Analysis Prof. Dr. Jian-Jia Chen LS 12, TU Dortmund 09/10, Jan., 2018 Prof. Dr. Jian-Jia Chen (LS 12, TU Dortmund) 1 / 43 Most Essential Assumptions for Real-Time Systems Upper
More informationVector Lane Threading
Vector Lane Threading S. Rivoire, R. Schultz, T. Okuda, C. Kozyrakis Computer Systems Laboratory Stanford University Motivation Vector processors excel at data-level parallelism (DLP) What happens to program
More informationCyrus: Unintrusive Application-Level Record-Replay for Replay Parallelism
Cyrus: Unintrusive Application-Level Record-Replay for Replay Parallelism Nima Honarmand, Nathan Dautenhahn, Josep Torrellas and Samuel T. King (UIUC) Gilles Pokam and Cristiano Pereira (Intel) iacoma.cs.uiuc.edu
More informationComputer Architecture
Computer Architecture QtSpim, a Mips simulator S. Coudert and R. Pacalet January 4, 2018..................... Memory Mapping 0xFFFF000C 0xFFFF0008 0xFFFF0004 0xffff0000 0x90000000 0x80000000 0x7ffff4d4
More informationCMP 334: Seventh Class
CMP 334: Seventh Class Performance HW 5 solution Averages and weighted averages (review) Amdahl's law Ripple-carry adder circuits Binary addition Half-adder circuits Full-adder circuits Subtraction, negative
More informationCSCI-564 Advanced Computer Architecture
CSCI-564 Advanced Computer Architecture Lecture 8: Handling Exceptions and Interrupts / Superscalar Bo Wu Colorado School of Mines Branch Delay Slots (expose control hazard to software) Change the ISA
More informationECEN 449: Microprocessor System Design Department of Electrical and Computer Engineering Texas A&M University
ECEN 449: Microprocessor System Design Department of Electrical and Computer Engineering Texas A&M University Prof. Sunil P Khatri (Lab exercise created and tested by Ramu Endluri, He Zhou and Sunil P
More informationToday. ESE532: System-on-a-Chip Architecture. Energy. Message. Preclass Challenge: Power. Energy Today s bottleneck What drives Efficiency of
ESE532: System-on-a-Chip Architecture Day 20: November 8, 2017 Energy Today Energy Today s bottleneck What drives Efficiency of Processors, FPGAs, accelerators How does parallelism impact energy? 1 2 Message
More informationSpecial Nodes for Interface
fi fi Special Nodes for Interface SW on processors Chip-level HW Board-level HW fi fi C code VHDL VHDL code retargetable compilation high-level synthesis SW costs HW costs partitioning (solve ILP) cluster
More informationICS 233 Computer Architecture & Assembly Language
ICS 233 Computer Architecture & Assembly Language Assignment 6 Solution 1. Identify all of the RAW data dependencies in the following code. Which dependencies are data hazards that will be resolved by
More informationDigital Systems Design Overview. ENGIN 341 Advanced Digital Design University of Massachuse?s Boston Department of Engineering Dr.
Digital Systems Design Overview ENGIN 341 Advanced Digital Design University of Massachuse?s Boston Department of Engineering Dr. Filip Cuckov Overview 1. IntroducGon to Programmable Logic Devices 2. Field
More informationECEN 651: Microprogrammed Control of Digital Systems Department of Electrical and Computer Engineering Texas A&M University
ECEN 651: Microprogrammed Control of Digital Systems Department of Electrical and Computer Engineering Texas A&M University Prof. Mi Lu TA: Ehsan Rohani Laboratory Exercise #4 MIPS Assembly and Simulation
More informationRandom Delay Insertion: Effective Countermeasure against DPA on FPGAs
Random Delay Insertion: Effective Countermeasure against DPA on FPGAs Lu, Yingxi Dr. Máire O Neill Prof. John McCanny Overview September 2004 PRESENTATION OUTLINE DPA and countermeasures Random Delay Insertion
More informationDM74LS670 3-STATE 4-by-4 Register File
DM74LS670 3-STATE 4-by-4 Register File General Description August 1986 Revised March 2000 These register files are organized as 4 words of 4 bits each, and separate on-chip decoding is provided for addressing
More informationEvaluating Overheads of Multi-bit Soft Error Protection Techniques at Hardware Level Sponsored by SRC and Freescale under SRC task number 2042
Evaluating Overheads of Multi-bit Soft Error Protection Techniques at Hardware Level Sponsored by SR and Freescale under SR task number 2042 Lukasz G. Szafaryn, Kevin Skadron Department of omputer Science
More information74F240 74F241 74F244 Octal Buffers/Line Drivers with 3-STATE Outputs
74F240 74F241 74F244 Octal Buffers/Line Drivers with 3-STATE Outputs General Description The 74F240, 74F241 and 74F244 are octal buffers and line drivers designed to be employed as memory and address drivers,
More informationCMP 338: Third Class
CMP 338: Third Class HW 2 solution Conversion between bases The TINY processor Abstraction and separation of concerns Circuit design big picture Moore s law and chip fabrication cost Performance What does
More information74F Bit Random Access Memory with 3-STATE Outputs
April 1988 Revised July 1999 74F189 64-Bit Random Access Memory with 3-STATE Outputs General Description The F189 is a high-speed 64-bit RAM organized as a 16- word by 4-bit array. Address inputs are buffered
More informationFormal Fault Analysis of Branch Predictors: Attacking countermeasures of Asymmetric key ciphers
Formal Fault Analysis of Branch Predictors: Attacking countermeasures of Asymmetric key ciphers Sarani Bhattacharya and Debdeep Mukhopadhyay Indian Institute of Technology Kharagpur PROOFS 2016 August
More informationINF2270 Spring Philipp Häfliger. Lecture 8: Superscalar CPUs, Course Summary/Repetition (1/2)
INF2270 Spring 2010 Philipp Häfliger Summary/Repetition (1/2) content From Scalar to Superscalar Lecture Summary and Brief Repetition Binary numbers Boolean Algebra Combinational Logic Circuits Encoder/Decoder
More informationA Combined Analytical and Simulation-Based Model for Performance Evaluation of a Reconfigurable Instruction Set Processor
A Combined Analytical and Simulation-Based Model for Performance Evaluation of a Reconfigurable Instruction Set Processor Farhad Mehdipour, H. Noori, B. Javadi, H. Honda, K. Inoue, K. Murakami Faculty
More informationEECS 579: Logic and Fault Simulation. Simulation
EECS 579: Logic and Fault Simulation Simulation: Use of computer software models to verify correctness Fault Simulation: Use of simulation for fault analysis and ATPG Circuit description Input data for
More informationPower Consumption Analysis. Arithmetic Level Countermeasures for ECC Coprocessor. Arithmetic Operators for Cryptography.
Power Consumption Analysis General principle: measure the current I in the circuit Arithmetic Level Countermeasures for ECC Coprocessor Arnaud Tisserand, Thomas Chabrier, Danuta Pamula I V DD circuit traces
More informationCHAPTER log 2 64 = 6 lines/mux or decoder 9-2.* C = C 8 V = C 8 C * 9-4.* (Errata: Delete 1 after problem number) 9-5.
CHPTER 9 2008 Pearson Education, Inc. 9-. log 2 64 = 6 lines/mux or decoder 9-2.* C = C 8 V = C 8 C 7 Z = F 7 + F 6 + F 5 + F 4 + F 3 + F 2 + F + F 0 N = F 7 9-3.* = S + S = S + S S S S0 C in C 0 dder
More informationECE 3401 Lecture 23. Pipeline Design. State Table for 2-Cycle Instructions. Control Unit. ISA: Instruction Specifications (for reference)
ECE 3401 Lecture 23 Pipeline Design Control State Register Combinational Control Logic New/ Modified Control Word ISA: Instruction Specifications (for reference) P C P C + 1 I N F I R M [ P C ] E X 0 PC
More informationCSE370: Introduction to Digital Design
CSE370: Introduction to Digital Design Course staff Gaetano Borriello, Brian DeRenzi, Firat Kiyak Course web www.cs.washington.edu/370/ Make sure to subscribe to class mailing list (cse370@cs) Course text
More informationInformation Security Theory vs. Reality
Information Security Theory vs. Reality 0368-4474-01, Winter 2011 Lecture 7: Information flow control Eran Tromer 1 Slides credit: Max Krohn, MIT Ian Goldberg and Urs Hengartner, University of Waterloo
More informationPipelining. Traditional Execution. CS 365 Lecture 12 Prof. Yih Huang. add ld beq CS CS 365 2
Pipelining CS 365 Lecture 12 Prof. Yih Huang CS 365 1 Traditional Execution 1 2 3 4 1 2 3 4 5 1 2 3 add ld beq CS 365 2 1 Pipelined Execution 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5
More informationMark Redekopp, All rights reserved. Lecture 1 Slides. Intro Number Systems Logic Functions
Lecture Slides Intro Number Systems Logic Functions EE 0 in Context EE 0 EE 20L Logic Design Fundamentals Logic Design, CAD Tools, Lab tools, Project EE 357 EE 457 Computer Architecture Using the logic
More informationLaboratory Exercise #11 A Simple Digital Combination Lock
Laboratory Exercise #11 A Simple Digital Combination Lock ECEN 248: Introduction to Digital Design Department of Electrical and Computer Engineering Texas A&M University 2 Laboratory Exercise #11 1 Introduction
More informationA Simple Architectural Enhancement for Fast and Flexible Elliptic Curve Cryptography over Binary Finite Fields GF(2 m )
A Simple Architectural Enhancement for Fast and Flexible Elliptic Curve Cryptography over Binary Finite Fields GF(2 m ) Stefan Tillich, Johann Großschädl Institute for Applied Information Processing and
More informationI/O Devices. Device. Lecture Notes Week 8
I/O Devices CPU PC ALU System bus Memory bus Bus interface I/O bridge Main memory USB Graphics adapter I/O bus Disk other devices such as network adapters Mouse Keyboard Disk hello executable stored on
More informationAttack Graph Modeling and Generation
Attack Graph Modeling and Generation Ratnesh Kumar, Professor, IEEE Fellow Electrical and Computer Engineering, Iowa State University PhD Students: Mariam Ibrahim German Jordanian University Attack Graph:
More informationVäxjö University. Software Security Testing. A Flexible Architecture for Security Testing. School of Mathematics and System Engineering
School of Mathematics and System Engineering Reports from MSI - Rapporter från MSI Växjö University Software Security Testing A Flexible Architecture for Security Testing Martin Andersson Aug 2008 MSI
More informationEC 413 Computer Organization
EC 413 Computer Organization rithmetic Logic Unit (LU) and Register File Prof. Michel. Kinsy Computing: Computer Organization The DN of Modern Computing Computer CPU Memory System LU Register File Disks
More informationALU A functional unit
ALU A functional unit that performs arithmetic operations such as ADD, SUB, MPY logical operations such as AND, OR, XOR, NOT on given data types: 8-,16-,32-, or 64-bit values A n-1 A n-2... A 1 A 0 B n-1
More informationTracking board design for the SHAGARE stratospheric balloon project. Supervisor : René Beuchat Student : Joël Vallone
Tracking board design for the SHAGARE stratospheric balloon project Supervisor : René Beuchat Student : Joël Vallone Motivation Send & track a gamma-ray sensor in the stratosphere with a meteorological
More informationOHW2013 workshop. An open source PCIe device virtualization framework
OHW2013 workshop An open source PCIe device virtualization framework Plan Context and objectives Design and implementation Future directions Questions Context - ESRF and the ISDD electronic laboratory
More informationOn the Use of a Many core Processor for Computational Fluid Dynamics Simulations
On the Use of a Many core Processor for Computational Fluid Dynamics Simulations Sebastian Raase, Tomas Nordström Halmstad University, Sweden {sebastian.raase,tomas.nordstrom} @ hh.se Preface based on
More informationLecture 13: Sequential Circuits, FSM
Lecture 13: Sequential Circuits, FSM Today s topics: Sequential circuits Finite state machines 1 Clocks A microprocessor is composed of many different circuits that are operating simultaneously if each
More informationParallelization of the QC-lib Quantum Computer Simulator Library
Parallelization of the QC-lib Quantum Computer Simulator Library Ian Glendinning and Bernhard Ömer VCPC European Centre for Parallel Computing at Vienna Liechtensteinstraße 22, A-19 Vienna, Austria http://www.vcpc.univie.ac.at/qc/
More informationExploring the Potential of Instruction-Level Parallelism of Exposed Datapath Architectures with Buffered Processing Units
Exploring the Potential of Instruction-Level Parallelism of Exposed Datapath Architectures with Buffered Processing Units Anoop Bhagyanath and Klaus Schneider Embedded Systems Chair University of Kaiserslautern
More informationToday. ESE532: System-on-a-Chip Architecture. Energy. Message. Preclass Challenge: Power. Energy Today s bottleneck What drives Efficiency of
ESE532: System-on-a-Chip Architecture Day 22: April 10, 2017 Today Today s bottleneck What drives Efficiency of Processors, FPGAs, accelerators 1 2 Message dominates Including limiting performance Make
More informationMS BA01 Miniature Altimeter Module
High resolution module, 20 cm Fast conversion down to 0.5 ms Low power, 0.6 µa (standby < 0.15 µa at 25 C) Integrated digital pressure sensor (24 bit ΔΣ AC) Supply voltage 1.8 to 3.6 V Operating range:
More informationHoare Logic for Realistically Modelled Machine Code
Hoare Logic for Realistically Modelled Machine Code Magnus O. Myreen, Michael J. C. Gordon TACAS, March 2007 This talk Contribution: A mechanised Hoare logic for machine code with emphasis on resource
More informationBranch Prediction based attacks using Hardware performance Counters IIT Kharagpur
Branch Prediction based attacks using Hardware performance Counters IIT Kharagpur March 19, 2018 Modular Exponentiation Public key Cryptography March 19, 2018 Branch Prediction Attacks 2 / 54 Modular Exponentiation
More informationDISARMAMENT HACKING 2.0 TOWARD A TRUSTED, OPEN-HARDWARE COMPUTING PLATFORM FOR NUCLEAR WARHEAD VERIFICATION
DISARMAMENT HACKING 2.0 TOWARD A TRUSTED, OPEN-HARDWARE COMPUTING PLATFORM FOR NUCLEAR WARHEAD VERIFICATION Moritz Kütt, Malte Göttsche, and Alexander Glaser Princeton University 57th Annual INMM Meeting,
More informationCPSC 3300 Spring 2017 Exam 2
CPSC 3300 Spring 2017 Exam 2 Name: 1. Matching. Write the correct term from the list into each blank. (2 pts. each) structural hazard EPIC forwarding precise exception hardwired load-use data hazard VLIW
More informationTimeline of a Vulnerability
Introduction Timeline of a Vulnerability Is this all a conspiracy? Vulnerability existed for many years 2 Michael Schwarz (@misc0110) www.iaik.tugraz.at Timeline of a Vulnerability Is this all a conspiracy?
More informationEmbedded Systems 23 BF - ES
Embedded Systems 23-1 - Measurement vs. Analysis REVIEW Probability Best Case Execution Time Unsafe: Execution Time Measurement Worst Case Execution Time Upper bound Execution Time typically huge variations
More informationDMP. Deterministic Shared Memory Multiprocessing. Presenter: Wu, Weiyi Yale University
DMP Deterministic Shared Memory Multiprocessing 1 Presenter: Wu, Weiyi Yale University Outline What is determinism? How to make execution deterministic? What s the overhead of determinism? 2 What Is Determinism?
More informationAdministrative Stuff
EE141- Spring 2004 Digital Integrated Circuits Lecture 30 PERSPECTIVES 1 Administrative Stuff Homework 10 posted just for practice. No need to turn in (hw 9 due today). Normal office hours next week. HKN
More informationDirect Self-Consistent Field Computations on GPU Clusters
Direct Self-Consistent Field Computations on GPU Clusters Guochun Shi, Volodymyr Kindratenko National Center for Supercomputing Applications University of Illinois at UrbanaChampaign Ivan Ufimtsev, Todd
More informationECE 571 Advanced Microprocessor-Based Design Lecture 10
ECE 571 Advanced Microprocessor-Based Design Lecture 10 Vince Weaver http://web.eece.maine.edu/~vweaver vincent.weaver@maine.edu 23 February 2017 Announcements HW#5 due HW#6 will be posted 1 Oh No, More
More information74F Bit D-Type Flip-Flop
74F821 10-Bit D-Type Flip-Flop General Description The 74F821 is a 10-bit D-type flip-flop with 3-STATE true outputs arranged in a broadside pinout. Ordering Code: Features 3-STATE Outputs Devices also
More informationChapter 8. Low-Power VLSI Design Methodology
VLSI Design hapter 8 Low-Power VLSI Design Methodology Jin-Fu Li hapter 8 Low-Power VLSI Design Methodology Introduction Low-Power Gate-Level Design Low-Power Architecture-Level Design Algorithmic-Level
More informationCOVER SHEET: Problem#: Points
EEL 4712 Midterm 3 Spring 2017 VERSION 1 Name: UFID: Sign here to give permission for your test to be returned in class, where others might see your score: IMPORTANT: Please be neat and write (or draw)
More informationMS BA Micro Altimeter Module
High resolution module, 20cm Fast conversion down to ms Low power, µa (standby < 0.5 µa) QFN package 5.0 x 3.0 x.0 mm 3 Supply voltage.8 to 3.6 V Integrated digital pressure sensor (24 bit Σ AC) Operating
More informationSimple Instruction-Pipelining (cont.) Pipelining Jumps
6.823, L9--1 Simple ruction-pipelining (cont.) + Interrupts Updated March 6, 2000 Laboratory for Computer Science M.I.T. http://www.csg.lcs.mit.edu/6.823 Src1 ( j / ~j ) Src2 ( / Ind) Pipelining Jumps
More informationEnrico Nardelli Logic Circuits and Computer Architecture
Enrico Nardelli Logic Circuits and Computer Architecture Appendix B The design of VS0: a very simple CPU Rev. 1.4 (2009-10) by Enrico Nardelli B - 1 Instruction set Just 4 instructions LOAD M - Copy into
More informationLecture 16 More Profiling: gperftools, systemwide tools: oprofile, perf, DTrace, etc.
Lecture 16 More Profiling: gperftools, systemwide tools: oprofile, perf, DTrace, etc. ECE 459: Programming for Performance March 6, 2014 Part I gperftools 2 / 49 Introduction to gperftools Google Performance
More information74F153 Dual 4-Input Multiplexer
74F153 Dual 4-Input Multiplexer General Description The F153 is a high-speed dual 4-input multiplexer with common select inputs and individual enable inputs for each section. It can select two lines of
More information74F402 Serial Data Polynomial Generator/Checker
Serial Data Polynomial Generator/Checker General Description The 74F402 expandable Serial Data Polynomial generator/ checker is an expandable version of the 74F401. It provides an advanced tool for the
More informationOperating systems and concurrency B03
Operating systems and concurrency B03 David Kendall Northumbria University David Kendall (Northumbria University) Operating systems and concurrency B03 1 / 13 Introduction A key function of OS is interrupt
More informationAnnouncements. Project #1 grades were returned on Monday. Midterm #1. Project #2. Requests for re-grades due by Tuesday
Announcements Project #1 grades were returned on Monday Requests for re-grades due by Tuesday Midterm #1 Re-grade requests due by Monday Project #2 Due 10 AM Monday 1 Page State (hardware view) Page frame
More informationOutline. EECS Components and Design Techniques for Digital Systems. Lec 18 Error Coding. In the real world. Our beautiful digital world.
Outline EECS 150 - Components and esign Techniques for igital Systems Lec 18 Error Coding Errors and error models Parity and Hamming Codes (SECE) Errors in Communications LFSRs Cyclic Redundancy Check
More informationProgrammable Logic Devices
Programmable Logic Devices Mohammed Anvar P.K AP/ECE Al-Ameen Engineering College PLDs Programmable Logic Devices (PLD) General purpose chip for implementing circuits Can be customized using programmable
More informationSimple Instruction-Pipelining. Pipelined Harvard Datapath
6.823, L8--1 Simple ruction-pipelining Laboratory for Computer Science M.I.T. http://www.csg.lcs.mit.edu/6.823 Pipelined Harvard path 6.823, L8--2. I fetch decode & eg-fetch execute memory Clock period
More informationPC100 Memory Driver Competitive Comparisons
Fairchild Semiconductor Application Note March 1999 Revised December 2000 PC100 Memory Driver Competitive Comparisons Introduction The latest developments in chipset and motherboard design have taken memory
More informationEECS150 - Digital Design Lecture 23 - FFs revisited, FIFOs, ECCs, LSFRs. Cross-coupled NOR gates
EECS150 - Digital Design Lecture 23 - FFs revisited, FIFOs, ECCs, LSFRs April 16, 2009 John Wawrzynek Spring 2009 EECS150 - Lec24-blocks Page 1 Cross-coupled NOR gates remember, If both R=0 & S=0, then
More informationBasic Computer Organization and Design Part 3/3
Basic Computer Organization and Design Part 3/3 Adapted by Dr. Adel Ammar Computer Organization Interrupt Initiated Input/Output Open communication only when some data has to be passed --> interrupt. The
More informationThe Analysis of Microburst (Burstiness) on Virtual Switch
The Analysis of Microburst (Burstiness) on Virtual Switch Chunghan Lee Fujitsu Laboratories 09.19.2016 Copyright 2016 FUJITSU LABORATORIES LIMITED Background What is Network Function Virtualization (NFV)?
More informationProject Two RISC Processor Implementation ECE 485
Project Two RISC Processor Implementation ECE 485 Chenqi Bao Peter Chinetti November 6, 2013 Instructor: Professor Borkar 1 Statement of Problem This project requires the design and test of a RISC processor
More informationDynamic Noninterference Analysis Using Context Sensitive Static Analyses. Gurvan Le Guernic July 14, 2007
Dynamic Noninterference Analysis Using Context Sensitive Static Analyses Gurvan Le Guernic July 14, 2007 1 Abstract This report proposes a dynamic noninterference analysis for sequential programs. This
More informationCircuit Modeling for Practical Many-core Architecture Design Exploration
Circuit Modeling for Practical Many-core Architecture Design Exploration Redefining design abstractions Dean Truong Bevan Baas VLSI Computation Lab University of California, Davis Outline Motivation Circuit
More informationHardware Acceleration of the Tate Pairing in Characteristic Three
Hardware Acceleration of the Tate Pairing in Characteristic Three CHES 2005 Hardware Acceleration of the Tate Pairing in Characteristic Three Slide 1 Introduction Pairing based cryptography is a (fairly)
More informationExcellent Integrated System Limited
Excellent Integrated System Limited Stocking Distributor Click to view price, real time Inventory, Delivery & Lifecycle Information: Fairchild Semiconductor PC For any questions, you can email us directly:
More information74F537 1-of-10 Decoder with 3-STATE Outputs
1-of-10 Decoder with 3-STATE Outputs General Description The 74F537 is one-of-ten decoder/demultiplexer with four active HIGH BCD inputs and ten mutually exclusive outputs. A polarity control input determines
More informationFrom Sequential Circuits to Real Computers
1 / 36 From Sequential Circuits to Real Computers Lecturer: Guillaume Beslon Original Author: Lionel Morel Computer Science and Information Technologies - INSA Lyon Fall 2017 2 / 36 Introduction What we
More informationHardware implementations of ECC
Hardware implementations of ECC The University of Electro- Communications Introduction Public- key Cryptography (PKC) The most famous PKC is RSA and ECC Used for key agreement (Diffie- Hellman), digital
More informationMM74C912 6-Digit BCD Display Controller/Driver
6-Digit BCD Display Controller/Driver General Description The display controllers are interface elements, with memory, that drive a 6-digit, 8-segment LED display. The display controllers receive data
More informationTimeline of a Vulnerability
Timeline of a Vulnerability Is this all a conspiracy? Vulnerability existed for many years 1 Daniel Gruss, Moritz Lipp, Michael Schwarz www.iaik.tugraz.at Timeline of a Vulnerability Is this all a conspiracy?
More informationNew Exploration Frameworks for Temperature-Aware Design of MPSoCs. Prof. David Atienza
New Exploration Frameworks for Temperature-Aware Degn of MPSoCs Prof. David Atienza Dept Computer Architecture and Systems Engineering (DACYA) Complutense Univerty of Madrid, Spain Integrated Systems Lab
More informationCMP N 301 Computer Architecture. Appendix C
CMP N 301 Computer Architecture Appendix C Outline Introduction Pipelining Hazards Pipelining Implementation Exception Handling Advanced Issues (Dynamic Scheduling, Out of order Issue, Superscalar, etc)
More informationDPA-Resistance without routing constraints?
Introduction Attack strategy Experimental results Conclusion Introduction Attack strategy Experimental results Conclusion Outline DPA-Resistance without routing constraints? A cautionary note about MDPL
More informationPerformance, Power & Energy. ELEC8106/ELEC6102 Spring 2010 Hayden Kwok-Hay So
Performance, Power & Energy ELEC8106/ELEC6102 Spring 2010 Hayden Kwok-Hay So Recall: Goal of this class Performance Reconfiguration Power/ Energy H. So, Sp10 Lecture 3 - ELEC8106/6102 2 PERFORMANCE EVALUATION
More information