Semantics of RTL and Validation of Synthesized RTL Designs using Formal Verification in Reconfigurable Computing Systems

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1 emntis of TL nd Vlidtion of ynthesized TL Designs using Forml Verifition in eonfigurle Computing ystems Phn C. Vinh nd Jonthn P. Bowen London outh Bnk University Centre for Applied Forml Methods, Institute for Computing eserh Fulty of BCIM, 13 Borough od, London E1 AA, UK UL: Emil: Astrt The funtionl vlidtion of stte-of-the-rt reonfigurle omputing system design is usully lorious, d ho nd open-ended tsk. It n e omplished through two si pprohes: simultion nd forml verifition. In vlidtion using forml verifition pproh, it ttempts to estlish tht the egister Trnsfer Level (TL design synthesized from the lgorithmi ehviorl speifition is mthemtilly orret. Therefore, finding the verifition methods to provide urte nd fst vlidtion esily would e very useful. In this pper, we develop semntis sed on Prtil Order Bsed Model (POM for TL nd, through this semntis, propose forml verifition method to prove the orretness of the TL synthesis result. This method n e used to hieve the following. On one hnd, it n urtely verify n TL desription with respet to ehviorl speifition of the system; on the other hnd, it n deide whether two proesses, whih re supposed to implement the sme funtion, hve the sme intertive ehviors so tht one n e repled y the other. 1 Introdution As high-level synthesis (HL in reonfigurle omputing systems eome more sophistited nd synthesized designs get more omple, it is importnt tht we develop systemti pproh to the vlidtion of synthesized egister Trnsfer Level (TL designs [13, 14]. Funtionl vlidtion of synthesized TL design n e usully omplished through two si pprohes: simultion nd forml verifition [4, 6, 7]. In this pper, we present our efforts to develop Prtil Order Bsed Model (POM sed semntis for TL nd, through these, to verify formlly the TL designs generted y n HL system tht epts lgorithmi ehviorl speifitions written in suset of VHDL nd genertes register trnsfer level design, lso epressed in VHDL. Vlidtion using forml verifition methods ttempts to estlish tht the TL design synthesized from the lgorithmi ehviorl speifition is mthemtilly orret. Theorem proving nd model heking re two populr forml verifition pprohes. Our pproh is to model the ehvior using POM notion nd use this model to develop interesting properties of the model tht should hold oth t the ehvior nd register trnsfer levels. After the TL design is synthesized, we will verify whether the sme properties ontinue to hold for the TL design. This pper is orgnized s follows. etion will drw some min shpes of relted work. etion 3 will present some si definitions of POM notion. etion 4 gives the POM semntis for the TL model. A verifition lgorithm for the TL synthesis results in reonfigurle omputing systems using POM is presented in setion 5 nd short onlusion is given in setion 6. elted Work Another vlidtion methodology of synthesized TL designs is to use simultion pproh, s presented informlly in [6, 7], for ompring simultion results of n lgorithmi VHDL speifition nd synthesized TL design, lso represented s VHDL desription, whih llows hnge in the yle-y-yle ehvior without signifint limittions. To enle this omprison, ommon set of simultion vetors is used. The informtion given in this vetor set serves s input to its POM, with whih the omprison is eeuted. eently, numer of reserhers hve een investigting tehniques known s prtil-order methods tht n signifintly redue the running time of forml vlidtion y voiding redundnt eplortion of eeution senrios. The results in [4] desrie the design of prtil-order lgorithm for the vlidtion tool nd disuss its effetiveness. It shows

2 tht reful ompile-time stti nlysis of proess ommunition ehvior yields informtion tht n e used during vlidtion to drmtilly improve its performne. 3 ome definitions Definition 3.1 (Chu spe A Chu spe is inry reltion etween two sets A nd X. It is written s triple (A, X,, where : A X {, 1} is the inry reltion s hrteristi funtion of suset of A X. A Chu spe [5] does not impose ny rdinlity restritions on A nd X. Thus ll rguments given elow will work for ll rdinlities. We n think of A s the set of events (representing the tions nd X s the set of sttes (representing the possile or permitted sttes. A stte is defined in terms of n ourrene reltion (, tht is true when the event hs ourred in the stte. Thus, eh stte is suset of A ontining the events tht hs ourred in the stte. The visul wy to write out Chu spe epliitly is s inry mtri of dimension A X, with eh entry giving the vlue of the reltion on its pir of oordintes. A is written t the top nd X on the side. Figure 1 gives emples of some Chu spes. The elements of A re denoted y,,, d,..., nd u, v, w,,... for elements of X. Mtri 1 1 Hsse Digrm Mtri Mtri Hsse Digrm Hsse Digrm Figure 1. Chu spes nd its representtions Definition 3. (POM A POM is Chu spe C given y the tuple (A, X,, where A = {, 1,..., n } is set of events, X = {, 1,..., n } is set of sttes, nd : A X {, 1} represents the ourrene reltion; i.e., (, = 1 if the event hs ourred in the 11 1 stte nd (, =, otherwise. Eh stte i A is defined in terms of s: i = { A nd (, i = 1} The POM in Figure hs three events, {,, }, nd si sttes, {, 1,, 3, 4, 5 }. It represents system where ny event of {,, } ours nd ording to the informtion omputed y tht event, one of two rest events will our. In stte, the event hs ourred; represents the stte where hs ourred fter or hs ourred fter. And so on. We n represent the POM in the form of mtri or s logil formul or s Hsse digrm [11]. In the mtri, eh entry (, ontins the vlue of the ourrene reltion. Thus, the rows of the mtri orrespond to the sttes of the POM nd the olumns orrespond to the events of the POM. Considering the mtri s truth tle, we n hve logil formul representing the POM. The pitoril representtion s Hsse digrm illustrtes the prtil order eisting etween the sttes. POM=(A,X, where A={,,} X={{},{},{,},{},{,},{,}} (A,X is represented y the following inry mtri. Mtri Logil formul Hsse Digrm f POM= 1 {} {} {,} {} {,} {,} 1 1 Figure. POM nd its representtions Definition 3.3 (Logil epresenttion We define the logil representtion f C of the POM C s: f C = <i<n f i where n = X nd f i is the logil formul orresponding to i X, defined s follows: f i = ( { A} nd (, i = 1 ( { A} nd (, i = In the logil representtion, we hve the events s vriles, the sttes s terms of the formul nd the reltion determines whether the vrile ppers omplemented or not. The logil formul f is true for eh stte tht is permitted in the POM. 11 1

3 4 POM-sed semntis for TL Ck in i Ck in j As strting point, we del with the prolem of oneto-one synhroniztion with vlue ehnge, irrespetive of the vlue tully ehnged [3, ]. ynthesis of the omple synhroniztion into TL form requires the use of severl signls to gurntee the semnti orretness of the synthesis. o eh synhroniztion opertion (event is ssoited with three signls, one for the ehnge of the dt itself nd two others to mnge the synhroniztion ( redy nd n knowledgment signl. The need for two signls for synhroniztion is due to the ft tht ommunition is rendezvous etween events. Let us ssume we hve two proesses, nd, whih respetively offer nd re le to ept vlue v through gte g t ertin time. In this se, two gtes re involved in the synhroniztion, one of whih offers vlue (epressed y the symol!, while the other epts vlue (indited y?. This sitution is epressed s in the two following sets of events: g where = {... g!v...} = {... g?v...} hemtilly, synthesis of the events g!v nd g?v n e represented s in Figure 3. The signl in i (in j represents the signl enling eeution of lok i(j nd signl out i (out j represents the termintion of lok i(j (whih oinides with the signl enling eeution of the lok i + 1. The signl g n is needed when hoie opertion is involved in the synhroniztion. The loks i nd j re synthesized into the TL lnguge s in Figure 3. The trnsmitter wits for the reeiver to e ville for synhroniztion, fter whih it knowledges the synhroniztion nd ehnges the vlue (if ny; v T represents the vrile ontining the vlue to e trnsferred, whih in TL is equivlent to register. The ehvior of the reeiver omplements tht of the trnsmitter; v is the register tht, following synhroniztion, will ontin the vlue ehnged. Aording to the synthesis sheme used, the trnsmitter is trnslted in four TL steps nd the reeiver in three steps. 4.1 et of events Let us onsider the one-to-one synhroniztion with vlue ehnge desried ove. Eh synhroniztion event is ssoited with three signls: one for the ehnge of the dt itself (g n, nd two others to mnge the synhroniztion (g rdy nd g k. In the sequel, we onsider the finite event set A = {( g rdy, g k, g n, ( g rdy, g k, g n, ( g rdy, g k, g n, ( g rdy, g k, g n, (g rdy, g k, g n, (g rdy, g k, g n i! ( out i g k g v g rdy g k g v g rdy out j... : : if( g rdy ; g rdy goto( ; +1 // Wit for the reeiver to e redy to +1 : g k 1 synhronize // Aknowledges the synhroniztion + : if( g n ; g n goto( ; +3 // Wit for the synhroniztion to e orretly +3 : g v v T onluded y the reeiver (g n=1 // Ehnges the vlue... :... : y : g rdy 1 ; if( g k ; g k goto(y ; y+1 ( Trnsltion of 3( j? ( g n // Wrns the trnsmitter to e redy for synhroniztion nd simultneously sends n k signl y+1 : g n 1 // Informs trnsmitter tht synhroniztion hs tully ourred y+ : v g v // Aepts the vlue... : (d Trnsltion of 3( Figure 3. The si intertion events nd TL lnguge g n, (g rdy, g k, g n, (g rdy, g k, g n }. At eh rising edge of the lok, n tion must e eeuted. The mening of the event set is tht the tion ( g rdy, g k, g n is eeuted when no g rdy, no g k nd no g n our; ( g rdy, g k, g n is eeuted when no g rdy nd no g k our ut only g n ours; nd so on. Definition 4.1 (Computtion A finite sequene of tions is omputtion over A nd the set of ll omputtions is denoted y A*. 4. et of ttes Let X e the set of sttes representing the possile or permitted sttes. A stte y X is defined in terms of trnsition reltion T (, when the event A n mke trnsition from the stte X to y. Thus, eh stte y is suset of A ontining the events tht n mke trnsition from tht stte, tht is y = { A nd T (, = y} Definition 4. (uessor nd Predeessor ttes A stte i X is predeessor of stte j X if T (, i = j. Thus, j is suessor of i.

4 Definition 4.3 (Initil tte A stte i X is initil stte when it hs no predeessors; i.e., there is no stte j X suh tht T (, j = i. Definition 4.4 (Finl tte A stte i X is finl stte when it hs no suessors; i.e., there is no stte j X suh tht T (, i = j. Indeed, the triple (A, X, T is POM s defined in setion 3 nd the omputtion in definition 4.1 n e lso understood s follows: omputtion Γ of POM (A, X, T is prtil order on X under trnsition reltion T ; i.e., Γ = (, 1,..., n where for ll i, i+1 Γ, i+1 is suessor of i. Definition 4.5 (POM Eeution An eeution α of POM (A, X, T is n infinite sequene of omputtions Γ i of (A, X, T. From this oservtion we will develop the notion of POMutomt in the setions elow. 4.3 POM-Automt A POM-utomton is triple A = (X,, T where X is finite set of sttes, is the initil stte, T is funtion from X A into X { }, the trnsition funtion. If T (, =, no trnsition leled y n e fired from stte. ( n e viewed s sink stte. A omputtion Γ = 1... n is epted y the utomton if there eists 1,..., n X suh tht: T (, 1 = 1 i > 1, T ( i 1, i = i This will e denoted y: n 1 n n If it is not the se, there eists 1 k n nd sequene of sttes suh tht: k k 1 uh pth through n utomton is lled the run of the utomton over the omputtion Γ. The set of ll omputtions epted y A will e denoted y L(A. The POMutomt of trnsmitters nd reeivers onsist of four sttes nd three sttes, respetively, s in Figure 4. In Figure 4(, the stte nmed stte (or orresponds to witing for the reeiver to e redy to synhronize (g rdy =, stte 1 (or 1 orresponds to the enled trnsmitter due to redy signl from the reeiver (g rdy = 1, stte (or to knowledgement of the synhroniztion (g k = 1 nd stte 3 (or 3 to the to the orret onlusion of the synhroniztion y the reeiver (g n = 1. In Figure 4(, the stte nmed stte (or orresponds to wrning the trnsmitter to e redy for synhroniztion nd simultneously sends n k signl (g rdy = 1; stte 1 (or 1 orresponds to knowledgement of the synhroniztion (g k = 1, nd stte (or to informing the trnsmitter tht synhroniztion hs tully ourred (g n = 1.! g rdy g k g n tte ( z z tte 1( 1 1 z tte ( 1 1 tte 3( where: z {,1} (,z,z (1,,z 1 (1,1, (1,1,1 (1,,z (1,1, (1,1,1 (? g rdy g k g n tte ( 1 z tte 1( tte ( where: z {,1} (1,,z (1,1, 1 (1,1,1 (1,1, (1,1,1 ( Figure 4. POM-utomton representtions We now present n utomt produt tht llows modulr desription of more omple proess. Eh suproess n e modeled n utomton nd the model of the omplete proess n e otined y omputing the produt of ll su-proess utomt. 4.4 POM-Automt Produt The proesses nd n e onneted s in Figure 5. Let = (X ; ; T nd = (X ; ; T e the utomt tht model the proesses nd respetively. We define the produt,, of nd to model the proess otined y linking to. We wnt to synhronize outputs 3

5 of with inputs of so tht when dt trnsfer etween nd is possile then this trnsfer must hppen. This leds to the following definition of the produt of nd, over the sme event set A: = (X,, T where X = X X = T is defined in the following wy: Let i = ( j, k e in X nd in A. If there eist g n! g v g k g rdy g v? g n j+1 X nd k+1 X suh tht T ( j, = j+1 nd T ( k, = k+1, we set Otherwise, we set T (( j, k, = ( j+1, k+1 T (( j, k, = Let us ssume the input (output width of is equl to the output (input width of, so tht these proesses n e onneted s in Figure 5. Eh stte in is pir onsisting of stte from nd stte from. The run of over the epted omputtion Γ = (1, 1, (1, 1, 1 is denoted s elow: ( 1, (1,1, (, 1 (1,1,1 ( 3, This mens tht in the stte ( 1, on event (1,1,, the utomton proeeds y eeuting from 1 nd in prllel, eeuting from, nd so on. 4.5 Equivlene of proesses Let A nd A e two proesses nd A nd A e their ssoited POM-utomt. A nd A re equivlent L(A = L(A In other words, the proesses A nd A re equivlent if they nnot e distinguished y their eternl ehviors. 4.6 POM emntis A POM n e interpreted s POM-utomton with set of events A nd set of possile sttes X. Being in stte, the POM-utomton eeutes some trnsitions over events to reh suessor stte of. Eh possile omputtion of the POM orresponds to eh run of the POM-utomton nd the eeution of the POM represents the set of POMutomton runs. A POM-utomton in terms of POM model is represented y the set of events A nd the events our t eh stte; i.e., the trnsition reltion T. A more prtil pproh sed on reltions etween sttes is tht eh POMutomton is modeled s set of reltions etween sttes nd for eh suh reltion we hve orresponding POM. ( g rdy g k g n = ( 1 1 z 1 = ( = ( where: z {,1} (1,,z (1,1, (1,1, 1 ( (1,1,1 (1,1,1 Figure 5. The onnetion of proesses nd nd its POM-utomton The POM of eh reltion etween sttes is onsidered s property of the POM-utomton. Thus, onjuntion of the properties will result in the POM-utomton. 5 Verifition Algorithm for the TL ynthesis esults 5.1 teps of the lgorithm Our verifition lgorithm is shown digrmmtilly in Figure 6. The steps of the lgorithm will e onsidered in the susetions elow. 5. Algorithmi ehviorl speifition The lgorithmi desription is speified using n pproprite high-level lnguge. A mjor tsk during this step is the reliztion of the different sheduling modes. In other words, progrm is reted in this step.

6 Algorithmi ehviorl speifition TL Dynmilly reonfigurle omputing epresses the notion tht the dynmi seletion of if... then... else desries the reonfigurtion in similr wy to the C MUX dynmi reonfigurtion strtion proposed y Luk et l., reported in [1] nd to lesser etent in [9], whih requires ll the lterntives to hve inputs of the sme type nd n output of the sme type. This dynmi seletion is lso similr to the sheme presented in [1], whih is little more generl thn C MUX mehnism. The sheme in [1] n desrie dynmi seletion etween ehviors with totlly different types. The design of Fleile Arry Bloks (FABs [8] nd edued Fleile Arry Bloks (FABs [15] n e epressed using dynmi seletion euse the reonfigurtion ehvior is ontrolled y four onfigurtion its, whih re inputs to the dynmi seletions nd essentilly enle dynmi seletion. 5.3 Creting the POM P EC Crete POM PEC Crete POM PEC - utomton Comprison esult Crete POM TL - utomton Figure 6. The verifition lgorithm the TL synthesis results using POM In the VHDL emple shown in the Figure 7, we hve proess P with five events relted to the sttements of P, in whih eh sttement is onsidered s n event. The min tsk is the genertion of the prtil order desription of the progrm sttements reted in setion 5.. In other words, this desription is used to indite the dt dependenies of sttements neessry for the genertion of the possile POM desription of the lgorithmi speifition, nmely (POM P EC. To fulfill this tsk, we need to eplin some terminologies in terms of the following si reltions etween events: independene, preedene, onflit nd disjuntive enle reltion [11]. Definition 5.1 (Independene reltion The independene reltion ( represents the independent eeution of two events nd. The POM for this reltion is shown in Figure 8, where ll sttes re permitted; tht is, ll susets of A re vlid sttes. No order is imposed to the ourrene of the events nd. P: proess egin events red(a,b; if (A>B then C:=A+B; else C:=s(A-*B; end if; send(c, hnnel1; end proess; Figure 7. A proess nd its event list f = p f p = = =1 + # f #= = + den f den= = + + Figure 8. ome si reltions etween events Definition 5. (Preedene reltion The preedene reltion ( represents the ourrene of the event followed y the ourrene of the event. The POM representtion for the reltion n e seen in Figure 8. This reltion is used to model the sequentil eeution of events. Definition 5.3 (Conflit reltion The onflit reltion (# represents either the ourrene of or the ourrene of. The orresponding POM nd logil formul re shown in Figure 8. A onflit reltion etween two events nd mens tht oth nd n never our in sme omputtion of the POM. Definition 5.4 (Disjuntive enle reltion The disjuntive enle reltion permits the representtion

7 of two events, whose eeutions disjuntively enle third event; i.e., den(,, mens the eeution of O enles the ourrene of. This reltion is needed, together with the onflit reltion eplined ove, to enle the events tht follow n if... then... else sttement. Figure 8 presents the POM nd its orresponding logil formul. In our prtil pproh to reting POM P EC, we use the reltions etween events. These reltions n e etrted from the system speifition given in high-level progrmming lnguge s in setion 5.. Let there e proess P with set of events A, together with reltions etween events, whih were etrted from tht proess speifition s follows. In Figure 7, we hve five events, where preedes 1, 1 preedes, 1 preedes 3, nd 3 re in onflit, nd the eeution of O 3 enles the ourrene of 4. The onjuntion them give us the POM for the proess P. Formlly, POM P EC is desried s POM P EC = { 1, 1, 1 3, # 3, den( 4,, 3 } 5.4 Creting the POM P EC -utomton From the event list nd dependeny reltions etween the events reted in setion 5.3, n utomton of the POM P EC is reted (see Figure TL ynthesis esult This is n TL synthesis result of the lgorithmi ehviorl speifition. This result hs een reted from the synthesis stge nd is trnsferred into the urrent verifition. The TL module [1, 3] is defined y the following: Components: ontins the delrtion of the omponents tht mke up the proessing unit. Control sequene: defines the internl ommnd sequene tht must e emitted y the ontrol unit. Permnent ssignment: defines n opertion tht must e repeted every lok yle. The ontrol sequene is mde up of steps; eh one is numered nd must e eeuted in single lok unit. Figure 1 shows this ontrol sequene for the proess P. (, 1,, 3, 4 (, 1,, 3, 4, 1,, 3, 4 (, 1,, 3,, 1,, 3,,,,, ( 4 ( 4 (, 1,, 3, 4 (, 1,, 3, 4 1 (, 1,, 3, ( 1 3 4, 1,, 3, (, 1,, 3, 4 5 ( 4 (, 1,, 3, 4 Figure 1. TL ontrol of proess P POM PEC = { p 1, 1 p, 1 p 3, # 3, den( 4,, 3} nd POM PEC utomton Logil formul: f = f p 1 Λ f 1 p Λ f 1 p 3 Λ f # 3 Λ f den(4,, 3 = ( 1 ( 3 = Λ ( 1 + Λ ( Λ + Λ ( Figure 9. POM P EC -utomton of proess P 5.6 Creting the POM T L -utomton A POM-utomton needs to e generted from the TL synthesis result. From the TL of proess P s shown in Figure 1, POM T L -utomton is reted s in Figure 11. POM TL utomton y 1 where:,y {,1} nd y Figure 11. POM T L -utomton of proess P

8 5.7 Comprison etween the POM P EC - utomton nd POM T L -utomton In ompring the POM speifition nd TL utomt, we need to determine the following to verify the orretness of n TL synthesis result. Definition 5.5 (Corretness of n TL ynthesis result An TL synthesis result using POM is orret iff it stisfies ll requirements of the POM speifition. Theorem 5.1 An TL synthesis result using POM is orret iff L(T L = L(PEC. In other words, the set of ll omputtions epted y T L is equl to the ones epted y PEC. Proof 5. if prt. By definition 5.5, when L(T L is equl to L(PEC then n TL synthesis result is orret. To prove the only if prt, we need to prove tht if L(T L L(PEC then the TL synthesis result is not orret. There re two ses s follows: If L(T L L(PEC then there eists requirement of omputtion Γ L(PEC\L(T L tht is not synthesized in the TL result. By definition 5.5, the TL synthesis result is not orret. If L(PEC L(T L then the speifition nd TL synthesis re not equivlent. In onsequene of this, their omputing ehviors re distint. In other words, the TL synthesis result is not orret s well. This onsidertion shows tht if the synthesis proess hs generted vlid TL result, then omprison is rried out here s n emintion tht heks whether POM T L - utomton is equivlent to POM P EC -utomton. Indeed, Figures 9 nd 11 show tht L(T L = L(PEC; thus the verifition indites the orretness of the TL synthesis results for the proess P. 6 ummry In this pper, Prtil Order Bsed Model (POM sed semntis for egister Trnsfer Level (TL desription nd verifition lgorithm hve een developed for vlidting the TL synthesis results. ome key fetures of this pproh re tht, firstly, the notion of POM (s Chu spe is onsidered s semnti si for TL nd, seondly, the notion of POM-utomt is dedited towrds forml orretness of the synthesis result t the register trnsfer level. The forml verifition method is sed on funtionl equivlene heking to determine if the POM T L -utomton is equivlent to the POM P EC - utomton. In other words, omprison is defined s n emintion tht heks whether the synthesis proess hs generted vlid TL desription. eferenes [1] B. Biley nd D. Gjski. TL semntis nd methodology. In Pro. 14th Interntionl ymposium on ystems ynthesis, pges 69 74, Montrel, Cnd, 3 eptemer 3 Otoer 1. [] V. Crhiolo, M. Mlgeri, nd G. Mngioni. An lgorithm for diret synthesis of forml speifitions. In Pro. 8th IEEE Interntionl Workshop on pid ystem Prototyping, pges 8 38, 4 6 June [3] V. Crhiolo, M. Mlgeri, nd G. Mngioni. Hrdwre/softwre synthesis of forml speifitions in odesign of emedded systems. ACM Trnstions on Design Automtion of Eletroni ystems, 5(3:399 43, July. [4] P. Godefroid, D. Peled, nd M. tskusks. Using prtilorder methods in the forml vlidtion of industril onurrent progrms. IEEE Trnstions on oftwre Engineering, (7:496 57, July [5] V. Gupt. Chu pes: A Model of Conurreny. PhD thesis, tnford University, UA, [6] C. Hnsen, A. Kunzmnn, nd W. osenstiel. Verifition y simultion omprison using interfe synthesis. In Pro. Design, Automtion nd Test in Europe (DATE, pges , 3 6 Ferury [7] C. Hnsen, F. A. M. D. Nsimento, nd W. osenstiel. Verifying high level synthesis results using prtil order sed model. In Pro. Hrdwre Lnguges, Design, Verifition nd Test (HLDVT, n Diego, CA, UA, Novemer [8]. D. Hynes nd P. Y. K. Cheung. A reonfigurle multiplier rry for video imge proessing tsks, suitle for emedding in n FPGA struture. In Pro. IEEE ymposium on FPGAs for Custom Computing Mhines, pges 6 34, April [9] W. Luk, N. hirzi, nd P. Y. K. Cheung. Compiltion tools for run-time reonfigurle designs. In Pro. 5th Annul IEEE ymposium on FPGAs for Custom Computing Mhines, pges 56 65, April [1] W. Luk, N. hirzi, nd P. Y. K. Cheung. Modelling nd optimising run-time reonfigurle systems. In Pro. IEEE ymposium on FPGAs for Custom Computing Mhines, pges , April [11] F. A. M. D. Nsimento nd W. osenstiel. Prtil order sed modeling of onurreny t the system level. In Pro. Interntionl Workshop on Conjoint ystems Engineering (CONYE, BdTölz, Germny, Mrh [1]. ingh. Interfe speifition for reonfigurle omponents. In Pro. IEEE/ACM Interntionl Conferene on Computer Aided Design (ICCAD, pges 1 19, n Jose, UA, 1 14 Novemer. [13] P. C. Vinh nd J. P. Bowen. An lgorithmi pproh y heuristis to dynmil reonfigurtion of logi resoures on reonfigurle FPGAs. In Pro. ACM/IGDA 1th Interntionl ymposium on Field Progrmmle Gte Arrys, pge 54, Monterey, UA, 4 Ferury 4. [14] P. C. Vinh nd J. P. Bowen. On the visul representtion of onfigurtion in reonfigurle omputing. Eletroni Notes in Theoretil Computer iene (ENTC, 19:3 15, 4. [15] C. Visvkul, P. Y. K. Cheung, nd W. Luk. A digit-seril struture for reonfigurle multipliers. In G. J. Brener nd. Woods, editors, Field-Progrmmle Logi nd Applitions, volume 147 of Leture Notes in Computer iene, pges pringer-verlg, 1.

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