DEPARTMENT OF ECE Faculty of Engineering and Technology, SRM University 15EC203J DIGITAL SYSTEMS LAB

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DEPARTMENT OF ECE Faculty of Engineering and Technology, SRM University SRM Nagar, Kattankulathur 603203, Kancheepuram District, Tamilnadu 15EC203J DIGITAL SYSTEMS LAB LABORATORY REPORT COVER PAGE

1 DEPARTMENT OF ECE Faculty of Engineering and Technology, SRM University SRM Nagar, Kattankulathur , Kancheepuram District, Tamilnadu 15EC203J DIGITAL SYSTEMS LAB LABORATORY REPORT COVER PAGE Name of the Student : Register No. : Class : Level-II / Semester-I / B.Tech / ECE Academic Year : Expt. No. & Title : Date of Experiment : Due Date : Submission Date : Instructor(s) : Mr. Manikandan A V M Mrs.A.Vinnarasi Mrs.M.K.Srilekha Particulars Possible Marks Lab Questions 10 Assigned Simulation Exercise 10 Design & In-Lab performance 20 Promptness, Neatness and Organization 10 Total Marks 50 Remarks : Name / Sign / Stamp with date

2 AIM EXPERIMENT-3 PARITY GENERATOR AND CHECKER 1. To design and implement even parity generator and checker. 2. To determine the parity generator s output for each of the sets of input data D2, D1, D0. 3. To determine the parity checker s output for each of the set of data from the transmitter. 4. To verify the operation of 8-bit odd/even parity generator/checker with cascade inputs (IC 74180) MATERIALS REQUIRED 1. Semiconductors : IC's ,, 7404, Equipments : Digital IC Trainer kit and Digital Multimeter 3. Miscellaneous : Patch cords and/or connecting wires THEORY When digital signals are transmitted from one circuit or system, error may occur during transmission due to external noise into the physical communication medium. The change of a 1 to 0 or 0 to 1 during transmission is known as error. It is necessary to detect and correct the error to obtain a correct message. One of the most common ways to achieve error detection is by means of a parity bit. Any group of bits contains either an even or an odd number of 1 s. A parity is attached to a group of bits to make the total number of 1 s in a group always even or always odd. An even parity bit makes the total number of 1 s even and an odd parity bit makes the total odd. This particular example uses a group of 3 bits as data to be transmitted, and it uses an even parity. The set of data to be transmitted is applied to the parity generator circuit, which produces the even parity bit, P, at its output. This parity bit is transmitted to the receiver along with the original data bits, making a total of 4 bits. These 4 bits (data +parity) enter the receiver s parity checker circuit, which produces an error output, E, that indicates whether or not a single bit error has occurred. The parity checking scheme is valid for the detection of a single error in the word. Actually, it is valid for any odd number of errors, but the probability that three or more errors will occur in a given word is near zero. What a single-bit parity checking system cannot do is detect an even number of errors (eg., two errors). It is also true that the error checking system cannot correct any single error it detects. To do so would require detecting its location, which is no trivial task. To identify the location of an error bit requires multiple parity detection units on the submodular level down on the bit level, a significant cost in the hardware. However, when this is done, an erroneous bit can be corrected. Memory systems in modern computers have such single-error correction capability.

3 PRE-LAB QUESTIONS Answer the questions in the space provided 1. Add an even parity bit to each of the following codes: (a) (b) Add an odd parity bit to each of the following codes: (a) (b) Check each of the even parity codes for an error: (a) Error / No Error (b) Error / No Error EVEN PARITY GENERATOR Logic diagram D2 D1 D0 Parity (P) Truth table D2 D1 D0 PARITY(P)

4 EVEN PARITY CHECKER Logic diagram D2 D1 D0 P Truth Table Error (E) {1=Error; 0=no Error} D2 D1 D0 PARITY ERROR

74180 8-BIT ODD/EVEN PARITY GENERATOR/CHECKER WITH CASCADE INPUTS PARITY GENERATOR The IC74180 is monolithic 8 bit parity generator/checker commonly used to detect the error in high

The output details are marked in truth table. True active-high or True active-low parity can be generated at both the even or odd outputs.

5 BIT ODD/EVEN PARITY GENERATOR/CHECKER WITH CASCADE INPUTS PARITY GENERATOR The IC74180 is monolithic 8 bit parity generator/checker commonly used to detect the error in high speed data transmission or data retrieval systems. Both even and odd parity enable inputs and parity outputs are available for generating or checking parity on 8 bits. The output details are marked in truth table. True active-high or True active-low parity can be generated at both the even or odd outputs. True active-high parity is established with even parity enable input(even) set HIGH and the odd parity input(odd) set LOW. True active- Low output is established with even parity enable input (Even) set LOW and the odd parity input (Odd) set HIGH.

6 PARITY CHECKER Parity checking of a 9 bit word (8 bit plus parity) is possible by using the two enable inputs plus an inverter as the ninth data input. To check for true active-high parity, the ninth data input is tied to the PO input and an inverter is connected between the Odd and Even inputs as shown in fig. To check for true active-low parity, the ninth data input is tied to the PE input and an inverter is connected between the PE and PO inputs as shown in fig. Parity Checker-True active HIGH Parity Checker-True active LOW

7 PROCEDURE (A) 3-bit Parity Generator / Checker using Logic Gates 1. Connect the logic circuit of parity generator and checker. Remember to connect pin 14 of each of the ICs to +5v and pin 7 to ground. 2. Apply the data levels D2, D1, D0 to the parity generator inputs and determine the parity generator s output. Note that P is 1 only when the original data contain an odd number of 1 s. Thus the total number of 1 s sent to the receiver (data + parity) will be even. 3. Apply each of the sets of data D2, D1, D0, and Parity bit (P) from the transmitter to the parity checker inputs and determine the parity checker s output. Note that a 1 is produced at E only when an odd no of 1 s appear in the inputs to the parity checker. This indicates that an error has occurred, since even parity is being used. (B) 8-bit Odd/Even Parity Generator using IC Place the IC74180 in the bread board. Connect pin-14 of the IC to +5v and pin-7 to ground. 2. Set even parity enable input (Even) to HIGH and the odd parity input (Odd) to LOW for obtaining True Active-HIGH parity at both the even or odd outputs. 3. Apply the data levels A, B, C, D, E, F, G, and H to the parity generator inputs and determine the parity generator s output, and verify the 1 st & 2 nd row entries of the function table of the IC Set even parity enable input (Even) to LOW and the odd parity input (Odd) to HIGH for obtaining True Active-LOW parity at both the even or odd outputs. 5. Apply the data levels A, B, C, D, E, F, G, and H to the parity generator inputs and determine the parity generator s output, and verify the 3 rd & 4 th row entries of the function table of the IC (C) 9-bit Odd/Even Parity Checker using IC Apply the 9-bit word (8-bit data plus parity). 7. Apply the 8-bit data word to the inputs pins marked A to H of the parity checker IC Apply the 9 th bit (parity bit) to the PO input. Connect an inverter between the Odd and Even inputs as shown in figure. Check for true active-high parity. 9. Apply the 9 th bit (parity bit) to the PE input. Connect an inverter between the Odd and Even inputs as shown in figure. Check for true active-low parity. POST-LAB QUESTIONS 1. Modify the 3-bit parity generator circuit with a control input to generate either an even or odd parity generate output. Verify the operation using logisim simulation. 2. Modify the 3-bit parity checker circuit with a control input to check either an even or odd parity error. Verify the operation using logisim simulation.

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT2: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 4 Following the slides of Dr. Ahmed H. Madian محرم 439 ه Winter 28