Analysis and Design Strategy of On-Chip Charge Pumps for Micro-power Energy Harvesting Applications

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1 Analysis and Design Strategy f On-Chip Charge Pumps fr Micr-pwer Energy Harvesting Applicatins Wing-Hung Ki, Yan Lu, Feng Su, Chi-Ying Tsui T cite this versin: Wing-Hung Ki, Yan Lu, Feng Su, Chi-Ying Tsui. Analysis and Design Strategy f On-Chip Charge Pumps fr Micr-pwer Energy Harvesting Applicatins. Salvadr Mir; Chi-Ying Tsui; Ricard Reis; Oliver C. S. Chy. 9th Internatinal Cnference n ery Large Scale Integratin (LSISOC), Oct 0, Hng Kng, China. Springer, IFIP Advances in Infrmatin and Cmmunicatin Technlgy, AICT-379, pp.58-86, 0, LSI-SC: Advanced Research fr Systems n Chip. <0.007/ _0>. <hal-05976> HAL Id: hal Submitted n 9 May 07 HAL is a multi-disciplinary pen access archive fr the depsit and disseminatin f scientific research dcuments, whether they are published r nt. The dcuments may cme frm teaching and research institutins in France r abrad, r frm public r private research centers. L archive uverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusin de dcuments scientifiques de niveau recherche, publiés u nn, émanant des établissements d enseignement et de recherche français u étrangers, des labratires publics u privés. Distributed under a Creative Cmmns Attributin 4.0 Internatinal License

2 Analysis and Design Strategy f On-Chip Charge Pumps fr Micr-Pwer Energy Harvesting Applicatins Wing-Hung Ki, Yan Lu, Feng Su and Chi-Ying Tsui ECE Department, HKUST, Hng Kng Bradcm Crpratin, San Jse, CA, USA {eeki, yanlu, eetsui}@ust.hk, fsu@bradcm.cm Abstract. Charge balance law based n cnservatin f charge is stated and emplyed t analyze n-chip linear, Fibnacci and expnential charge pumps. Fr micr-pwer n-chip implementatins, bth the psitive- and the negativeplate parasitic capacitrs have t be cnsidered. ltage cnversin ratis and efficiencies can be btained in clsed frm fr single- and dual-branch linear charge pumps, but nt fr Fibnacci and expnential charge pumps. Instead, a first iteratin apprximatin analysis fr cmputing vltage cnversin rati is prpsed. Fr the linear charge pump, efficiency ptimizatin is achieved by first cmputing the ptimal number f stages, and then btaining frm the required utput vltage the reductin factr that is a functin f lad current, flying capacitr and switching frequency. Using a 0.35m CMOS prcess, 8X linear, Fibnacci and expnential charge pumps are designed and their perfrmances are cmpared and cnfirmed by extensive Cadence Spectre simulatins. It is cncluded that linear charge pumps attain the best efficiency. Keywrds: charge balance, charge pump, charge redistributin, expnential charge pump, Fibnacci charge pump, linear charge pump Intrductin Micr-pwer energy harvesting and micr-sensr applicatins require fully nchip implementatin f pwer management units that include integrated switchedcapacitr pwer cnverters, r charge pumps (QPs). Embeed systems that have a stringent silicn estate need fully n-chip charge pumps fr reading and writing EEPROM. Fr n-chip charge pumps, efficiency in pwer and area are tw majr cncerns, and bth are clsely related t charge pump tplgies that determine the number f capacitrs and switches and lsses due t parasitic capacitrs. Integrated linear (r Dicksn) charge pumps (LQPs) are the mst ppular implementatins due t their simple structure and readily available design prcedures [-8]. With a -phase nn-verlapping clck, the Fibnacci charge pump (FQP) [9] and the expnential charge pump (EQP) [0, ] prmised t achieve very high vltage cnversin ratis using fewer capacitrs than the LQP, and bth are ptential candidates fr n-chip applicatins. Therefre, there is a practical need in analyzing which charge pump wuld have the best efficiency using the smallest area f n-chip capacitrs.

3 Cnsider a (linear) charge pump with N flying capacitrs and a lad capacitr. Fr each flying capacitr C k (the k th stage), ne plate is always at a higher ptential and is called the psitive plate, while the ther is the negative plate. Fr an n-chip capacitr C k, bth the psitive-plate and negative-plate parasitic capacitrs can be cnsidered t be prprtinal t C k, namely, C k and C k, respectively, and they are nt negligibly small. In [], the utput vltage was derived by assuming that all C k are equal and the lad capacitr C L is infinite, and equal C k gives the smallest ttal capacitance in maximizing []. The exact argument f hw t charge up an infinite capacitr was nt presented, and the efficiency was nt cnsidered. The Dicksn derivatin f [] used heuristic reasning in accunting fr C k and frmed the basis f many subsequent analyses [3-8]. Evidently, a mre slid derivatin n par with circuit analysis using Kirchhff's current and vltage laws is needed. In [3], the authrs cmmented that the utput vltage ripple culd be aed back t the case with C L =, but gave n cmputatin details. Nevertheless, the majr cncern f [3] (and [8]) was t cmpute the nn-ideal effect f the transistr switches. In [4], bth the lad capacitr and the parasitic capacitrs were nt cnsidered in analyzing the Dicksn charge pump, and n efficiency infrmatin was given. In [5] (and [7], an extended versin f [5]), the crrect equatin fr the utput vltage f an ideal linear charge pump with different C k and an infinite C L was put dwn withut elabratin. Mre imprtantly, it presents a design prcedure that minimizes the input current, which is equivalent t maximize the pwer cnversin efficiency. Hwever, C k are ignred in [5] as the authrs argue that the majr cntributins f lss are frm C k. T imprve the analysis f [5], bth C k and C k are included in [6], but it assumes that all C k are charged in bth phases, while in the steady state, any capacitr shuld have alternate charging and discharging phases in ne cycle. Despite the deficiencies, [5] and [6] are amng the very few publicatins that presented frmulae fr cmputing efficiency. While analyses f LQPs are numerus, there is n crrespnding analysis fr FQPs and EQPs, and they culd nt be easily analyzed by the Dicksn derivatin. In this research, the linear charge pump with parasitic capacitrs and a finite lad capacitr is analyzed. Ideal switches are assumed, as nn-ideal switches lead t incmplete charge transfer that shuld be dealt with in a separate wrk. Analysis n charge transfer and charge redistributin is based n systematic applicatin f the charge balance law (QBL) t be discussed in Sectin [, 3]. The utput vltage (t) and the average utput vltage are derived in Sectin 3, the pwer cnversin efficiency in Sectin 4, and and f the dual-branch linear charge pump in Sectin 5. Cadence Spectre simulatin results f single- and dual-branch linear charge pumps are presented in Sectin 6. The first iteratin apprximatin analysis is emplyed in analyzing Fibnacci and expnential charge pumps in Sectin 7 and Sectin 8, respectively [4]. All charge pumps are cmpared in Sectin 9. After cncluding that the linear charge pump is the mst efficient n-chip implementatin with the smallest area, a detail design strategy is prpsed in Sectin 0, fllwed by sme cncluding remarks in Sectin.

4 Charge Balance Law In circuit analysis, we use Kirchhff's current law and Kirchhff's vltage law systematically t slve prblems. It is beneficial t have a similar law fr analyzing switched-capacitr circuits including charge pumps. In fact, t facilitate the cmputatin f charge transfer, a law that is based n cnservatin f charge can be frmulated. The charge balance law (QBL) says In a system f capacitrs, the sum f all charges leaving a nde at any instance f charge transfer is equal t zer. It is bvius that the term "leaving a nde" can be replaced by "entering a nde" with the same validity. This law was first named Kirchhff's charge law in [] and then in [3], but is better be renamed as the charge balance law. It is als knwn simply as charge balance in [5]. Fig. shws n capacitrs (C, C,, C n ) t be cnnected at the nde a at t=t. Fr each capacitr, ne plate will be cnnected t a and let us arbitrarily assign that plate t be the psitive plate, while the negative plate will be cnnected t ther circuit cmpnents nt shwn. Prir t the charge transfer, the crrespnding capacitr vltages are C (t ), C (t ),, Cn (t ), and at t=t, charge transfer ccurs, such that when charge redistributin is cmpleted, the capacitr vltages are C (t + ), C (t + ),, Cn (t + ). Emplying QBL we have C (t ) C (t ). () n n k k Ck k k Ck A simple way t apply QBL is t remember Ttal Initial Charge = Ttal Final Charge. () In this paper, all equatins accunting fr charge transfer are written in the frm f (). C C n C t=t a Cn C 3 Fig.. Charge redistributin at the nde a. 3

5 3 Analysis f Single-Branch Linear Charge Pumps Fig. shws a single-branch N-stage linear charge pump (LQP) with a vltage cnversin rati M (= / ) that is equal t N+ if the lad current is zer. The analysis is simplified by having a lad current I instead f a lad resistr. The case using ideal switches and n parasitic capacitr has been derived in [3]. We nw turn t the general case that any n-chip (flying) capacitr C k has bth psitive-plate and negative-plate parasitic capacitrs C k and C k t grund. C Ck Ck C k CN c(k ) ck c(k ) cn dn (t) C Ck C k Ck C N d(k ) dk d(k ) dn C L I C c(k) Ck ck Ck c(k ) Ck cn C N Fig.. Single-branch (N+)X linear charge pump with parasitic capacitrs. Fig. 3 shws the vltages acrss the capacitrs C k, C k and C L. Every capacitr C x has a charging phase cx and a discharging phase dx. Fr example, fr k even, the charging phase f C k is ck =. We assign k as the capacitr vltage f C k (at the end) f its discharging phase. The analysis f charge pumps invlves mundane charge accunting, and ur experience tells us that it is mre efficient t wrk frm the utput side twards the input side. Fig. 3(d) shws the time-varying utput vltage (t), and let be the utput vltage at the beginning f the discharging phase f C N ( dn =). During dn =, the lad current I discharges C N and C L fr half f the clck perid T/, and IT/ ( )C C During the next phase cn =, C N is discnnected frm C L, and the lad current discharges C L and gives N IT/ 3. CL L. (3) (4) The utput vltage ripple is immediately given by IT 3. C [( )C C L ] L N (5) 4

6 / C C ( C) Ck k / Ck ( C ) k k k (C) (C) k k (a) t (b) dk ck dk t (c), CN CN dn N cn ( C N) Fig. 3. Capacitr and utput vltages f LQP: (a) C and C ; (b) Ck and Ck ; (c) CN and CN ; and (d) (t). While C L is discharged by I, C N is being charged up, and the charging phase f C N is the discharging phase f C N. Therefre, in cn =, C N is discharged t N, C N is charged t + N, and C N is discharged t + N. In fact, it will becme clear later that while the flying capacitr C k is being charged up, C k is being discharged (Fig. 4). At the start f the next clck phase, that is, at the instant f dn = again, C N redistributes charge with C L such that (t) is pumped up frm 3 t. Emply QBL gives ( )C ( ) C C ( ) C C. (6) N N L 3 N N L In substituting (3) and (4) int (6) we have IT N ()C. (7) Next, cnsider the charge redistributin f C N with C N, and QBL gives ( )C N( N) C N( ) CN. C C ( )( )C ( ) N N N N N N In making use f (7), (8) can be simplified t (C N) (N ) (t) N 3 t (d) dn dn cn dn t (8) IT N N. ()C N (9) 5

7 k k k C k C k k k C k Ck Fig. 4. Capacitr C k in discharging phase. We then cnsider the general k th stage, such that C k is charged up by C k in its charging phase ck, and redistributes charge with C k+ during its discharging phase dk. Emply QBL and an equatin similar t (8) can be written dwn. By gruping the terms invlving C k and C k+ n different side we btain Ck (+ )Ck k(+ )Ckk Ck (+ )Ck k(+ )Ck k. (0) An immediate relatin is revealed if we cnsider k=n such that the right hand side f (0) is equal t I T, and (0) is the same as (9) with a different index. Clearly, the same relatin prpagates dwn the charge pump, and we can rewrite (0) as I k k ( T)C. () Hwever, C has n prir stage, and 0 (nt ) is zer, that is, k I ( T)C. () The interpretatin f () is that the verall change in charge f each flying capacitr in ne cycle is the amunt f charge I T delivered t the adjacent higher stage in the same cycle. This charge transfer is independent f C L. Cnsider that when C k is charged t + k, the vltage acrss C k is als + k. When C k is discharged t k, the vltage acrss C k is + k. It is clear frm () that + k is larger than + k. Hence, when C k is being charged, C k is being discharged, but in [6], C k is assumed t be charged in bth phases. Next, substitute (9), () and () int (7), and we have N N IT k ()C An imprtant bservatin is that is independent f C L, and this prperty is very useful in simplifying the analysis fr the case f C L =. Frm, ne can write dwn and 3 frm (3) and (4) easily: N N IT IT/ k k N, ( )C ( )C C L k. (3) (4) 6

8 3 N N IT IT/. k( )C C The average utput vltage can be cmputed frm Fig. 3(d) by averaging the areas f trapezids as = ( )/4, that is, N N IT IT. k( )Ck 8 C L ( )CNCL A practical capacitance assignment requires C L >C k, and usually, C L >>C k, and the effect f C L is negligibly small; r equivalently, we may assume C L, such that =. T maximize ( ) and minimize the ttal capacitance C T it is clear that all C k shuld be set equal [, 3]: The ttal capacitance C T is k L (5) (6) C C... CN C. (7) CT NC, (8) and the utput vltage and the utput vltage ripple (with C L >>C k ) are then given by N NI T, ()C IT. C L Let us define the reductin factr as the fractinal vltage drp per stage due t the lad current I with the flying capacitr equal t C: IT. C The vltage cnversin rati M can then be written as NN. M As (as well as ) is fixed in a fabricatin prcess, the nly way t increase the utput vltage (=M ) is t use a small, that is, t use a large C r a high switching frequency f s (=/T) as design cnstraints allw. In Sectin 4, we will shw that this criterin is in cnflict with maximizing the efficiency in the presence f parasitic capacitrs. (9) (0) () () 7

9 4 Efficiency Optimizatin f Linear Charge Pumps After btaining the utput vltage as a functin f capacitrs, switching frequency and lad current, the next is t cmpute and ptimize the efficiency. Let E i be the input energy supplied by in ne cycle, and E the utput energy cnsumed by the lad in the same cycle. The efficiency f a charge pump is given by The term E is simply given by E E E. i (3) I T. (4) With reference t Fig., the term E i supplied by can be divided int three types: () E i is the cycle energy delivered t the psitive plates f C and C when being charged; () E ik is the cycle energy delivered t the negative plate f C k when it is discharged; and (3) E i3k is the cycle energy delivered t the psitive plates f C k when being charged. Hence, E E E E. (5) k N N i i k ik k i3 First f all, cnsider C being charged by. With reference t Fig. 3(a), when C is previusly discharged t, C is charged t ( + ). In the charging phase f C, if we assume there is n reversin lss, that is, the charge C ( + ) entirely redistributes with C first befre C is charged by, then the charge Q i supplied by is C C( ) Q i( )C. (6) Using () and that E i is equal t Q i, we have E i I T. (7) In cmputing E ik, dente the charge that is lst n the psitive plate f C k in its discharging phase as Q ik, and this charge has t be supplied by t the negative plate f C k. Hence, fr C k (kn), we have C( ) Q C. (8) k k ik k k Using () and that E ik is equal t Q ik, we have E ( I TC ik k Special care is needed fr C N, as its discharging phase cnsists f tw parts. The first part is fr C N t redistribute charge with C L, and the charge supplied by is Q in : ). N N in N (9) C( ) Q C( ). (30) 8

10 The secnd part is discharging C N and C L by I fr half f the perid, and the charge supplied by t C N is Q in : C( N ) QiN C( N ). (3) Using (7) in (3), and that the ttal cycle energy E in is given by (Q in +Q in ), we have E in (ITCN ). Here we prved that E in is independent f C L and has the same frm as E ik. Fr the negative-plate parasitic capacitrs, it is easy t btain E i3k as E i3k k (3) C. (33) Frm Sectin 3, the ptimal capacitr assignment is C k =C. Therefre, in cmbining (7), (9), (3) and (33) we have IT N α I T NC NC +α +α Frm the abve discussin, we bserve that the input cycle energy E i is independent f C L. In fact, C L plays an imprtant rle in determining the utput vltage ripple (5), but has a negligible effect n the average utput vltage (6). Fr all practical purpses, we may assume C L =, and (34) can be written as NN. N( ) N The reductin factr is required t be small if the utput vltage has t be as large as pssible, fr example, <0.05. Hwever, a small is achieved by a large C, which translates t large lsses f C and C. Frm (35), bth the psitiveplate and negative-plate parasitic capacitrs have cmparable effect n the efficiency. T maximize efficiency, if N is fixed, the nly parameter that can be changed is, and we need t slve fr the cnditin d/d=0. T make the differentiatin easier, we rewrite (35) as ( ), ( ). (34) (35) (36) with N N, (37). (38) 9

11 The ptimal reductin factr is btained as pt, and the crrespnding maximum efficiency is max pt (39). (40) Hwever, if a predefined has t be achieved, pt btained in (39) may nt satisfy (). T satisfy (), we substitute int (35) and btain N ( ) M (4) N ( )M. N N N ( )(M ) As (+)M is a cnstant, maximizing is the same as minimizing the denminatr: N N, N ( )(M ) (4) (43) and d/dn=0 is satisfied if N pt ( ) (M ). (44) Nte that if =0, then (44) is reduced t Npt (M) 0 which gives the same result as btained in [5]. The design strategy accrding t the abve analysis will be discussed in details in Sectin 0. (45) 5 Analysis f Dual-Branch Linear Charge Pumps Dual-branch and multi-phase charge pumps result in smaller utput vltage ripples than single-branch cunterparts, and in-depth analysis is needed t btain the design equatins [3, 6]. Fig. 5 shws the schematic f a dual-branch (N+)X linear charge pump, with the tw branches perating in cmplementary phases. Only the charging and discharging phases f Branch A are labeled. Due t symmetry, we assign 0

12 C Ak =C Bk =C k, but we still use C Ak and C Bk when clarity in descriptin is needed. Negative-plate parasitic capacitrs are nt shwn. Fig. 6 shws the timing diagrams f C N and (t), as thse f C and C k are the same as the single-branch case. Branch B C C Ck Ck CN CN ck cn dn (t) C C C k Ck C N CN CL I dk ck dn cn Branch A Fig. 5. Dual-branch (N+)X linear charge pump., CN (a) CN dn N cn ( C N) (C N) (N ) (t) t dn dn cn dn (b) t Fig. 6. Timing diagram f dual-branch LQP f (a) C N ; and (b) (t). The analysis fllws clsely that f the single-branch case and is skipped. The key results f, and the average utput vltage =( + )/ are shwn belw: N N IT/ IT/ k k N, ( )C ( )C C L N N I k k (46) T/ ()C, (47) N N IT/ IT/4 k k N. ( )C ( )C C L (48)

13 Nte again that is independent f C L. Fr C L >>C k, the average utput vltage is equal t, and t maximize and minimize the ttal capacitance C T it is clear that all C k shuld be set equal: C C... CN C II, (49) where the subscript II is fr the dual-branch case. The utput vltage with C L >>C k is N NIT/ ()C, (50) II and the utput vltage ripple by restating a finite C L (>>C k ) is IT. C L As in Sectin 3, if we assign the reductin factr II as IT then the vltage cnversin rati is IT II C II (C/), NN / MII Cmpare (50) and (9), if we assign II. (5) (5) (53) CII C/ (54) then bth single-branch and dual-branch charge pumps have the same utput vltage fr the same ttal capacitance C T (nte that NC II =NC fr the dual-branch LQP). The nly difference between the tw LQPs is the utput vltage ripple, with the dualbranch LQP being nly half f that f the single-branch case. The equatin fr efficiency f the dual-branch LQP is the same as (35) by replacing with II /, and therefre, all equatins (36) thrugh (45) apply t bth the single-branch and dualbranch linear charge pumps. 6 Cmparisn f Single- and Dual-Branch Linear Charge Pumps We validate the analyses f single- and dual-branch linear charge pumps fr the fllwing aspects. (A) Perfrm time-dmain Cadence simulatin t verify equatins (5, 3-5) f the single-branch LQP, and equatins (46-48) f the dual-branch LQP. (B) Perfrm Cadence simulatins n utput vltage and efficiency f (A) and cmpare with theretical results. (C) Perfrm Matlab simulatin f pt and max fr different N, and. Cadence simulatins will be perfrmed and cmpared with theretical values. Fr all Cadence simulatins presented in this paper, the switches

14 are realized by nearly ideal switches that have very lw n-resistance f 0.Ω and very large ff-resistance f TΩ. Simulatins are perfrmed using relative tlerance f 0 6, abslute tlerance in current f pa, and abslute tlerance in vltage f µ. (A) Fr time-dmain simulatin, we design single-branch and dual-branch 8X LQPs (N=7) with the fllwing specificatin: the input vltage is, the lad current I is 0μA, and the switching frequency f s is 0MHz. The psitive-plate and negativeplate parameters are =0.0 and =0.05, respectively. The nn-verlapping dead time is set t be ns. Fr the single-branch 8X LQP, we set C=0pF and C L =5pF. Fig. 7(a) shws the simulatin result f (t) n which, and 3 are marked. Fr the dual-branch 8X LQP, we set C II =0pF and C L =5pF. Fig. 7(b) shws the simulatin result f (t) n which and are marked. Table tabulates the analysis and simulatin results alng with the percentage errrs. The errrs fr i 's are due t the switch dead time in ur simulatin and are all smaller than 0.03%. Fig. 7. Time-dmain simulatin f (a) single-branch LQP; and (b) dual-branch LQP. (B) The reductin factrs f the charge pumps in (A) are =0.05 and II =0., respectively, and are nt the ptimal values. Efficiency cmputatins are perfrmed fr C L =5pF and C L =nf (such that it can be regarded as infinite), and bth are nly 3

15 arund 46.5% (Table ). Next, fr the single-branch charge pump with N=7, =0.0, =0.05 and C L =nf, pt is cmputed frm (39) t be and max is 65.7%. Cadence simulatin gives an almst identical efficiency f 65.9%. The results are again tabulated in Table. (C) We wuld like t find ut the general range f pt and the crrespnding max. Fig. 8 shws pt and max vs, and N. The negative-plate parasitic parameter takes the value f 0.00, 0.05 and 0.0, while the psitive-plate parasitic parameter ranges frm 0.00 t 0.0 fr N= (vltage dubler), N=3 and N=7. Cadence simulatins are als perfrmed fr =0 t =0.0 at an interval f 0.0. The theretical curves match very well with Cadence simulatins. Table. Output vltages and utput vltage ripples f LQPs. Analysis Simulatin % errr Single-branch % % % 3.m 3.5m.9% Dual-branch % % 4.m 4.7m 3.5% Table. Output vltages and efficiencies f LQPs. Analysis Simulatin % errr Single-branch with =0.05, C=0pF, C L =5pF % 46.47% 46.49% 0.043% Single-branch with =0.05, C=0pF, C L =nf % 46.48% 46.5% 0.065% Dual-branch with II =0., C II =0pF, C L =5pF % 46.5% 46.54% 0.043% Dual-branch with II =0., C II =0pF, C L =nf % 46.48% 46.50% 0.043% Single-branch with pt =0.987, C=5.03pF, C L =nf % 65.7% 65.9% 0.03% 4

16 (a) (b) (c) Fig. 8. pt and max fr (a) N=; (b) N=3; and (c) N=7. 5

17 7 Analysis f Fibnacci Charge Pumps Fig. 9 shws a single-branch 8X Fibnacci charge pump, leaving ut all parasitic capacitrs fr a clear expsitin f the tplgy [9]. It uses nly fur flying capacitrs t achieve a vltage cnversin rati f 8. An immediate questin is: will the ttal capacitance be smaller than that f the 8X LQP fr the same utput vltage? In fact, the same questin can be asked f the 8X expnential charge pump t be discussed in Sectin 8. Fr a cmplete analysis with C L 0 including parasitic capacitrs, it can be shwn, by fllwing the prcedure as discussed in Sectin 3, that f bth single- and dual-branch charge pumps are independent f C L, and as C L,. Therefre, we assume C L = t arrive at a simpler prcedure as discussed belw. C C C C3 4 C I Fig. 9. Single-branch 8X Fibnacci charge pump. Fig. 0 shws the cnnectins f the switches, the flying capacitrs and their parasitic capacitrs f the 8X FQP in bth = and =. As discussed in Sectin 3, fr any flying capacitr C k, the charging phase is ck and the discharging phase is dk, and the capacitr vltage when fully discharged in dk = is designated as k. Clearly, in c = =, C is charged t, and in d = =, C is discharged t, but then d is the same as c, and C is charged t +. The same mechanism prpagates dwn the stages, and it als applies t the parasitic capacitrs. Let us cnsider the case with ==0 first. It is straightfrward t wrk frm the last stage back t the first stage. In the charging phase f C 4 (i.e., =), C 4 is charged t + + 3, while C is discharged by I fr the duratin f T/. In the discharging phase, C 4 is stacked n tp f and C, and C 4 supprts I fr T/, and C 4 is eventually discharged t 4. Emply QBL, we have C( 4 ) 3 C 4 4 IT. (55) Nte that fr C L =C =, the utput vltage will never change, and we need t accunt fr the lad current cnsumptin as discussed abve s that the result wuld be crrect. Next, fr charge transfer at d ( ), we have C( 3 ) C 4 4 C 3 3C( 4 ) 3, (56) and it can be simplified using the result f (55) t give C( 3 ) C 3 3 IT. (57) 6

18 (a) b =++ 4 a 4 C4 C4 C C C3 C3 C4 C C C C I (b) d c 3 C 3 C 3 C4 C4 C C C C C 3 C C I Fig. 0. Capacitr cnnectins f 8X FQP in (a) =; and (b) =. The charge transfer at a ( ) is nt as straightfrward, as it is the negative plate f C 4 that is cnnected t a. Taking this int cnsideratin and we btain C( ) C 3 3C( 4 ) 3 C C( 3 ) C 4 4. (58) Using bth (55) and (57) gives C( ) C IT. (59) In a similar fashin, the charge transfer at c ( ) gives C C 3IT. (60) Backward substitutin can then be perfrmed, and we btain 3I T, C (6) 7

19 3I T I T C C, 3IT IT IT 33, C C C Finally, = + + 4, and we have 3IT IT IT IT 4 5. C C C C 3 9IT 4IT IT IT 8. C C C C 3 The analysis f a higher rder FQP is similar, and ne can easily infer the result frm bserving the abve trend f k. Frm (65), it is bvius that the capacitrs shuld nt have the same value: the /C term has a weight f 9, the /C term has a weight f 4, and the /C 3 and /C 4 terms have weights f. Qualitatively, C shuld be larger t minimize the reductin due t a larger weight. Quantitatively, t minimize the ttal capacitance, the prcedure described in [, 3] shuld be fllwed, and the ptimal assignment is C C (6) (63) (64) (65) 3C, (66) C, (67) C3 C4 C, (68) CT CCC3C4 7C. (69) Using the abve ptimal assignment fr the ideal case, we have 7I T C 8. This is the same result as btained fr the single-branch 8X LQP with =0 (9). Therefre, fr n-chip implementatin, there is n advantage in saving capacitr area by using FQP instead f LQP. This is a very imprtant cnclusin f this research. Nevertheless, we cntinue t wrk ut the vltage cnversin rati in the presence f C k and C k, as the result wuld be useful fr ff-chip implementatin. In analyzing FQP including C k and C k, we prpse a first iteratin apprximatin (FIA) analysis. This prcedure can wrk with bth C k and C k tgether, but fr the purpse f illustratin, let us cnsider nly C k first (=0). Again, we cnsider the charge transfer at b ( ) and btain (70) 8

20 ( )C 4( 3) C44C 4( 4) IT. (7) Eq. (7) can be rearranged t read C( 4 ) 3 C 4 4C( 4 43) IT. (7) Fllwing the same prcedure and rearranging the crrespnding equatins as in (7), we have C( 3 ) C 3 3C( 3 3) IT, (73) C( ) C C( ) C( 4 43) IT, (74) C C C C( 3 3) C( 4 43) 3IT. (75) The difficulty f slving (7) t (75) lies with the parasitic terms C k. Cnsider (7). If is very small, the term with C 4 shuld be much smaller than the terms with C 4 nly. If there is an errr in the multiplicand f C 4 (that is, ), the errr wuld be f secnd rder and can be neglected. Nw, fr,, <<, we have 4 5, 3 3, and. Using this apprximatin we have C 4(43) 3 C4. (76) Perfrming the same apprximatin fr (73), (74) and (75) by als including 0 we btain 8 5 I T 3 3 C, (77) 3 9 I T 6 6 C, I T C 3, I T C 4, (78) (79) (80) I T C (FQP). This utput vltage is much lwer than that f the LQP (9): 8 7 7I T C (LQP). Clearly, linear charge pumps are preferred t Fibnacci charge pumps fr n-chip implementatin. (8) (8) 9

21 8 Analysis f Expnential Charge Pumps Fig. shws the dual-branch expnential charge pump that uses N flying capacitrs and ne lad capacitr [0, ]. Nte that with N flying capacitrs, a N X charge pump can nly be realized using a multi-phase clck [7, 8]. The analysis is left as a challenge t the readers and nly the key results are presented belw. Fr the ptimal capacitr assignment with ==0, we have CA CB 4CII, (83) CA CB CII, (84) C3A C3B CII, (85) CT (CACAC 3A) 4C. (86) II B C CB CB C3B C C3 C A CA C 3A C I A Fig.. Dual-branch 8X expnential charge pump. Fr, 0, we use first iteratin apprximatin and the final capacitr vltages k and are 4 3 IT, CII 8 5 IT, CII I T 3, CII (87) (88) (89) 0

22 I T (EQP). CII 90) This result is t be cmpared with (8) and (8) fr ==0: with C II =C/, all LQP, FQP and EQP have the same utput vltage using the same ttal capacitance. Fr the same 0 and/r 0, LQP achieves the highest vltage cnversin rati, and EQP achieves the lwest vltage cnversin rati. 9 Cmparisn f LQPs, FQPs and EQPs Fr the purpse f cmparisn, we design single-branch 8X LQP and 8X FQP, and dual-branch 8X LPQ, 8X FQP and 8X EQP with the fllwing specificatin: the input vltage is, the lad current I is 0μA, and the switching frequency f s is 0MHz. Ideal switches are used and the nn-verlapping dead time is set t be ns. The single-branch unit capacitr C (B) =C is 0pF, such that the reductin factr = I T/(C ) is 0.05, and the ttal capacitance f all charge pumps are C T =40pF. The lad capacitr C L is nf t fulfill the assumptin f C L >>C k. Due t limited space, nly the time-dmain simulatin f the single-branch 8X FQP is shwn. Fig. shws the psitive-plate vltages f C k and the utput vltage (t) fr the case with =0.05 and =0.04. As C L, (t) is nt a cnstant; but the mid-vltage f (t) is as shwn. Fig.. Simulated wavefrms f single-branch 8X FQP.

23 The simulated values are t be cmpared with the cmputed values using FIA analysis. Cnsider the psitive-plate vltage f C 4. The maximum value (in the discharging phase) is 6.979, and the minimum value (in the charging phase) is.677. Hence, 4(sim) = = The curves are a little bit difficult t read due t verlapping. Eq. (8) gives 4(cmp) = 4.36, and the errr is.6%. The cmputed and simulated values are cmpiled in Table 3. Nte that in FIA analysis, k in the C k terms are ver-estimated, and they lead t cnsistently under estimatin f the cmputed k terms. Fig. 3 shws the time-dmain simulatin f the dual-branch 8X FQP with C (B) = C II =C/=0pF, such that C T =40pF. Except fr the reductin in utput vltage ripple as discussed in [3], the crrespnding vltages f the dual-branch FQP are the same as the single-branch cunterpart, verifying ur cnclusin that they shuld have the same perfrmance when C L =. The secnd set f simulatins is t plt the utput vltage vs and vs individually. Here, all three charge pumps are dual-branch charge pumps. Optimal capacitance assignment fr the respective ideal case is used. Hence, fr the 8X LQP, C ka = C kb = C = 0pF, where the subscript "A" is fr the A-branch, and "B" fr the B- branch. Fr the 8X FQP, C A :C A :C 3A :C 4A = C B :C B :C 3B :C 4B = 3C:C:C:C; and fr the 8X EQP, C A :C A :C 3A = C B :C B :C 3B = 4C:C:C. Fr all three charge pumps, the ttal n-chip capacitance C T is 40pF, and C L = nf. Fig. 4 shws the simulatin results f vs and vs fr all three charge pumps, with bth and changed frm 0 t 0.. The calculated results match the simulated results quite well when and are small, as shwn in Table 3: fr =0.05 and =0.04, the errr is nly -.4%. The differences becme larger fr larger and. T enhance the accuracy in cmputatin, a mre cmplicated secnd iteratin apprximatin has t be used. Table 3. Cmputed and Simulated values f 8X FQP. Cmputed Simulated Errr = % = % = % = % %

24 Fig. 3. Simulated wavefrms f dual branch 8X FQP. (a) 3

25 (b) (c) Fig. 4. vs and vs fr (a) LQP; (b) FQP; and (c) EQP. 0 Design Strategy f Optimal Linear Charge Pumps As the linear charge pump is the mst efficient n-chip implementatin, it is wrthwhile t devise a design strategy in ptimizing the efficiency fr a specified utput vltage. Table 4 summarizes the design strategies prpsed in [5] and [6], alng with ur wn prpsal. The design strategy f [5] has been very successful in ptimizing the efficiencies f LQPs and wrth repeating in sme details. In [5], instead f wrking directly n, the input current I in cnsisting f the currents 4

26 flwing int the negative-plate parasitic capacitrs C k were used t find N pt that minimizes I in, while C k were left ut. In assuming =0, N pt is cmputed using (45). The input current I in with =0 is derived as [5] N I in N 0 N M I. Then the flying capacitr C is cmputed using () and (4), and can be btained frm (35), all with =0 (Table 4). The drawback f [5] is in neglecting C k. In present-day technlgy, an MIM (metal-insulatr-metal) capacitr has a capacitance f ff/m. The bttm-plate (usually implemented as negative-plate) parasitic parameter is =0.0~0.05, while the tp-plate (usually implemented as psitive-plate) parasitic parameter is 0.fF/m f perimeter. If the unit capacitr is.6pf, it culd be realized by a 40m40m MIM capacitr, and =0.0. If the unit capacitr is 400fF, then increases t 0.0. Mrever, when switches r dides are taken int cnsideratin, aitinal parasitic capacitrs will be aed t bth plates. Therefre, the assumptin that C k are negligible may nt be justified. Table 4. Cmparisn f analyses and ptimizatin methds f LQPs. (9) [5] [6] This wrk = 0, 0 0, 0 = ++ N pt (M ) N is given a priri (+) (M ) = IT C NM C is given a priri N ( )M N N (N+) NIT C N NIT ( )C N NIT ( )C M N N M (N ) N N ( )M N( ) N An attempted t perfect the analysis f [5] by including the input currents f C k was prpsed in [6]. Ref. [6] did nt shw hw N is cmputed, and it is reasnable t use N pt and as cmputed in [5]. By using the frmula fr due t [] that includes C k, was accurately estimated (Table 4). Hwever, all C k were assumed t be charged in bth phases (that gives the factr N+ shwn in Table 4) and was thus nt accurate enugh. Mrever, the parameter C/D in [6] was nt derived crrectly. 5

27 Our prpsed design strategy cmplements that f [5] by crrectly accunting fr the effects f C k. By gruping the denminatr f (34) as I in T, the input current I in is btained as ( )N I Iin N. N ( )M The dependence f in (9) cannt be btained very easily thrugh ad hc aitin f C k terms t (9), but it can be handled crrectly thrugh using the systematic applicatin f the charge balance law as shwn in Sectin 4. It is bvius that minimizing I in f (9) is the same as minimizing f (43). Fllwing the steps in [5], N pt is first cmputed using (44) that crrectly accunts fr C k (Table 4). Frm Fig. 4, it is clear that max decreases as N increases fr the same and. Qualitatively, using a larger N t realize the same utput cnversin rati M means that mre C k have t be used, and there will be mre lsses frm C k and C k. Therefre, a smaller N is preferred if the realized is acceptable fr that applicatin. After N is determined, ne then has tw chices in cmputing C: the first ne is t cmpute C using (39), such that maximum efficiency is guaranteed, but the realized utput vltage may deviate frm the required ; and the secnd ne is t cmpute C using (4) such that = M as required. Here, we prpse that we shuld cmpute C using (4) whatsever t make sure that the realized utput vltage is the same as the specificatin, while the degradatin in efficiency is t small t be f cncern. Our argument is as fllw. When is nt equal t pt, the efficiency can be btained frm max using Taylr's series expansin: d d max d d pt The maximum efficiency is btained by finding the cnditin fr d/d=0; hence, the first rder term is zer. Fr the secnd derivative, it can easily be shwn that giving d d pt pt pt.. max. pt In general, the cefficient f the (/ pt ) term is smaller than unity. Fr / pt = 0. (0% deviate frm the ptimal value), the decrease in efficiency is nly less than %. Hence, we cnclude that C shuld be cmputed using (4). (9) (93) (94) (95) 6

28 As an example, let us design a charge pump that has an average utput vltage f 5 (M=5) with the fllwing specificatins: the input vltage is, the lad current I is 0μA, and the switching frequency f s is 0MHz. The psitive-plate and negative-plate parameters are =0.0 and =0.06, respectively. The lad capacitr is C L =nf. Fr the design accrding t [5], N pt and are cmputed using the crrespnding frmulae in Table 4. N pt is cmputed t be 4.95, and naturally N is taken as 5. As is assumed t be zer while actually it is 0.0, bth the utput vltage and the efficiency are verestimated, as the simulatin results in Table 5 shw. Fr the design accrding t [6], N pt and are btained as in [5]. As the accurate frmula fr is used, the theretical value (4.9604) is very clse t the simulated value (4.960). Mrever, as the effects f C k are partially accunted fr, the theretical efficiency (0.659) is clser t the simulated value (0.6466) than that f [5] (0.6667). Fr ur prpsed design, N pt is cmputed using (44), and the value is We chse N=5 instead f N=6 because it is clser t 5.08, and we can use (4) t cmpute that still satisfies M=5. The reductin factr is cmputed t be 0.9. Bth the theretical and the simulatin values are =5.00. Fr cmputing the efficiency, the theretical value (0.6434) is als very clse t the simulated value (0.6436). T maximize the efficiency, we may re-cmpute t btain pt =0.34, and the crrespnding max is Frm (95), the cefficient f (/ pt ) is 0.65, with = = 0.04, and / pt =0.. The efficiency is then = = Tw cnclusins can be drawn: (i) the estimated using (95) is less than % frm the cmputed value; and (ii) even with a 0% deviatin frm pt, the resultant efficiency is still very clse t max. A plt f versus in the vicinity f pt, alng with Cadence simulatins, is shwn in Fig. 5. Table 5. Cmparisn f analyses with simulatins. Analysis Simulatin % errr [5] with N=5, C=5pF % 66.67% 64.47% 3.4% [6] with N=5, C=5pF % 65.9% 64.47%.% This wrk with N=5, C=5.pF % 64.34% 64.36% 0.03% This wrk with N=5, C=4.7pF % 64.49% 64.5% 0.03% 7

29 Fig. 5. Simulated vs in the vicinity f pt with =0.0. Cnclusins In this research, charge balance law is systematically emplyed t analyze charge pumps with ideal switches and finite psitive-plate and negative-plate parasitic capacitrs. Equatins fr utput vltages, utput vltage ripples and efficiencies are derived fr single-branch and dual-branch linear charge pumps. In cmputing (t), a finite lad capacitr C L is used, and the result is extended t C L =. We bserve that C L determines the utput vltage ripple, but has a negligible effect n the average utput vltage. Frm exact derivatins, it is fund that is independent f C L fr bth single-branch and dual-branch charge pumps, and can be used t simplify analysis fr C L =. Interplatin culd then be perfrmed t btain and 3 fr single-branch charge pumps, and fr dual-branch charge pumps. Besides linear charge pumps, Fibnacci and expnential charge pumps are analyzed. The exact analysis f FQPs and EQPs are t cmplex and n insight culd be btained. Instead, we prpsed a first iteratin apprximatin analysis t btain reasnably accurate results. Our findings are as fllws. () If C L =, the perfrmance f single-branch and dual-branch charge pumps are the same, and the single-branch LQP is preferred due t its lwer cmplexity. () If parasitic capacitrs are negligible, LQP, FQP and EQP give the same ttal capacitance fr the same utput vltage. (3) In the presence f parasitic capacitrs, LQP is the best tplgy that culd achieve the highest utput vltage. Efficiency ptimizatin f LQPs is thrugh first cmputing the ptimal number f stages, fllwed by finding the reductin factr that achieves the required average utput vltage. Using pt t maximize the efficiency may nt be necessary as the sensitivity f w.r.t. is very lw. Frm the btained we may then chse t 8

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