D Series Power MOSFET

Transcription

1 D Series Power MOSFET SiHUND PRODUCT SUMMRY (V) at T J max. R DS(on) max. () at 2 C V GS = V.2 Q g max. (nc) 2 Q gs (nc) 2 Q gd (nc) Configuration Single D IPK (TO2) G D S ORDERING INFORMTION Package Lead (Pb)free Lead (Pb)free and Halogenfree G D S NChannel MOSFET FETURES Optimal design Low area specific onresistance Low input capacitance (C iss ) Reduced capacitive switching losses High body diode ruggedness vailable valanche energy rated (UIS) Optimal efficiency and operation Low cost Simple gate drive circuitry Low figureofmerit (FOM): R on x Q g Fast switching Material categorization: for definitions of compliance please see PPLICTIONS Consumer electronics Displays (LCD or plasma TV) Server and telecom power supplies SMPS Industrial Welding Induction heating Motor drives Battery chargers IPK (TO2) SiHUNDE SiHUNDGE BSOLUTE MXIMUM RTINGS (T C = 2 C, unless otherwise noted) PRMETER SYMBOL LIMIT UNIT DrainSource Voltage GateSource Voltage ± V V GS GateSource Voltage C (f > Hz) Continuous Drain Current (T J = C) V GS at V T C = 2 C. I D T C = C.9 Pulsed Drain Current a I DM. Linear Derating Factor.6 W/ C Single Pulse valanche Energy b E S. mj Maximum Power Dissipation P D 69 W Operating Junction and Storage Temperature Range T J, T stg to C DrainSource Voltage Slope T J = 2 C 2 dv/dt Reverse Diode dv/dt d.22 V/ns Soldering Recommendations (Peak Temperature) c for s C Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. V DD = V, starting T J = 2 C, L = 2. mh, R g = 2, I S =. c..6 mm from case. d. I SD I D, starting T J = 2 C. S6Rev. C, 2Jan6 Document Number: 99 RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T

2 SiHUND THERML RESISTNCE RTINGS PRMETER SYMBOL TYP. MX. UNIT Maximum Junctiontombient R thj 62 Maximum JunctiontoCase (Drain) R thjc.8 C/W SPECIFICTIONS (T J = 2 C, unless otherwise noted) PRMETER SYMBOL TEST CONDITIONS MIN. TYP. MX. UNIT Static DrainSource Breakdown Voltage V GS = V, I D = 2 μ V Temperature Coefficient /T J Reference to 2 C, I D = 2 μ.6 V/ C GateSource Threshold Voltage (N) V GS(th) = V GS, I D = 2 μ V GateSource Leakage I GSS V GS = ± V ± n = V, V GS = V Zero Gate Voltage Drain Current I DSS = V, V GS = V, T J = 2 C μ DrainSource OnState Resistance R DS(on) V GS = V I D = Forward Transconductance a g fs = 8 V, I D =. S Dynamic Input Capacitance C iss VGS = V, 7 Output Capacitance C oss = V, 2 Reverse Transfer Capacitance C rss f = MHz Effective Output Capacitance, Energy pf Related b C o(er) 2 = V to V, V GS = V Effective Output Capacitance, Time Related c C o(tr) 26 Total Gate Charge Q g 6 2 GateSource Charge Q gs V GS = V I D =., = V 2 nc GateDrain Charge Q gd TurnOn Delay Time t d(on) 2 2 Rise Time t r V DD = V, I D =. 9 8 TurnOff Delay Time t d(off) R g = 9., V GS = V 22 ns Fall Time t f 26 Gate Input Resistance R g f = MHz, open drain. DrainSource Body Diode Characteristics Continuous SourceDrain Diode Current I MOSFET symbol D S showing the G integral reverse Pulsed Diode Forward Current I SM p n junction diode 2 S Diode Forward Voltage V SD T J = 2 C, I S =., V GS = V.2 V Reverse Recovery Time t rr 29 ns Reverse Recovery Charge Q rr T J = 2 C, I F = I S =., di/dt = /μs, V R = 2 V.7 μc Reverse Recovery Current I RRM Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. C oss(er) is a fixed capacitance that gives the same energy as C oss while is rising from % to 8 % S. c. C oss(tr) is a fixed capacitance that gives the same charging time as C oss while is rising from % to 8 % S. S6Rev. C, 2Jan6 2 Document Number: 99 RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T

3 SiHUND TYPICL CHRCTERISTICS (2 C, unless otherwise noted) I D, DraintoSource Current () 6 2 TOP V V V 2 V V V 9 V T J = 2 C 8 V 7 V 6 V 2 2, DraintoSource Voltage (V) R DS(on), DraintoSource On Resistance (Normalized) I D = V GS = V T J, Junction Temperature ( C) Fig. Typical Output Characteristics Fig. Normalized OnResistance vs. Temperature I D, DraintoSource Current () 2 TOP V V V 2 V V V 9. V 8. V 7. V 6. V. V T J = C Capacitance (pf) C iss C oss C rss V GS = V, f = MHz C iss = C gs C gd, C ds Shorted C rss = C gd C oss = C ds C gd 2 2, DraintoSource Voltage (V) Fig. 2 Typical Output Characteristics 2, DraintoSource Voltage (V) Fig. Typical Capacitance vs. DraintoSource Voltage I D, DraintoSource Current () 6 2 T J = C T J = 2 C V GS, GatetoSource Voltage (V) = V = 2 V = V 2 2 V GS, GatetoSource Voltage (V) Q g, Total Gate Charge (nc) Fig. Typical Transfer Characteristics Fig. 6 Typical Gate Charge vs. GatetoSource Voltage S6Rev. C, 2Jan6 Document Number: 99 RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T

4 SiHUND. I SD, Reverse Drain Current (). T J = C T J = 2 C V GS = V I D, Drain Current () V SD, SourceDrain Voltage (V) T J, Case Temperature ( C) Fig. 7 Typical SourceDrain Diode Forward Voltage Fig. 9 Maximum Drain Current vs. Case Temperature I D, Drain Current ().. Operation in this area limited by R DS(on) Limited by R DS(on) * T C = 2 C T J = C Single Pulse BVDSS Limited μs ms ms, DraintoSource Voltage (V) * V GS > minimum V GS at which R DS(on) is specified, DraintoSource Breakdown Voltage (V) T J, Junction Temperature ( C) Fig. 8 Maximum Safe Operating rea Fig. Typical DraintoSource Voltage vs. Temperature Normalized Effective Transient Thermal Impedance. Duty Cycle = Single Pulse..... Pulse Time (s) Fig. Normalized Thermal Transient Impedance, JunctiontoCase S6Rev. C, 2Jan6 Document Number: 99 RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T

5 SiHUND R D V GS D.U.T. V Q G R G V DD Q GS Q GD V Pulse width µs Duty factor. % Fig. 2 Switching Time Test Circuit V G Charge Fig. 6 Basic Gate Charge Waveform 9 % Current regulator Same type as D.U.T. kω 2 V.2 µf. µf % V GS t d(on) t r t d(off) t f D.U.T. V DS V GS Fig. Switching Time Waveforms m I G I D Current sampling resistors L Fig. 7 Gate Charge Test Circuit Vary t p to obtain required I S R G I S D.U.T V DD V t p. Ω Fig. Unclamped Inductive Test Circuit t p V DD I S Fig. Unclamped Inductive Waveforms S6Rev. C, 2Jan6 Document Number: 99 RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T

6 SiHUND Peak Diode Recovery dv/dt Test Circuit D.U.T. Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer R g dv/dt controlled by R g Driver same type as D.U.T. I SD controlled by duty factor D D.U.T. device under test V DD Driver gate drive P.W. Period D = P.W. Period V GS = V a D.U.T. l SD waveform Reverse recovery current Body diode forward current di/dt D.U.T. waveform Diode recovery dv/dt V DD Reapplied voltage Inductor current Body diode forward drop Ripple % I SD Note a. V GS = V for logic level devices Fig. 8 For NChannel maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see S6Rev. C, 2Jan6 6 Document Number: 99 RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T

7 Package Information TO2 (HIGH VOLTGE) E Thermal PD D (Datum ) L L θ2 E b C C..2 M C B L2 D B θ c2 C Seating plane B B L View x b2 x b 2 x e..2 M C B c Lead tip Plating (c) b, b Base metal c (b, b2) Section B B and C C MILLIMETERS INCHES MILLIMETERS INCHES DIM. MIN. MX. MIN. MX. DIM. MIN. MX. MIN. MX D E b E.2.7 b e 2.29 BSC 2.29 BSC b L b L b L c L c θ ' ' ' ' c θ2 2' ' 2' ' D ECN: S82Rev., Sep8 DWG: 968 Notes. Dimensioning and tolerancing per SME Y.M Dimension are shown in inches and millimeters.. Dimension D and E do not include mold flash. Mold flash shall not exceed. mm (.") per side. These dimensions are measured at the outermost extremes of the plastic body.. Thermal pad contour optional with dimensions b, L2, E and D.. Lead dimension uncontrolled in L. 6. Dimension b, b and c apply to base metal only. 7. Outline conforms to JEDEC outline TO2. Document Number: Revision: Sep8

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