Embedded MCSoC Architecture and Period-Peak Detection (PPD) Algorithm for ECG/EKG Processing
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1 The 19 th Intelligent System Symposium (FAN2009), Aizu-Wakamatsu, Sep.17-18, 2009 Embedded MCSoC Architecture and Period-Peak Detection (PPD) Algorithm for ECG/EKG Processing Yasuyoshi Haga, Abderazek Ben Abdallah, Kenichi Kuroda School of Computer Science and Engineering, The University of Aizu, Japan Sep. 17, 2009 FAN2009 1
2 Outline Background Our proposal Period-Peak Detection Algorithm System architecture Preliminary Evaluation Conclusion Sep. 17, 2009 FAN2009 2
3 Background (1/4) Heart period is important in medical care. Heart period is calculated from electrocardiogram (ECG/EKG) signal. voltage mv R Period R T T P U P U Q Q time s S S Sep. 17, 2009 FAN2009 3
4 Background (2/4) Heart period detection Heart period mv R R R Sep. 17, 2009 FAN s
5 Background (3/4) Problems of period detection R-R Interval False Interval R R Faulty analysis R-T Interval False Interval R mv True Interval True Interval T Sep. 17, 2009 FAN t
6 Background (4/4) ECG/EKG is an essential tool in heart medicine. Problems Long time for analysis Analyze huge amount of data Insufficient accuracy Noisy and complicate waveform Large and heavy systems Targets Real time analysis High accuracy Portability Sep. 17, 2009 FAN2009 6
7 Our proposal (1/2) Real time analysis High accuracy Portability Hardware Implementation MultiCore System-on-a-Chip architecture (MCSoC) Sep. 17, 2009 FAN2009 7
8 Our proposal (2/2) MCSoC part ADC 1 ADC 12 FIR 1 FIR 12 SDRAM MCSoC ECG Analysis Heart period Peaks Waveforms A typical 12 leads Signal reading Filtering Analysis Display Sep. 17, 2009 FAN2009 8
9 Background Our proposal Contents Period-Peak Detection Algorithm System architecture Preliminary Evaluation Conclusion Sep. 17, 2009 FAN2009 9
10 Filter (1/2) ADC 1 ADC 12 FIR 1 FIR 12 SDRAM MCSoC ECG Analysis Heart period Peaks Waveforms A typical 12 leads Signal reading Filtering Analysis Display Sep. 17, 2009 FAN
11 Filter (2/2) Filter is used for noise reduction. Muscle noise T-wave interference The filter module is Bandpass filter Based on digital FIR filter N y [ n ] = a i x n i i = 0 n] : current a x i n : filter's coefficients : current filter N : filter order output or previous filter inputs Sep. 17, 2009 FAN
12 Analysis algorithm ADC 1 ADC 12 FIR 1 FIR 12 SDRAM MCSoC ECG Analysis Heart period Peaks Waveforms A typical 12 leads Signal reading Filtering Analysis Display Sep. 17, 2009 FAN
13 Period-Peak Detection Algorithm (1/4) This algorithm is based on autocorrelation function (ACF). Reading data Derivation Autocorrelation Find interval Peak detection Calculate threshold Find peaks Store results Period detection Sep. 17, 2009 FAN
14 Period-Peak Detection Algorithm (2/4) -Derivation- Emphasis of the signal peaks Implementation with simple operations (-) y t ( t) n ( n + 1] + 1) n] n = n + 1] n] n]: current sampling data (filtered orignal ECG/EKG signal) t, n : current time (step) Sep. 17, 2009 FAN
15 Period-Peak Detection Algorithm (3/4) ACF Periodicity analysis of signals R y [ k ] = n= n= n] n k ] R y : the autocorrelation function n]: the ECG/EKG filtered signal k : the number of lags of the autocorrelation Sep. 17, 2009 FAN
16 Period-Peak Detection Algorithm (4/4) ACF Modification for MCSoC implementation N R y [ L] = n= 0 n] n L] R y : the autocorrelation function n]: the ECG/EKG filtered signal N : the number of times needed for the calculations to get the period Sep. 17, 2009 FAN
17 Calculation process of ACF (1/6) Assumption -The ECG/EKG signals are 9 samples. Time t Signal n] R y [ L] 8 = n= 0 n] When n L < n 0, y is 0 L] Sep. 17, 2009 FAN
18 Calculation process of ACF (2/6) 8 = R [0] n] n 0] = n] y n= 0 8 n= 0 n] Signal Signal n] n] Calculation R [ 0] = y 15 Sep. 17, 2009 FAN
19 Calculation process of ACF (3/6) R y [1] 8 = n= 0 n] n 1] n] n] Zero (n-l < 0) Calculation No calculation (n > 8) R [ 1] = y 6 Sep. 17, 2009 FAN
20 Calculation process of ACF (4/6) R y [2] 8 = n= 0 n] n 2] n] n] Zero (n-l < 0) Calculation No calculation (n > 8) R [ 2] = y 4 Sep. 17, 2009 FAN
21 Calculation process of ACF (5/6) R y [3] 8 = n= 0 n] n 3] n] n] Zero (n-l < 0) Calculation No calculation (n > 8) R [ 3] = y 10 Sep. 17, 2009 FAN
22 Calculation process of ACF (6/6) Results n] L R y Ry Sep. 17, 2009 FAN L
23 Calculation process of ACF (6/6) Results n] L R y Period Period Ry Sep. 17, 2009 FAN L
![Calculation process of ACF (6/6) Results n]](/docs-images/91/105190842/images/24-2.jpg "0 1 2 0 1 2 0 1 2 L R y 0 1 2 3 4 5 6 7 8 15")
24 Calculation process of ACF (6/6) Results n] L R y Period Period Ry Every 3 samples are periodic Sep. 17, 2009 FAN L
25 Calculation process of peaks (1/3) Period detection Calculate threshold Find max peak Find peaks Configure threshold Store results Sep. 17, 2009 FAN
26 Calculation process of peaks (2/3) Step 1 Calculate threshold Period n] Max peak = 2 Threshold = 1 Sep. 17, 2009 FAN
27 Calculation process of peaks (2/3) Step 1 Calculate threshold Period n] Max peak = 2 Threshold = 1 50% Sep. 17, 2009 FAN
28 Calculation process of peaks (3/3) Step 2 Find the time slots and values of peaks Period n] Over the threshold Max peak = 2 Threshold = 1 Sep. 17, 2009 FAN
29 Calculation process of peaks (3/3) Step 2 Find the time slots and values of peaks Period n] Peaks Max peak = 2 Threshold = 1 Sep. 17, 2009 FAN
30 Background Our proposal Contents Period-Peak Detection Algorithm System architecture Preliminary Evaluation Conclusion Sep. 17, 2009 FAN
31 Processing phase Phase 1 Phase 2 Phase 3 Phase 4 ADC 1 ADC 12 FIR 1 FIR 12 SDRAM MCSoC ECG Analysis Heart period Peaks Waveforms A typical 12 leads Signal reading Filtering Analysis Display Sep. 17, 2009 FAN
32 System block diagram (1/4) SDRAM VGA ADC SDRAM Controller VGA Controller Shared Bus CPU On-chip Memory FIR Filter Sep. 17, 2009 FAN
33 System block diagram (2/4) Phase 1 SDRAM VGA ADC Reading data SDRAM Controller VGA Controller Shared Bus CPU On-chip Memory FIR Filter Sep. 17, 2009 FAN
34 System block diagram (3/4) SDRAM VGA Phase 2, 3 Filtering ADC and SDRAM Controller VGA Controller Analysis Shared Bus CPU On-chip Memory FIR Filter Sep. 17, 2009 FAN
35 System block diagram (4/4) SDRAM VGA ADC SDRAM Controller VGA Controller Shared Bus CPU On-chip Memory FIR Filter Phase 4 Display Sep. 17, 2009 FAN
36 Background Our proposal Contents Period-Peak Detection Algorithm System architecture Preliminary Evaluation Conclusion Sep. 17, 2009 FAN
37 Module Processor + on-chip memory Prototype Result Combinational ALUTs Memory ALUTs Dedicated logic registers 1,680 (1%) 0 (0%) 1,654 (1%) FIR filter 450 (<1%) 52 (<1%) 612 (<1%) Others 1,918 (2%) 96 (<1%) 1,937 (2%) Entire system 4,048 (4%) 148 (<1%) 4,203 (4%) Prototyping board (Stratix III DSP board EP3SL150F1152C2) Sep. 17, 2009 FAN
38 System Block Diagram with Analysis Module SDRAM VGA ADC CPU On-chip Memory SDRAM Controller VGA Controller Shared Bus Hardware Accelerator (PPDA Module) CPU On-chip Memory FIR Filter Slave Module Master Module Sep. 17, 2009 FAN
39 Conclusion We proposed Embedded MCSoC Architecture for ECG/EKG processing. We implemented small Master Module. Sep. 17, 2009 FAN
40 Thank you for listening Sep. 17, 2009 FAN
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