Analytical Pinning-Voltage Model of a Pinned Photodiode in a CMOS Active Pixel Sensor

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1 Journal of Sensor Science and Technology Vol. 20, No. 1 (2011) pp DOI : /JSST pissn /eISSN Analytical Pinning-Voltage Model of a Pinned Photodiode in a CMOS Active Pixel Sensor Sung-sik Lee 1, Arokia Nathan 1, Myung-Lae Lee 2 and Chang-Auck Choi 2,+ Abstract An analytical pinning-voltage model of a pinned photodiode has been proposed and derived. The pinning-voltage is calculated using doping profiles based on shallow- and exponential-junction approximations. Therefore, the derived pinning-voltage model is analytically expressed in terms of the process parameters of the implantation. Good agreement between the proposed model and simulated results has been obtained. Consequently, the proposed model can be used to predict the pinning-voltage and related performance of a pinned photodiode in a CMOS active pixel sensor. Keywords : CMOS active Pixel Sensor, Pinning-Voltage, Pinned Photodiode, Analytical Model, Low voltage Operation 1. INTRODUCTION Pinned photodiode(ppd)-based pixels are widely used in CMOS active pixel sensors(capss) due to their low noise level and high sensitivity[1-7] performances. During the operation of the PPD-based pixels, the performance strongly depends on its pinning-voltage(v P ) level, which directly affects the charge-transfer process by the transfergate[2,3]. It is mainly because PPD-based pixels have shown some problems in pixel operation, especially at a low supply-voltage, due to an incomplete charge-transfer and the difficulty of full depletion arising from a high level of V P, resulting in a high random noise-level[3-5]. Hence, it should be required to measure the V P. However, it is difficult to measure V P, so that an accurate prediction of V P is very important to improve device performance in advance, using an analytical model. A simple analytic model for V P was introduced in which the abrupt junction approximation is assumed[6]. However, this model is only valid for uniform doping profiles of a PPD. In this work, an analytical V P model of a PPD has been proposed. To derive the analytic model, shallow- and exponential-junction approximations are employed for 1 London Center for Nanotechnology, University College London, London WC1H 0AH, United Kingdom 2 Electronics and Telecommunications Research Institute(ETRI), 138 Gajeong-no, Daejeon, , Republic of Korea + Corresponding author : cachoi@etri.re.kr (Received : Jul. 31, 2010, Revised : Dec. 9, 2010, Accepted : Dec. 17, 2010) Gaussian doping profiles based on the LSS(Lindhard, Scharff, Schiott) theory[8-10]. In order to verify the proposed V P model, comparisons between the new model and the simulation data have been made using a twodimensional device simulator(sil-vaco). In the following sections, the pinning voltage model is derived, verified, and discussed. 2. MODEL DEVELOPMENT A schematic cross sectional view of the PPD is illustrated in Fig. 1(a), which is composed of both P o /N W junction and N W /P epi junction. In Fig. 1(a), a definition for the voltage pinning condition can be expressed by In addition, the pinning-point is located at the middle of N W, as shown in Fig. 1(a). To calculate the depletion width(w N1, W N2 ) at V P, we begin with a Poisson s equation as follows: where E(x) is an electric field, V(x) is the potential, (x) is the charge density, n(x) is ionized donor density, p(x) is ionized acceptor density, is the permittivity of the silicon, and q is the magnitude of an electron charge. For n(x), the PPD shows Gaussian profiles of N W (x) by the

2 Analytical Pinning-Voltage Model of a Pinned Photodiode in a CMOS Active Pixel Sensor where P P is the peak density of P o (x), R P1 is the projected range of P o (x), R P1 is the normal straggle of P o (x), N P is the peak density of N W (x), R P2 is the projected range of N W (x), and R P2 is the normal straggle of N W (x). After the annealing, R P is redefined by both the annealing time (t) and the dopant-diffusivity (D) at the annealing temperature[8, 9]. At the junction X J1, we can write (5) for a charge density of (x 1 ) based on the shallow junction approximation: By solving (2) using (x 1 ) and the boundary conditions that relate the balance of the charge requirement and depletion approximation[10], we may obtain Fig. 1. (a) A schematic diagram in cross-sectional view and (b) doping profiles based on the Gaussian distribution of the PPD (where t Nw is the junction thickness of the N-well, W N1 is the depletion width in the N-well region at the junction of the N W /P o, and W N2 is the depletion width in the N-well region at the junction of the N W / P epi ). For junction X J2, we can write (7) for charge density (x 2 ) based on an exponential junction approximation: implantation process[8,9], as shown in Fig. 1(b). However, it is difficult to solve the Poisson's equation based on the Gaussian function analytically. Thus, the Gaussian function can be transformed to the parabolic function in the logscale[8-10]. In addition, the parabolic function can be expressed by a linear function in the range of x > (R P2 + R P2 ), and the linear function in the log-scale is transformed into an exponential function in the linear-scale[10]. Therefore, N W2 (x) based on the exponential junction approximation are employed[8, 9], as shown in Fig. 1(b). We can then solve the Poisson's equation and derive an analytical expression for V P. The detailed derivation of the proposed V P model is as follows. As shown in Fig. 1(b), we may obtain p(x) and n(x) based on the Gaussian distribution as in (3) and (4): By solving (2) using charge density (x 2 ) and boundary conditions that relate the balance of the charge requirement and depletion approximation[10], we may obtain (8) assuming exp( W N2 ) 1 exp(- W P2 ): From (1), (6) and (8), we can obtain the analytical expression for V P as follows:

3 Sungsik Lee Arokia Nathan Myung-Lae Lee Chang-Auck Choi Finally, we have an analytical expression for V P, as shown in (9). The derived pinning-voltage model is analytically expressed in terms of the parameters of the implantation(n P, P P, R P1, R P2, R P1, and R P2 ), which are associated with the implant dose(q P, Q N ) and implantation energy(e P, E N )[8,9]. Therefore, V P can be expressed and calculated by the process parameters of the implant dose and implant energy. Table I. Implantation and related process conditions of the PPD for typical cases 3. RESULT AND DISCUSSION In order to verify the accuracy of the proposed model, the simulation results are used for comparison with our model. The typical process conditions for the PPD are used for both the proposed model and simulation, as shown in Table 1. The calculation of V P has been performed using the proposed V P model, as shown in (9). For the calculation of the proposed model, the implant parameters( R P1, R P1, R P2, and R P2 ) are determined by using the plots based on the LSS theory[8, 9]. Fig. 2 shows the calculated V P in comparison with the SILVACO simulation results. Good agreement between the proposed model and simulation results has been obtained, as shown in Fig. 2. In addition, it has been found that V P shows very sensitive characteristics for the N-well implant conditions Fig. 2. Plot of the Pinning-voltage(V P ) vs. N-well implantation energy(e N ) of the proposed model in comparison with the simulated results for various cases of N-well Dose(Q N = cm -2, cm -2, cm -2, cm -2, and cm -2 ). Other conditions(q P, E P, P epi ) are fixed. of Q N and E N. This is mainly because the dominant parameters(n P and X J2 ) are determined by the combination of Q N and E N. On the other hands, the proposed model is based on a 1- Dimensional Poisson s equation so that it is difficult to consider some non-ideal effects, such as breakdown characteristics and parasitic element-related effects. In other words, the proposed model is only valid for a shallow junction, which is fabricated by using a low energy implantation, operating at a low voltage. There are some reasons why a 1-Dimensional model was employed in our analytical model. First, the PPD is normally operated at a low voltage below 1.8 V. Moreover, the p-type substrate and the epi-layer(p epi ) play a role as a resistor to suppress the diode breakdown, though the pinning voltage is below 1 V. Second, a shallow junction can be approximated to a 1-Dimensional structure, which is also one of the reasons why our model is more fit to the simulation results at lower implantation energy below 150 ev, as shown in Fig. 2. Consequently, the proposed model has been verified and can be used to predict V P for typical cases of implantation conditions(q N, E N ) of the PPD process. 4. CONCLUSION This paper presents an analytical model for the pinningvoltage of a pinned photodiode. In order to verify the proposed model, comparisons between the proposed model and simulation results have been made. It is shown that excellent agreement has been obtained. Although the

4 Analytical Pinning-Voltage Model of a Pinned Photodiode in a CMOS Active Pixel Sensor developed model is valid for the Gaussian doping profile based on the LSS theory and suitable for a shallow junction device by low energy implantation, it can be used to predict a typical case of the pinning voltage in a CMOS active pixel sensor. REFERENCES [1] H. Abe, Device technologies for high quality and smaller pixel in CCD and CMOS image sensors, in IEDM Dig. Tech. Papers, pp , [2] K. Findlater, R. Henderson,D, Baxter, et al., SXGA pinned photodiode CMOS image sensor in m technology, in ISSCC Dig. Tech. Papers, pp , [3] K. Mabuchi, N. Nakamura, E. Funatsu, et al., "CMOS image sensors comprised of floating diffusion driving pixels with buried photodiode," IEEE J. Solid-State Circuits, vol. 39, pp , Dec [4] J. Lai and A. Nathan, "Reset and partition noise in active pixel image sensors," IEEE Trans. Electron Devices, vol. 52, pp , Oct [5] H. Tian, B. Fowler, and A.E. Gamal, "Analysis of temporal noise in CMOS photodiode active pixel sensor," IEEE J. Solid-State Circuits, vol. 36, pp , Jan [6] T. Lule, S. Benthien, and H. Keller, et al., "Sensitivity of CMOS based imagers and scaling perspectives," IEEE Trans. Electron Devices, vol. 47, pp , Nov [7] I. D. Jung, M. K. Cho, K. M. Bae, et al., "Pixelstructured scintillator with polymeric microstructures for X-Ray image sensors," ETRI Journal, vol. 30, no. 5, pp , Oct [8] G.Dearmaley, J.H.Freeman, R.S.Nelson, et al., "Ionimplantation, North-Holland, New York, [9] R.C. Jaeger, Introduction to microelectronic fabrication, Second Edition, Prentice Hall, [10] B. Streetman and S. Banerjee, Solid state electronic devices, 5th Edition, Prentice Hall. Sungsik Lee graduated from Korea Advanced Institute of Science and Technology(KAIST) in 2006 and joined ETRI as a researcher for studying in the solid state sensors and the integrated circuit design for driving a sensor. Now, He is a PhD candidate with London Centre for Nanotech-nology, University College London, United Kingdom. He has been the first author of the international journals, the international conference proceedings. Also, he holds the international patents as the first inventor. His research interest is the solid state device physics and mathematical modeling, including the mobility and conduction mechanism in the metal-oxide semiconductors, such as InGaZnO, HfInZnO, ZnO, etc. He is a member of the Material Research Society(MRS). Arokia Nathan is a professor of University College London, United Kingdom. He holds the Sumitomo/ STS Chair of Nanotechnology. He is also the chief technology officer of Ignis Innovation Inc, Waterloo, Canada, a company he founded to commercialize technology on thin film silicon backplanes and driving algorithms for active matrix organic light emitting diode displays. He has extensive experience in device physics and modeling, and materials processing and integration. His present research interests lie in fabrication of devices, circuits, and systems using disordered semiconductors, including organic materials and nanocomposites, on rigid and mechanically flexible substrates for large area electronics, for imaging and display applications. He received his PhD in Electrical Engineering from the University of Alberta, Edmonton, Alberta, Canada, in In 1987, he joined LSI Logic Corp., Santa Clara, CA where he worked on advanced multi-chip packaging techniques and related issues. Subsequently, he was at the Institute of Quantum Electronics, ETH Zrich, Switzerland. In 1989, he joined the Department of Electrical and Computer Engineering, University of Waterloo. In 1995, he was a Visiting Professor at the Physical Electronics Laboratory, ETH Zrich.

5 Sungsik Lee Arokia Nathan Myung-Lae Lee Chang-Auck Choi In 1997 he held the DALSA/NSERC industrial research chair in sensor technology, and was a recipient of the 2001 Natural Sciences and Engineering Research Council E.W.R. Steacie Fellowship. In 2005/2006, he was a Visiting Professor in the Engineering Department, University of Cambridge, UK, and later in 2006, he joined the London Centre for Nanotechnology and the Department of Electrical Engineering, University College London, and holds a Royal Society Wolfson Research Merit Award. He has published extensively in the field of sensor technology and CAD, and thin film transistor electronics, and has over 30 patents filed/awarded. He is a co-author of two books, Microtransducer CAD and CCD Image Sensors in Deep-Ultraviolet, both published by Springer in 1999 and 2005, respectively. He is a Chartered Engineer (UK) and a Fellow of the Institution of Engineering and Technology. He is a Senior Member of the IEEE and a member of the American Physical Society, Electrochemical Society, Materials Research Society, Society for Information Displays, and International Society for Optical Engineering. He is a member of the IEEE EDS Publications Committee and the IEEE EDS/LEOS Sub- Committee on Organic and Polymer Devices. He chaired the 2005 and 2006 IEEE Lasers and Electro-Optics Society Technical Committee on Displays and serves as SRC Vice- Chair for Regions 1,2,3,&7. He received the IEEE/EDS Distinguished Lecturer Award in He is the Editor-in- Chief of the IEEE/OSA Journal of Display Technology, and an editor of Electron Device Letters and IEEE Trans. Devices, Materials, and Reliability. He co-chaired the Fall 2005 Materials Research Society Symposium M: Flexible and Printed Electronics, Photonics, and Biomaterials, the Fall 2006 Materials Research Society Symposium BB on Mobile Energy, and the Spring Materials Research Society Symposium A on Amorphous and Polycrystalline Thin-Film Silicon Science and Technology in 2007 and He was a Guest Editor for a two-part Special Issue on Flexible Electronics Technology in IEEE Proceedings. Myung-Lae Lee received his BS degree in Physics from Dong-A University, Busan, Korea, in 1989, and his MS and PhD degrees in Physics from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1992 and 1998, respectively. Since 1998, he has been working for ETRI. His research interests include the design, fabrication, and characterization of MEMS devices with signal processing ICs for applications in the areas of optics, RF, and USN. Chang-Auck Choi received his MS and PhD degrees in electronic engineering from Kyungpook National University, Taegu, Korea, in 1988 and 1999, respectively. Since 1980, he has worked for ETRI in the area of developing micro-electro-mechanical system (MEMS) devices and advanced semiconductor process technology. He is currently the project manager of MEMS sensor technology development. He is currently researching physical sensors and integrated MEMS sensors for ubiquitous sensor networks.