DESCRIPTION. Vout=3.3V. X TR 2K 0x08

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1 FETURES Minimum BV DSS > 650V. llowed V GS range 5V to +2V. Operational beyond the -60 C to +230 C temperature range. Low R DS(on) o XTR2K0x08: C Maximum I D: o XTR2K0208: 230 C (package limited) o XTR2K0308: 230 C On-time (t d(on)+t r): o XTR2K0x08: 230 C Off-time (t d(off)+t f): o XTR2K0x08: 230 C Ruggedized 3-lead TO257, 8-lead side brazed DIP and 8-lead SOIC-like with epd. PPLICTIONS Reliability-critical, utomotive, eronautics & erospace, Down-hole. Voltage regulation, voltage clamping, power switching, motor control, power inverters. PRODUCT HIGHLIGHT VIN High Input Voltage Series Regulator XTRM Series XTR2K0x08 HIGH-TEMPERTURE, 80mΩ HIGH-VOLTGE N-CHNNEL DEPLETION JFET DESCRIPTION XTR2K0x08 is a family of 80mΩ depletion jfets with maximum operation voltages between 50V and 300V designed to reliably operate from -60 C to +230 C, with junction temperature able to reach +250 C. Fabricated on a Silicon Carbide (SiC) process, XTR2K0x08 parts offer reduced leakage currents while offering low R DS(on) and gate charge (Q g). These features allow XTR2K0x08 parts to be ideally suited for linear as well as for switching applications. Parts from the XTR2K0x08 family are available in ruggedized 3- lead TO257, 8-lead side brazed DIP and 8-lead SOIC-like with epd. High-Voltage Composite Transistor (Cascode) DRIN XTR2K0x08 (HV Depletion FET) XTR2K0x08 (HV Depletion FET) VIN /SHDN XTR750 GND 3.3V VOUT TRIM Vout=3.3V GTE Cin Cout XTR2N0425 (40V MOSFET) SOURCE ORDERING INFORMTION X TR 2K 0x08 Source: X = X-REL Semi Process: TR = HiTemp, HiRel R = HiRel Part family Part number Product Reference Max VDS Temperature Range Package Pin Count Marking XTR2K0208-D 50V -60 C to +230 C Ceramic side Braze DIP 8 XTR2K0208 XTR2K0208-FE 50V -60 C to +230 C Gull-wing flat pack with epad 8 XTR2K0208 XTR2K0308-T 300V -60 C to +230 C TO XTR2K0308 Other packages and packaging configurations possible upon request. For some packages or packaging configurations, MOQ may apply. DS revc of 6

2 BSOLUTE MXIMUM RTINGS Drain-source voltage XTR2K0208 0V to +50V XTR2K0308 0V to +650V Gate-source voltage -20V to +3V Storage temperature range Operating junction temperature range ESD classification -70 C to +230 C -70 C to +250 C 2kV HBM MIL-STD-750 Caution: Stresses beyond those listed in BSOLUTE MXIMUM RTINGS may cause permanent damage to the device. These are stress ratings only and functionality of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to BSOLUTE MXIMUM RTINGS conditions for extended periods may permanently affect device reliability. PRODUCT VRINTS TO-257 Front view DIP8 / CDFP8 Top view 8 XTR2K0308-T 2 3 XTR2K0208-D XTR2K0208-FE THERML CHRCTERISTICS DRIN, 2, 3 SOURCE 2 SOURCE 4 GTE 3 GTE 5, 6, 7, 8 DRIN Case Floating epd of CDFP8 SOURCE Parameter Condition Min Typ Max Units XTR2K0308-T (TO257) Thermal Resistance: J-C 5 C/W R Th_J-C Thermal Resistance: J- R Th_J- XTR2K0208-D (DIP8) Thermal Resistance: J-C R Th_J-C Still air. 50 C/W 20 C/W Thermal Resistance: J- Still air. 00 C/W R Th_J- XTR2K0208-FE (DFP8 with exposed pad) Thermal Resistance: J-C Measured on epd. 7 C/W R Th_J-C Thermal Resistance: J- R Th_J- epd thermally connected to 3cm² PCB copper 70 C/W DS revc of 6

3 RECOMMENDED OPERTING CONDITIONS Parameter Min Typ Max Units Drain-source voltage V DS XTR2K0208 XTR2K0308 Gate-source voltage V GS Junction Temperature T j V C V Operation beyond the specified temperature range is achieved. XTR2K0208 SPECIFICTIONS Unless otherwise stated, specification applies for -60 C<T j<230 C. Parameter Condition Min Typ Max Units DC Characteristics Maximum Continuous Drain-source Voltage V GS=-5V 50 V V DS_Max Static Drain-source On-state Resistance R DS(on) Continuous Drain I D(DC) V GS(th) Temperature Drift of V GS(TH) Off-state Drain I DSS Reverse Gate Leakage I GSSR Forward Gate Leakage I GSSF C Characteristics Input Capacitance C iss Output Capacitance C oss Transfer Capacitance C rss Switching Characteristics Pulsed Drain I DM Total Gate Charge Q g Turn-on Delay Time t d(on) Rise time t r Turn-off Delay Time t d(off) Fall Time t f Turn-on Energy E ON Turn-off Energy E OFF V GS=0V, I DS=2 V GS=+2V for TO-257 T J 50 C T J=230 C V DS=5V, I DS=50m V 60 C<T j<230 C 200 mv V DS=50V, V GS=-5V V GS=-5V V GS=2V V DS=00V, V GS=-5V, f=00khz V GS sweep=-5 to +2V, =ms T C 50 C m µ µ m 500 pf V DS=50V, V GS sweep=-5 to +2V 62 nc V DS=50V, V GS sweep=-5 to 2V, R G_Ext=2.5Ω. Inductive load ns µj DS revc of 6

4 XTR2K0308 SPECIFICTIONS Unless otherwise stated, specification applies for -60 C<T j<230 C. Parameter Condition Min Typ Max Units DC Characteristics Maximum Continuous Drain-source Voltage V GS=-5V 300 V V DS_Max Static Drain-source On-state Resistance R DS(on) Continuous Drain I D(DC) V GS(th) Temperature Drift of V GS(TH) Off-state Drain I DSS Reverse Gate Leakage I GSSR Forward Gate Leakage I GSSF C Characteristics Input Capacitance C iss Output Capacitance C oss Transfer Capacitance C rss Switching Characteristics Pulsed Drain I DM Total Gate Charge Q g Turn-on Delay Time t d(on) Rise time t r Turn-off Delay Time t d(off) Fall Time t f Turn-on Energy E ON Turn-off Energy E OFF V GS=0V, I DS=2 V GS=+2V for TO-257 T J 50 C T J=230 C V DS=5V, I DS=50m V 60 C<T j<230 C 200 mv V DS=50V, V GS=-5V V GS=-5V V GS=2V V DS=00V, V GS=-5V, f=00khz V GS sweep=-5 to +2V, =ms T C 50 C m µ µ m 500 pf V DS=300V, V GS sweep=-5 to +2V 65 nc V DS=300V, V GS sweep=-5 to 2V, R G_Ext=2.5Ω. Inductive load ns µj DS revc of 6

5 PCKGE OUTLINES Dimensions shown in mm [inches]. Tolerances ±3 mm [±0.005 in] unless otherwise stated. Ceramic Gull-wing Flat pack with epad DFP8 4x R 0.8 [0.032] 5.84 [0.230] 0.05 [0.002] 8x 3 [0.005] 5.84 [0.230] XTRPPPPP YYWWNN 5.58 [0.220] 6.60 ±0.25 [0.260 ±0.0] 7.75 ±0.25 [0.305 ±0.0] 0.64 [0.025] 0.00 ±0.05 [0.000 ±0.002] epd 4x R 0.64 [0.025] 5.46 ±0.25 [0.25 ±0].45 [0.057] 6x.27 8x 0.30 ±0.05 [0.050] [0.02 ±0.002] 3.8 ±3 [50 ±0.005] 5.46 ±0.25 [0.25 ±0] 4x R 0.76 [0.030] Ceramic Side Brazed Dual In-line DIP8 3.2 ±0.20 [0.520 ±0.008].43 [0.450] 0.03 [0.00] 8x 0.03 [0.00] 7.87 ±0.25 [0.30 ±0.00] 7.37 ±020 [0.290 ±0.008] XTRPPPPP YYWWNN 6.86 [0.270].27 [0.050] 3.30 ±0.25 [30 ±0.00] 2.6 [0.085] 8x 4.00 ±0.50 [58 ±0.020] 6x 2.54 [00] 8x 0.46 [0.08] 7.62 ±3 [0.300 ±0.005] TO-257 (TO-220M) Ø 3.50 [38] 0.60 ±5 [0.47 ±0.028].00 ±0 [0.039 ±0.004] 4.90 ±0.20 [93 ±0.008] [0.004] 3.50 ±0.20 [0.532 ±0.008] XTRPPPPP YYWWNN 6.50 ±0.20 [0.650 ±0.008] 0.60 ±5 [0.47 ±0.028] 4x R 0.5 [0.020] 8.00 ±0.50 [0.707 ±0.020] Ø 3x 2.0 [0.083].0 [0.043] 2x 2.54 [00] 5.08 ±0.20 [0.200 ±0.008] Ø 3x 0.80 [0.032] 2.90 ±0.20 [4 ±0.008] DS revc of 6

6 Part Marking Convention Part Reference: XTRPPPPPP XTR X-REL Semiconductor, high-temperature, high-reliability product (XTRM Series). PPPPP Part number (0-9, -Z). Unique Lot ssembly Code: YYWWNN YY Two last digits of assembly year (e.g. 5 = 205). WW ssembly week (0 to 52). ssembly location code. NN ssembly lot code (0 to 99). IMPORTNT NOTICE & DISCLIMER Information in this document supersedes and replaces all information previously supplied. Information in this document is provided solely in connection with X-REL Semiconductor products. The information contained herein is believed to be reliable. X-REL Semiconductor makes no warranties regarding the information contain herein. X-REL Semiconductor assumes no responsibility or liability whatsoever for any of the information contained herein. X-REL Semiconductor assumes no responsibility or liability whatsoever for the use of the information contained herein. The information contained herein is provided "S IS, WHERE IS" and with all faults, and the entire risk associated with such information is entirely with the user. X-REL Semiconductor reserves the right to make changes, corrections, modifications or improvements, to this document and the information herein without notice. Customers should obtain and verify the latest relevant information before placing orders for X-REL Semiconductor products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by such information. Unless expressly approved in writing by an authorized representative of X-REL Semiconductor, X-REL Semiconductor products are not designed, authorized or warranted for use in military, aircraft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or property or environmental damage. General Sales Terms & Conditions apply. CONTCT US For more information on X-REL Semiconductor s products, technical support or ordering: Web: /products Tel: Fax: Sales: sales@x-relsemi.com /EN/Sales-Representatives Information: info@x-relsemi.com Support: support@x-relsemi.com X-REL Semiconductor 90, venue Léon Blum 3800 Grenoble France DS revc of 6

60 V, 0.3 A N-channel Trench MOSFET

60 V, 0.3 A N-channel Trench MOSFET Rev. 01 11 September 2009 Product data sheet 1. Product profile 1.1 General description ESD protected N-channel enhancement mode Field-Effect Transistor (FET) in a small SOT2 (TO-26AB) Surface-Mounted