Chapter 8: Atmel s AVR 8-bit Microcontroller Part 3 Microarchitecture. Oregon State University School of Electrical Engineering and Computer Science

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1 Chapter : tmel s VR -bit Microcontroller Part 3 Microarchitecture Prof. en Lee Oregon State University School of Electrical Engineering and Computer Science Chapter Goals Understand what basic components needed and how they are interconnected to implement a datapath to perform data transfer and processing. Design a control unit to provide appropriate signals to the various components to control the operations within the datapath. Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 2

2 Contents. Microarchitectrure.2 Instruction Format.3 Components in the asic path.4 Multi-cycle Implementation.5 Eecution of More Comple Instructions. Control Unit Design. Finite State Implementation of the Control Unit. Pipeline Implementation Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 3. Microarchitecture Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 4 2

3 VR path - get the net instruction from memory. Eecute - figure out what to do with it and do it. This is how all CPUs wor! Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 5 VR Control Unit Maes the /Eecute happen Controls the fetch (of instruction) Decodes instructions Controls eecution of instructions Two basic types Hardwired (fast) Microprogrammed (fleible) Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 3

4 .2 Instruction Format Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture VR Instruction Format Two-operand format r d d d d d r r r r (e.g., DD, CP, MOV, etc.) I/O format d d d d d (e.g., IN, OUT) Immediate format K K K K d d d d K K K K (e.g., LDI, NDI, ORI, etc.) One-operand format d d d d d (e.g., INC, DEC, COMP, etc.) Displacement format - - q - q q - d d d d d - q q q (e.g., LDD, STD) Direct format (e.g., JMP, CLL) -relative format (e.g., RJMP, RCLL, Rcc, etc.) 2 Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 4

5 .3 Components in the asic path Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 9 asic VR path ++,, or Z + Two stages: and Eecute ddr + Inst/ R, R+, -R, or R+q + DMR Eecute lignment Unit Rd Rr K q 5 5 or 2 + or R ddr. w w r r in in out out MUX In ddr MUXF R MUXG MUX LU LU ddress dder R, R+,-R, or R+q ++,, or Z Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 5

6 s Counter Instruction DMR ddress Net Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture Memories In ddr In ddr PM_write PM_read DM_write DM_read Inst/ or Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 2

7 Sign-Etension & Zero-Fill n-bit to m-bit mapping ++,, or Z + ddr Inst/ R, R+, -R, or R+q + + DMR Eecute lignment Unit Rd Rr K q 5 5 or 2 + or R ddr. w w r r in in out out MUX In ddr MUXF R MUXG MUX LU LU ddress dder R, R+,-R, or R+q ++,, or Z Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 3 Sign-Etension & Zero-Fill n n m m MS LS M L S S q q q q q q Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 4

8 LU LU_f 4 LU Performs -bit operations. Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 5 lignment Unit Maps bits in the Instruction Format to fields needed by the datapath r d d d d d r r r r K K K K d d d d K K K K d d d d d d d d d d q - q q - d d d d d - q q q Two-operand Immediate I/O Single-operand Displacement 2-bit -relative -bit -relative lignment Rd Rr K q 5 5 or 2 Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture

9 ddress Rd Rr 5 5 ddr. w w r r Maps opcode,, Rd, and Rr to r, r, w, and w. RL automatically generates X, Y, and Z bad on opcode. Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 2-read-port, 2 write-port in in CLK... r r w w w in w in out r r out RF_w RF_w ddress read in one cycle (e.g., X-, Y-, or Z). D R Q D R 2 Q... 2 MUX D R E Q... E E... 2 MUX... Decoder 2... Decoder 2... RF_w RF_w out out Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 9

10 ddress dder dder_f 2 ddress dder Generates target address for branches and jumps. Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 9 MUXs Routes information from one part of the datapath to another ++,, or Z + ddr Inst/ R, R+, -R, or R+q + + DMR Eecute lignment Unit Rd Rr K q 5 5 or 2 + or R ddr. w w r r in in out out MUX In ddr MUXF R MUXG MUX LU LU ddress dder R, R+,-R, or R+q ++,, or Z Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 2

11 .4 Multi-cycle Implementation Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 2 and Eecute Stages Spends one cycle in the stage to fetch an instruction. Spends one or more cycles in the Eecute and stages to eecute an instruction. Eecute Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 22

12 Multi-cycle Implementation t IF EX IF EX EX2 IF EX IF EX EX2 EX3 Instruction i Instruction i+ Instruction i+2 Instruction i+3 Instruction cycles ( and Eecute) eecuted quentially. Will e pipeline implementation later. Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 23 Cycle + ddr Inst/ Instruction + + DMR Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 24 2

13 Eecute Cycle Depends on the instruction rithmetic and transfer ranch and jump Different parts of the datapath are activated. Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 25 rithmetic and Instructions Eecute DMR lignment Unit Rd Rr K q 5 5 or 2 ddr. w in in out w r r out Rd op Rr, Rd op K, or op Rd Rd Rr MUX Rr or K K In ddr MUXF MUXG MUX LU ddress dder Op Rd, Rr Op Rd, K Op Rd Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 2 3

14 Transfer: MOV (-bit) Eecute DMR lignment Unit Rd Rr K q 5 5 or 2 ddr. w in in out w r r out r = Rr w = Rd Rr Rr MUX In ddr MUXF MUXG MUX LU ddress dder Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 2 Transfer: MOVW (-bit) Eecute DMR lignment Unit Rd Rr K q 5 5 or 2 Rr+ Rr ddr. w in in out w r r out MUX In Rr+:Rr ddr MUXF MUXG r = Rr+ r = Rr w = Rd + w = Rd MUX LU ddress dder Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 2 4

15 Transfer: IN Eecute DMR lignment Unit Rd Rr K q 5 5 or 2 ddr. w in in out w r r out r = + 32 w = Rd MUX In ddr MUXF MUXG MUX LU ddress dder Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 29 Transfer: OUT Eecute DMR lignment Unit Rd Rr K q 5 5 or 2 ddr. w in in out w r r out w = + 32 r = Rd (Rr) Rd (Rr) Rd (Rr) MUX In ddr MUXF MUXG MUX LU ddress dder Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 3 5

16 Load and Store Us ddress (R): X-, Y-, and Z- register. Displacement Pre-decrement Post-increment Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 3 Indirect Load and Store EX R Eecute DMR lignment Unit Rd Rr K q 5 5 or 2 R ddr. w in in out w r r out MUX In R ddr MUXF MUXG r = Rh r = Rl MUX LU ddress dder 32

17 Indirect \w Disp. EX Y+q or Z+q Eecute DMR lignment Unit Rd Rr K q 5 5 or 2 ddr. w in in out w r r out r = Rh r = Rl MUX In ddr MUXF q MUXG Y or Z MUX LU ddress dder 33 Indirect \w Pred. EX R- Eecute DMR lignment Unit Rd Rr K q 5 5 or 2 R- R-(h) R-(l) ddr. w in in out w r r out MUX In ddr MUXF MUXG R r = Rh r = Rl w = Rh w = Rl MUX LU ddress dder 34

18 Indirect \w Post. - EX R Eecute R+ R R+(h) R+(l) w in in out w r Rd Rr 5 5 ddr. r out lignment Unit MUX K q In or 2 DMR ddr MUXF MUXG R r = Rh r = Rl w = Rh w = Rl MUX LU ddress dder Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 35 Load EX2 Eecute DMR lignment Unit Rd Rr K q 5 5 or 2 ddr. w in in out w r r out w = Rd M[R] MUX In R ddr MUXF MUXG MUX LU ddess dder 3

19 Store EX2 Eecute DMR lignment Unit Rd Rr K q 5 5 or 2 ddr. w in in out w r r out r = Rd (Rr) MUX Rd/Rr In R ddr MUXF MUXG MUX LU ddress dder 3 -relative ranch EX ++ ddr + Inst/ DMR Eecute lignment Unit Rd Rr K q 5 5 or 2 ddr. w w r r in in out out MUX In ddr 2 + MUXF MUXG MUX LU ddress dder

20 Jump Direct EX + ddr + Inst/ DMR Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 39 Jump Direct EX2 ddr + Inst/ DMR Eecute lignment Unit Rd Rr K q 5 5 or 2 ddr. w w r r in in out out MUX In ddr MUXF MUXG MUX LU ddress dder 4 2

21 Jump Indirect EX Z ddr + Inst/ DMR Eecute lignment Unit Rd Rr K q 5 5 or 2 ddr. w w r r in in out out MUX In ddr MUXF Z MUXG MUX LU ddress dder 4.5 Eecution of More Comple Instructions Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 42 2

Enhanced VR path dditional s: RR Return ddress MDR PMR ddress Concatenation = h l RR = RRh RRl dditional MUXs: MUXD MUXE MUXI DEMUX SP Manipulation: Increment/Decrement Unit Eecute R MDR MUX 2 LU PMR

22 Enhanced VR path dditional s: RR Return ddress MDR PMR ddress Concatenation = h l RR = RRh RRl dditional MUXs: MUXD MUXE MUXI DEMUX SP Manipulation: Increment/Decrement Unit Eecute R MDR MUX 2 LU PMR Rd Rr 5 5 ddr. w w r r in in out out Z q MUXL ddr Inst/ lignment Unit LU MUX K DEMUX R, R+, R-, or R+q MUXD In or 2 R DMR MUXE ddr ++ or RRh + + RR MUXI RRl ddress dder MUXF + MUXG + SP+ or SP- + or SP ± SP R, R+,R-, or R+q ++, or Z 43 Control Signals DEMUX DEMUX MJ 3 ways to latch : _en h: h_en l: l_en Only one can be enabled at a time. Eecute CU => Control Unit + lignment Unit MDR MH MC 2 2 PMR Rd Rr 5 5 ddr. _en w w r r in in out out q MUXL ddr Inst/ h_en Control & lignment Unit K RF_w RF_w ML or 2 l_en DMR _en MI RR MUXI MK + _en SP_en SP _en enables latching of both and RR M MUX 4 LU_f MD MUXD ME MUXE MUXF MUXG MF MG M MUX In ddr 2 ddress LU DM_w DM_r dder Inc_Dec dder_f ± 44 22

23 . Control Unit Design Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 45 Instructions Considered # of Eecute cycles 2 2 2/ 4 Defined in tmel -bit VR Instruction Set Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 4 23

24 Encoding Group Defines different arithmetic & logic operations add Group Defines different immediate operations ori Group C Group D etension a a a a aa defines X, Y, or Z register + defines post-increment - defines pre-decrement ld call Defines different conditions st breq Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 4 Encoding Group nop movw muls mulu fmul fmuls fmulsu cpc sbc add or lsl cp cp sub adc or rol and or tst eor or clr cpi Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 4 or mov 24

25 Encoding Group sbci subi ori or sbr andi or cbr Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 49 Encoding Group C X ld X st X ldd X std X X lpm elpm pop push com neg swap inc asr lsr ror X X dec jmp call Group C encodes the largest number of instructions c z n v s h t i clc clz cln clv cls clh clt cli Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 5 25

26 Encoding Group C lds ret reti sleep brea wdr lpm elpm spm ijmp icall eijmp sts eicall adiw cbi in sbiw sbic sbi sbis out Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 5 Encoding Group D rjmp rcall ldi r brcs or brlo breq brmi brvs brlt brts brie brcc or brsh brne brpl brvc brge brhc brtc brid bld bst sbrc sbrs Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 52 2

27 Stage DEMUX + PMR MUXL ddr Inst/ + + Eecute MDR M[] DMR + RR SP lso latches + onto RR 2 Rd Rr 5 5 ddr. w w r r in in out out Control & lignment Unit K RF_w RF_w q or 2 MUXI MUX MUXD MUXE In ddr MUXF MUXG MUX LU DM_w ddress DM_r dder ± 53 DD EX PMR DEMUX MUXL ddr _en must be so that it points to the net instruction be fetched. + Inst/ Eecute MDR 2 Rd Rr 5 5 ddr. w w r r in in out out K RF_w RF_w DD Rd, Rr Control & lignment Unit q or 2 DMR RR MUXI SP _en in the last EX cycle can be don t care, since stage will fetch a new instruction. must not be modified. Rd+Rr MUXD MUXE MUXF MUXG MUX In ddr Rd Rr MUX LU DM_w ddress DM_r dder ± SP must not be modified. 54 2

28 ORI EX PMR DEMUX MUXL ddr _en must be so that it points to the net instruction be fetched. + Inst/ Eecute MDR 2 Rd Rr 5 5 ddr. w w r r in in out out K RF_w RF_w ORI Rd, K Control & lignment Unit q or 2 DMR RR MUXI SP _en in the last EX cycle can be don t care, since stage will fetch a new instruction. must not be modified. Rd K MUXD MUXE MUXF MUXG MUX In ddr Rd K MUX LU DM_w ddress DM_r dder ± SP must not be modified. 55 REQ EX ++ DEMUX PMR MUXL ddr (taen) or (not taen) + _en needs to be or depending Z-flag. Inst/ Eecute MDR 2 Rd Rr 5 5 ddr. w w r r in in out out K RF_w RF_w REQ Control & lignment Unit q or 2 DMR RR MUXI SP _en in the last EX cycle can be don t care, since stage will fetch a new instruction. must not be modified. MUXD MUXE MUXF MUXG MUX + In ddr MUX LU DM_w ddress DM_r dder ± SP must not be modified. 5 2

29 LD and ST EX PMR DEMUX MUXL ddr _en must be so that it points to the net instruction be fetched. + Inst/ Eecute MDR 2 LD Rd, Y or ST Y, Rr Rd Rr 5 5 ddr. w w r r in in out out Yh Yl Control & lignment Unit K RF_w RF_w q or 2 DMR RR MUXI SP _en must be to provide instruction to the subquent cycle. must not be modified. Yh:Yl MUXD MUXE MUXF MUXG MUX In ddr Yh:Yl MUX LU DM_w ddress DM_r dder ± SP must not be modified. 5 LD EX2 PMR DEMUX MUXL ddr _en must be so that it points to the net instruction be fetched. + Inst/ Eecute MDR 2 Rd Rr 5 5 ddr. w w r r in in out out K RF_w RF_w LD Rd, Y Control & lignment Unit q or 2 DMR RR MUXI SP _en in the last EX cycle can be don t care, since stage will fetch a new instruction. SP must not be modified. M[Y] MUX MUXD In MUXE Y ddr MUXF MUXG MUX LU DM_w DM_r ddress dder ± 5 29

30 ST EX2 PMR DEMUX MUXL ddr _en must be so that it points to the net instruction be fetched. + Inst/ Eecute MDR 2 Rd Rr 5 5 ddr. w w r r in in out out K RF_w RF_w ST Y, Rr Control & lignment Unit q or 2 DMR RR MUXI SP _en in the last EX cycle can be don t care, since stage will fetch a new instruction. SP must not be modified. MUX MUXD Rr In MUXE Y ddr MUXF MUXG MUX LU DM_w DM_r ddress dder ± 59 Direct Subroutine Call EX Return ddress (R) CLL K Net Instruction EX2 Low => K RR R SP Rl High SP EX3 Low Rh Rl High K => K Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 3

31 CLL EX PMR DEMUX MUXL + _en can be don t care since it will be overwritten in EX3. ddr + Inst/ Eecute MDR 2 w w r r in in out out Rd Rr 5 5 ddr. MUX Control & lignment Unit K RF_w RF_w CLL q MUXD In or 2 DMR MUXE ddr +2 RR MUXI MUXF MUXG SP _en must be to provide instruction to the subquent cycle. SP must not be modified. Subroutine return address is latched onto RR. MUX LU DM_w DM_r ddress dder ± CLL EX2 PMR DEMUX MUXL _en can be don t care since it will be overwritten in EX3. ddr + Inst/ Eecute MDR 2 Rd Rr 5 5 ddr. w w r r in in out out K RF_w RF_w CLL Control & lignment Unit q or 2 DMR RR MUXI SP- SP _en must be to provide instruction to the subquent cycle. RR must not be modified. MUX MUXD MUXE RRl SP In ddr MUXF MUXG MUX LU DM_w ddress DM_r dder ± 2 3

32 CLL EX3 PMR DEMUX MUXL updated. ddr + Inst/ Eecute MDR 2 Rd Rr 5 5 ddr. w w r r in in out out K RF_w RF_w CLL Control & lignment Unit q or 2 DMR RR MUXI SP-2 SP _en in the last EX cycle can be don t care, since stage will fetch a new instruction. MUX MUXD MUXE RRh SP- In ddr MUXF MUXG MUX LU DM_w ddress DM_r dder ± 3 Summary of Control Signals Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 4 32

33 . Finite State Implementation of the Control Unit Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 5 Sequence Control M[], +, + IF DD ORI REQ REQ LD or ST CLL Z= Z= Rd Rd+Rr Rd Rd-K -- DMR X ++ M[] + EX LD ST CLL Rd M[DMR] M[DMR] Rd M[SP] l SP SP- EX2 CLL M[SP] h SP SP- EX3 Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 33

Finite State Table IF is independent of inputs State transition from (IF) depends on opcode State transition from (IF) to (REQ, Z =) or (REQ, Z=) depends on opcode and Z.

34 Finite State Table IF is independent of inputs State transition from (IF) depends on opcode State transition from (IF) to (REQ, Z =) or (REQ, Z=) depends on opcode and Z. State transition from (LD/ST, EX) to (LD, EX2) or (ST, EX2) depends only on bit 9 of opcode. State transition from to and from to depends only on the current state. Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture FSM Current State () Z CLK D D D 2 D 3 Control... Net State pth Control Outputs Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 34

35 RL Mapping X = not relevant op DD (EX) X Rd Rr Rd Rr 5 5 ddr. w w r r X Rd Rd Rr op ORI (EX) X Rd X Rd Rr 5 5 ddr. w w r r X Rd Rd X op LD and ST (EX) X X X Rd Rr 5 5 ddr. w w r r X X Yh Yl Y-register op LD (EX2) X Rd X Rd Rr 5 5 ddr. w w r r X Rd X X Destination op ST (EX2) X Rd X Rd Rr 5 5 ddr. w w r r X X X Rd Source Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 9 RL Mapping (cont.) X = not relevant X REQ (EX) X X X Rd Rr 5 5 ddr. w w r r X X X X RF is not accesd! X CLL (EX) X X X Rd Rr 5 5 ddr. w w r r X X X X X CLL (EX2) X X X Rd Rr 5 5 ddr. w w r r X X X X X RF is not accesd! Separate Inc/Dec Unit and path for manipulating SP CLL (EX3) X X X Rd Rr 5 5 ddr. w w r r X X X X Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 35

ddress 5 4 9... Rd Rr 5 5 State Decoder Yh Yl 2 GPR w MUX w MUX r 2 3 MUX r Ch.

36 ddress Rd Rr 5 5 State Decoder Yh Yl 2 GPR w MUX w MUX r 2 3 MUX r Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture. Pipeline Implementation Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 2 3

37 Pipeline Implementation t IF EX IF EX EX2 IF EX IF EX EX2 EX3 Instruction i Instruction i+ Instruction i+2 Instruction i+3 Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 3 Eecution of DD and PMR DEMUX MUXL + +2 Eecution of ORI and is similar. ddr + Inst/ +2 Net Instruction Eecute MDR DD Rd, Rr DMR RR SP 2 Rd Rr 5 5 ddr. w w r r in in out out Control & lignment Unit K RF_w RF_w q or 2 MUXI Rd+Rr MUXD MUXE MUXF MUXG MUX In ddr Rd Rr MUX LU DM_w ddress DM_r dder ± 4 3

38 Eecution of REQ and ++ PMR DEMUX MUXL + ddr (taen) Eecution of any conditional branch instruction and is similar. + Inst/ +2 $ (taen) MUX Eecute MDR REQ DMR RR SP 2 Rd Rr 5 5 ddr. w w r r in in out out Control & lignment Unit K RF_w RF_w q or 2 MUXI MUX MUXD MUXE In ddr MUXF MUXG + MUX LU DM_w ddress DM_r dder ± 5 Eecution of REQ and t t IF EX IF EX ranch Penalty IF EX IF IF EX i i+ i i+ REQ not taen REQ taen Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 3

39 Eecution of CLL-EX3 & IF EX EX2 EX3 t IF Target address of CLL latched onto Instruction at target address of CLL fetched IF EX Instruction i Instruction i+ ed instruction invalid Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture Eecution of CLL-EX3 & PMR DEMUX MUXL Creates a bubble by eecuting a NOP instruction - $. ddr + Inst/ $ MUX SP-2 Eecute MDR CLL DMR RR SP 2 Rd Rr 5 5 ddr. w w r r in in out out Control & lignment Unit K RF_w RF_w q or 2 MUXI MUX MUXD MUXE RRh SP- In ddr MUXF MUXG MUX LU DM_w ddress DM_r dder ± 39

40 Questions? Ch. : tmel's VR -bit Microcontroller, Part 3 - Microarchitecture 9 4

Chapter 7: Digital Components. Oregon State University School of Electrical Engineering and Computer Science. Review basic digital design concepts:

Chapter 7: Digital Components. Oregon State University School of Electrical Engineering and Computer Science. Review basic digital design concepts: hapter 7: igital omponents Prof. en Lee Oregon tate University chool of Electrical Engineering and omputer cience hapter Goals Review basic digital design concepts: esigning basic digital components using