Error Control Codes for Memories

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1 The 2 th Korea Test Conference Error Control Codes for Memories June 22, 2 Jun Jin Kong, Ph.D. (jjkong@samsung.com) Samsung Electronics Co., Ltd. (Memory)

2 Biography of Jun Jin Kong Brief History Present: Samsung Electronics Co., Ltd., Semiconductor Business Division 25: University of Minnesota, USA, Electrical Engineering (VLSI Architecture Design for DSP, Channel Coding, Quantum Computing) 989: Samsung Advanced Institute of Technology Research Interests Channel Signal Processing for Memory and Memory based Storage Systems Channel Signal Processing for Magnetic/Optical Recording Systems VLSI Architecture Design for Digital Signal Processing (VLSI DSP) Low Power Digital CMOS Design Social Activities IEEE, Member / CASS VSA TC Steering Committee Member of the Coding and Information Society in Korean Institute of Communication Science The Institute of Electronics Engineers of Korea, Semiconductor Society June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong /4

3 Semiconductor Memories: Introduction

4 MOS Memory Hierarchy MOS (Metal-Oxide Semiconductor) Memory mid-96s Volatile Random Access Memory (RAM) Non-Volatile Read Only Memory (ROM) Static RAM (SRAM) 97 by Intel Emerging Memories - FeRAM : Ferroelectric RAM - MRAM : Magnetoresistive RAM - PRAM : Phase change RAM Dynamic RAM (DRAM) Refresh (UV)-EPROM Chip-level erase 97 by Intel Programmable ROM (PROM) FF-EEPROM byte-level erase EEPROM Mask ROM One Time PROM 97 by Intel single cell erase Flash EEPROM block-level erase 979 by Intel 984 by Toshiba June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 3/4

5 Emerging Memories June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 4/4

6 The Characteristics of an Ideal Memory ) Nonvolatility 2) High Density [consumes small space/bit] 3) Fast read/write/erase 4) In-system re-writability 5) Bit alterability 6) High Endurance [high write/erase cycles] 7) Low power consumption 8) High bit count 9) Low cost ) Highly scalable ) Single-power supply 2) Ruggedness 3) Portability 4) Small form factor 5) Highly integrable with other system technologies June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 5/4

7 NVM: Flash memory Flash memories are non-volatile memories (NVM) in which a single cell can be electrically programmed and a large number of cells called a block, sector or page are electrically erasable at the same time. The word flash itself is related to the fact that since the whole memory can be erased at once, erase time can be very fast. Two are the parameters describing how good and reliable a non-volatile memory cell is: endurance and retention. endurance: capability of maintaining the stored information after erase/program/read cycling. retention: capability of keeping the stored information in time. June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 6/4

8 Flash Memory: Cell Structure Two are the most common solutions used to store charge: charge trap: in traps which are present in the insulator or at the interface between two dielectric materials. floating gate (FG): in a conductive material layer between the gate and the channel and completely surrounded by insulator. This is the floating gate device. Floating Gate Interpoly Dielectric Word Line Tunnel Oxide Drain Source Flash (FG: Floating Gate) June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 7/4

9 Flash Memory: Array Architecture NOR large cell and fast random access Contact is the limiting factor for scale-down NAND Small cell and fast burst read Easy to scale-down Bit Line Contact Bit Line Bit Line Contact Bit Line Unit Cell Unit Cell Control Gate Control Gate Common Source June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 8/4

10 NAND Flash Memory Organization Page & Block small page page = (52 + 6) Byte: Program/Read Unit block = 32 page: Erase Unit June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 9/4

11 NAND Flash Memory Applications Source: Flash Memory Summit 2 (Samsung) June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong /4

12 A Price Challenge of Flash Memory To overcome the price challenge, we have to reduce the cost. To reduce the cost, we have to increase memory density. Source: Flash Summit 29 (Sandisk) June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong /4

13 How can we increase Memory Density? The primary technique for increasing the memory density is to reduce the size of the memory cell (scaling). Another approach to improving memory density is to increase the number of possible states in a cell (multi-leveling). Multilevel storage has a lower tolerance for disturbance of the stored data (e.g., data retention) than conventional Flash, and thus will most likely require some form of error correction in the system or will be used in loss tolerant applications (e.g. MP3 Player) for the higher bit/cell densities. Or use new architecture (3D Memory) or new memory. Scaling/Multi-leveling Benefit: Cost Down Challenge: Reliability/Speed Degradation Solutions: Material, Process, Circuit Design, Signal Processing June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 2/4

14 Evolution of NAND Flash Technology (Scaling) Source: 2 IEEE International Memory Workshop (Kinam Kim, Technology Challenges for Deep-Nano Semiconductor), pp.-2, May 6-9, 2. June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 3/4

15 Multi-leveling: Vth Distribution # of Cells # of Cells Erase State Program State Vth Erase State Program States Vth SLC (Single Level Cell): -bit/cell MLC (Multi Level Cell): 2-bit/cell June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 4/4

16 Do we have a solution? Reliability Issues Endurance / Retention: f (Vth Distribution, ) Data Integrity: Target BER (bit error rate) = f (application, raw BER) Raw BER = f (Vth Distribution) Vth Distribution = f (Oxide Degradation, Charge Loss, Coupling, Disturb, ) Program/Read Performance Issues Program/Read Schemes NAND Interface / Host Interface Solutions: NAND Level & System Level Solution Material, Process, and Circuit Design [NAND] + Signal Processing Algorithms System: Card/SSD Host Controller NAND June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 5/4

17 Error Control Codes for Memories: Error Detection/Correction Codes

18 Communication System vs. Storage System Source Source Encoder Encryption ECC Encoder Modulation Data Text Voice/Audio Image Moving Pictures Graphics Huffman CELP AAC JPEG MPEG DES (Data Encryption Standard) AES (Advanced Encryption Standard) RSA (Rivest/Shamir/Adleman) Feedback Channel Impairments Interference Noise Channel (Air/Wire, Storage) Sink (User) Source Decoder Decryption ECC Decoder Demodulation Source Coding Cryptography Channel Coding June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 7/4

19 System Limitation vs. Channel Solution (Transmission) Power Limited System: Deep Space Communication Use Error Correction Codes Advantage: Coding Gain Disadvantage: increasing Bandwidth & Overhead (Parity) Bandwidth Limited System Use High Transmission Power or High Level Modulation Power & Bandwidth Limited System: Telephone Use Coded Modulation June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 8/4

20 Error Control Codes Error Control Protocols/Codes Design FEC (Forward Error Correction) using Error Correction Codes Block Codes: Hamming, BCH, RS, LDPC, etc. Algebraic Codes Tree Codes: Convolutional Codes, Trellis Codes, etc. Concatenated Codes Coded Modulation Soft-decision decoding, iterative decoding ARQ (Automatic Repeat request) using Error Detection Codes Parity Check Codes: even parity check codes, odd parity check codes CRC (Cyclic Redundancy Check) Codes Hybrid-ARQ: FEC + ARQ June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 9/4

21 Examples of ECC for DRAM For DRAM Core: Error Correction Codes FEC Scheme For DRAM Interface: Error Detection Codes ARQ Scheme ECC Techniques for DRAM Core On-chip ECC: (32, 8) SEC-DED modified Hamming code (odd-parity) 32 data bits + 8 parity bits On-chip ECC: (28, 9) SEC-DED Odd-weight Hamming Code (interleaved?) 28 data bits + 9 parity bits On-chip ECC: double-bit/word-line soft errors Augmented Product Code (APC) Remarks single bit correction -Mbit Cache DRAM Feb. 99 single bit correction 6-Mbit DRAM Oct. 99 double bit correction Nov. 992 (988, 993) SEC/DED (single-error-correcting/double-error-detecting) codes: Hamming codes. SEC/DED/SbED (single-error-correcting/double-error-detecting/single b-bit byte error-detecting) SbEC/DbED (single b-bit byte error correcting/double b-bit byte error-detecting) codes: RS codes or BCH codes over GF (2 b ). June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 2/4

22 Examples of ECC for NAND Flash For NAND Core: Error Correction Codes FEC Scheme BCH, LDPC, etc. For End-to-End Data Integrity: Error Detection Codes ARQ Scheme CRC, etc. System: Card/SSD Host Controller NAND BER < - BER < -2 An Error Detection Code An Error Correction Code June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 2/4

23 A Classification of ECC ECC (Channel Codes) BLOCK CODES (Algebraic Codes) TREE CODES - Hamming Codes [95] - Cyclic Codes: BCH, RS [96] - Reed-Muller Codes [954] - LDPC Codes [962, 995] Soft-Decision Decoding Iterative Decoding - Convolutional Codes [955] * Linear / Nonlinear * Binary / Nonbinary * Systematic/Nonsystematic CONCATENATED CODES [966] - Block + Block - Block + Tree - Tree + Tree: Turbo Codes [993] Coded Modulation - TCM [982] - BCM (Block Coded Modulation) June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 22/4

24 Selection of a Coding Scheme The system factors that affect the choice of a coding scheme are data: structure, the nature of the information (error status/type) and the resulting error-rate requirements (target decoded error-rate), the data rate and any realtime processing requirements channel: power and bandwidth constraints and the nature of the noise mechanisms (error profile) specific user constraints: cost limitations. One further factor that affects choice of a coding scheme is prejudice or, as it is more kindly known, familiarity. The goal of channel code design is to find a code that is easy to encode and decode, and at the same time gives a high code rate for the largest minimum distance. June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 23/4

25 ECC: Code Design (Parameters) Codeword length: n = k + r, where k = message size (dimension) & r = parity size Code Rate: R = k / n Minimum distance: d min min d c, c ci, c j C c c i j i j n k r message parity Any two codewords differ in at least d min places Error Correcting Capability: t A Systematic Code s d s t min 2t when t s t dmin 2 t d min t June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 24/4

26 Decoding Principles Decoding Principles When a received word is decoded, the output is correct or false, or no decision can be made. These outputs may be defined as correct decoding (correctable/detectable error), false decoding (miscorrection/misdetection) and decoding failure (uncorrectable) respectively. June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 25/4

27 ECC Encoding: An Example Data + Redundancy: Increase Minimum Distance Error Detection and/or Correction Data Codeword = Data + Redundancy Encoding (Rule) Choose 2 3 as codewords among 2 4 possible combinations * Rule: represented by polynomial or matrix, or graph, etc. June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) 26/4 J. J. Kong

28 ECC Decoding: An Example ECC Decoding: Received (Read) Data = Distance = Distance = Distance = 3 Distance = Distance = 3 Distance = Distance = 3 Distance = 3 Error Detection!!! Most Probable Errors:,,, detectable but uncorrectable! June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) 27/4 J. J. Kong

29 ECC: BCH/RS Code BCH (Bose-Chaudhuri-Hocquenghem) Code A BCH code is a multilevel, cyclic, variable-length error-correcting code used to correct multiple random error patterns. Generator Polynomial: lcm of 2t consecutive minimal polynomials RS (Reed-Solomon) Code An RS code can be considered as a special case of BCH codes Generator Polynomial g( x) lcm M ( x), M ( x),..., M ( x) 2t g( x) ( x j b b b 2t js ) June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 28/4

30 ECC: BCH Code Encoding Parities are generated and concatenated with messages by Galois Field divider. nk c( x) x m( x) p( x) p(x) nk p( x) x m( x) mod g( x) c(x) m(x) p, p,, p n-k- m, m,, m k- June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 29/4

31 ECC: BCH Code Decoding Decoding Procedure. Syndrome Calculation 2. Determine the Error Location 3. If errors > t, decoding failure! 4. Estimate Error Values 5. Error Correction Syndrome Calculation S i i i ib r( ) c( ) e( ) i i i Q( ) g( ) e( ) i e( ), b i b 2t June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 3/4

32 ECC: LDPC Code Approaching the Shannon limit within.45db Low-Density Parity-Check (LDPC) codes are defined by a parity-check matrix Hc T T c : codeword, H : parity-check matrix Small number of non-zero terms (sparse) in the parity-check matrix H = a b c d e f g a cycle A B C D A B C D a b c d e f g parity-check matrix Tanner (bipartite) graph Check nodes and variable nodes denote columns and rows in H, respectively. June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 3/4

33 ECC: LDPC Code Decoding Iterative Decoding Algorithm Message Passing Algorithm: Sum Product Algorithm, Min Sum Algorithm CN VN Initialization (VN) check node update variable node update Check Hc T T stop or check node update June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 32/4

34 CRC (Cyclic Redundancy Check) Code: Primitive Polynomial A primitive polynomial with degree n is an irreducible polynomial whose period is 2 n -, i.e. maximum possible length. A polynomial is said to be irreducible if it cannot be factored into nontrivial polynomials over the same field. n irreducible polynomials primitive polynomials + x, x + x 2 + x + x 2 + x + x x + x 3, + x 2 + x 3 + x + x 3, + x 2 + x x + x 4, + x + x 2 + x 3 + x 4, + x 3 + x 4 + x + x 4, + x 3 + x x 2 + x 5, + x + x 2 + x 3 + x 5, + x 3 + x 5, + x + x 3 + x 4 + x 5, + x 2 + x 3 + x 4 + x 5, + x + x 2 + x 4 + x 5 + x 2 + x 5, + x + x 2 + x 3 + x 5, + x 3 + x 5, + x + x 3 + x 4 + x 5, + x 2 + x 3 + x 4 + x 5, + x + x 2 + x 4 + x 5 Period of + x + x 2 + x 3 + x 4 (irreducible but not primitive): x 5 = (x )( + x + x 2 + x 3 + x 4 ) 5 June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 33/4

35 CRC Code: Preliminary The CRC Code Generator Polynomial: g( x) = x a + Px P(x): a primitive polynomial with degree n The degree of g(x) = n + a, (a and n > a) The length of CRC = The degree of g(x) = n + a The period of P(x) = 2 n - (maximum length sequence) The period of g(x) = period of (x a + ) period of P(x) = period of (x a + ) (2 n - ) < 2 n+a - The length of codeword = degree of codeword polynomial Coefficients in GF(2): binary field (x a + ) is primitive only when a = ( period of (x + ) = ). June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 34/4

36 CRC Code: LFSR LFSR (Linear Feedback Shift Register) n j g( x) = c jx where c cn j= External Type Critical path! c c c n- x x 2 2 x 3 x n Internal Type Fanout! c c 2 c n- x + x 2 + x 3 + x n June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 35/4

37 CRC Generation The CRC of the data is computed by finding the remainder when the data polynomial d(x) is divided by the generator polynomial g(x). * Remark: Appending the remainder bits to the input message bits has the effect of premultiplying d(x) by x n and then dividing by g(x). Where n is the degree of generator polynomial. d d d 2 If d( x) d x d x d x d x then d n d n d n d n2 n x d( x) d x d x d x d x x 2 2 d n n-bits shift left c(x) = x n d(x) + r(x) = q(x) g(x) x n d(x) = q(x) g(x) + r(x) c(x): codeword polynomial, d(x): message polynomial r(x): remainder polynomial (degree = n - n bits) g(x): generator polynomial (degree = n CRC = n bits), q(x): quotient polynomial June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 36/4

38 CRC Code: Error Detection by CRC Checking e(x) = c (x) c(x) = {q (x) g(x) + r (x)} q(x) g(x) = {q (x) - q(x)} g(x) + r (x) = Q(x) g(x) + r (x) r (x) = : no errors in channel or detection fail r (x) : detect errors in channel c (x): received codeword polynomial e(x): error polynomial r (x): remainder of error polynomial June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 37/4

39 CRC Code: Error Detection Capability (/2) Theorem : All single-bit errors will be detected by any code whose generator polynomial has more than one term. Theorem 2: All cases of an odd number of bits in error will be detected by a code whose generator polynomial has (x a + ), where a is greater than zero, as a factor. Theorem 3: A code will detect all single- and double-bit errors if the degree of codeword polynomial is no greater than the period of the generator polynomial. Theorem 4: A code will detect all single-, double-, and triple-bit errors if its generator polynomial is of the form (x a + ) P(x) and the degree of codeword polynomial is no greater than the period of the generator polynomial. June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 38/4

40 CRC Code: Error Detection Capability (2/2) Theorem 5: A CRC code of degree (n + a) with non-zero constant term can always detect a single burst error of length no greater than (n + a). Note that a burst of length b is defined as any error pattern for which the number of bits between and including the first and last bits in error is b. (the length of burst error = the degree of error polynomial ) Theorem 6: A code with a generator polynomial of the form (x a + ) P(x) has a guaranteed double-burst detection capability provided the degree of codeword is no greater than the period of the generator polynomial. It will detect any combination of double bursts when the length of the shorter burst is no greater than the degree of P(x) and the sum of the burst lengths is no greater than (a + ). June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 39/4

41 CRC Code: Error Detection Capability (An Example) [Theorem 5] Undetected Probability of CRC Codes for Single Burst Error (degree of CRC generator polynomial: r = n + a, burst error size: b) ) b r : undetected probability = 2) b = r + : undetected probability = 2 r 3) b > r + : undetected probability = 2 -r CRC-CCITT (CRC6): g(x) = (x + )(x 5 + x 4 + x 3 + x 2 + x 4 + x 3 + x 2 + x + ) degree = 6, length of data sequence = For block length = length of (data + CRC parity) ) Odd number of bit errors: % detected [Theorem 2] 2) Single-, double-, triple-bit errors: % detected [Theorem 4] 3) [Theorem 5] Single burst error with span 6-bit: % detected Single burst error with span = 7-bit: % detected undetected probability = Single burst error with span 8-bit: % detected undetected probability =.53-5 June 22, 2 (Education Purpose Only, The 2th Korea Test Conference) J. J. Kong 4/4

42 Question & Comment Thank you!

Cyclic Codes. Saravanan Vijayakumaran August 26, Department of Electrical Engineering Indian Institute of Technology Bombay

Cyclic Codes. Saravanan Vijayakumaran August 26, Department of Electrical Engineering Indian Institute of Technology Bombay 1 / 25 Cyclic Codes Saravanan Vijayakumaran sarva@ee.iitb.ac.in Department of Electrical Engineering Indian Institute of Technology Bombay August 26, 2014 2 / 25 Cyclic Codes Definition A cyclic shift