Outline. EECS150 - Digital Design Lecture 26 Error Correction Codes, Linear Feedback Shift Registers (LFSRs) Simple Error Detection Coding

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1 Outline EECS150 - Digital Design Lecture 26 Error Correction Codes, Linear Feedback Shift Registers (LFSRs) Error detection using arity Hamming code for error detection/correction Linear Feedback Shift Registers Theory and ractice Nov 21, 2002 John Wawrzynek Fall 2002 EECS150 Lec26-ECC Page 1 Fall 2002 EECS150 Lec26-ECC Page 2 Error Correction Codes (ECC) Memory systems generate errors (accidentally flied-bits) DRAMs store very little charge er bit Soft errors occur occasionally when cells are struck by alha articles or other environmental usets. Less frequently, hard errors can occur when chis ermanently fail. Where erfect memory is required servers, sacecraft/military comuters, Memories are rotected against failures with ECCs Extra bits are added to each data-word extra bits are used to detect and/or correct faults in the memory system in general, each ossible data word value is maed to a unique code word. A fault changes a valid code word to an invalid one - which can be detected. Fall 2002 EECS150 Lec26-ECC Page 3 Simle Error Detection Coding Parity Bit Each data value, before it is written to memory is tagged with an extra bit to force the stored word to have even arity: b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 + Each word, as it is read from memory is checked by finding its arity (including the arity bit). b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 A non-zero arity indicates an error occurred: two errors (on different bits) is not detected (nor any even number of errors) odd numbers of errors are detected. Fall 2002 EECS150 Lec26-ECC Page 4 + c

2 Hamming Error Correcting Code Use more arity bits to inoint bit(s) in error, so they can be corrected. Examle: Single error correction (SEC) on 4-bit data use 3 arity bits, with 4-data bits results in 7-bit code word 3 arity bits sufficient to identify any one of 7 code word bits overla the assignment of arity bits so that a single error in the 7-bit work can be corrected Grou arity bits so they corresond to subsets of the 7 bits: 1 rotects bits 1,3,5,7 2 rotects bits 2,3,6,7 3 rotects bits 4,5,6, d 2 d 4 Bit osition number 001 = = 3 1 = = 7 0 = = 3 1 = = 7 0 = 4 1 = 5 1 = = 7 Fall 2002 EECS150 Lec26-ECC Page d 2 d 4 Hamming Code Examle Note: arity bits occuy ower-oftwo bit ositions in code-word. On writing to memory: arity bits are assigned to force even arity over their resective grous. On reading from memory: check bits (c 3,c 2,c 1 ) are generated by finding the arity of the grou and its arity bit. If an error occurred in a grou, the corresonding check bit will be 1, if no error the check bit will be 0. check bits (c 3,c 2,c 1 ) form the osition of the bit in error. Examle: c = c 3 c 2 c 1 = 1 error in 4,5,6, or 7 (by c 3 =1) error in 1,3,5, or 7 (by c 1 =1) no error in 2, 3, 6, or 7 (by c 2 =0) Therefore error must be in bit 5. Note the check bits oint to 5 By our clever ositioning and assignment of arity bits, the check bits always address the osition of the error! c=000 indicates no error Fall 2002 EECS150 Lec26-ECC Page 6 Hamming Error Correcting Code Overhead involved in single error correction code: let be the total number of arity bits and d the number of data bits in a + d bit word. If error correction bits are to oint to the error bit ( + d cases) lus indicate that no error exists (1 case), we need: 2 >= + d + 1, thus >= log( + d + 1) for large d, aroaches log(d) Adding on extra arity bit covering the entire word can rovide double error detection d 2 d 4 4 On reading the C bits are comuted (as usual) lus the arity over the entire word, P: C=0 P=0, no error C!=0 P=1, correctable single error C!=0 P=0, a double error occurred C=0 P=1, an error occurred in 4 bit Tyical modern codes in DRAM memory systems: 64-bit data blocks (8 bytes) with 72-bit code words (9 bytes). Fall 2002 EECS150 Lec26-ECC Page 7 Linear Feedback Shift Registers (LFSRs) These are n-bit counters exhibiting seudo-random behavior. Built from simle shift-registers with a small number of xor gates. Used for: seudo-random number generation counters error checking and correction Advantages: very little hardware high seed oeration Examle 4-bit LFSR: Fall 2002 EECS150 Lec26-ECC Page 8

3 4-bit LFSR Circuit counts through different non-zero bit atterns Leftmost bit decides whether the xor attern is used to 10 comute the next value or if the register just shifts left Can build a similar circuit with any number of FFs, may need more xor gates. 11 In general, with n fli-flos, 2 n different non-zero bit atterns (Intuitively, this is a counter that 0001 wras around many times and in a strange way.) Fall 2002 EECS150 Lec26-ECC Page 9 Alications of LFSRs Performance: In general, xors are only ever 2-inut and never connect in series. Therefore the minimum clock eriod for these circuits is: T > T 2-inut-xor + clock overhead Very little latency, and indeendent of n! This can be used as a fast counter, if the articular sequence of count values is not imortant. Examle: micro-code micro-c Can be used as a random number generator. Sequence is a seudorandom sequence: numbers aear in a random sequence reeats every 2 n -1 atterns Random numbers useful in: comuter grahics crytograhy automatic testing Used for error detection and correction CRC (cyclic redundancy codes) ethernet uses them Fall 2002 EECS150 Lec26-ECC Page LFSR circuits erforms multilication on a field. A field is defined as a set with the following: two oerations defined on it: addition and multilication closed under these oerations associative and distributive laws hold additive and multilicative identity elements additive inverse for every element multilicative inverse for every non-zero element Examle fields: set of rational numbers set of real numbers set of integers is not a field Finite fields are called Galois fields. Examle: Binary numbers 0,1 with XOR as addition and AND as multilication. Called GF(2). Consider olynomials whose coefficients come from GF(2). Each term of the form x n is either resent or absent. Examles: 0, 1, x, x 2, and x 7 + x With addition and multilication these form a field: Add : XOR each element individually with no carry: x 4 + x x x x 2 + x x 3 + x Multily : multilying by x n is like shifting to the left. x 2 + x + 1 x + 1 x 2 + x + 1 x 3 + x 2 + x x Fall 2002 EECS150 Lec26-ECC Page 11 Fall 2002 EECS150 Lec26-ECC Page 12

4 These olynomials form a Galois (finite) field if we take the results of this multilication modulo a rime olynomial (x). A rime olynomial is one that cannot be written as the roduct of two non-trivial olynomials q(x)r(x) Perform modulo oeration by subtracting a (olynomial) multile of (x) from the result. If the multile is 1 this corresonds to XOR-ing the result with (x). For any degree, there exists at least one rime olynomial. With it we can form GF(2 n ) Additionally, Every Galois field has a rimitive element, α, such that all non-zero elements of the field can be exressed as a ower of α. By raising α to owers (modulo (x)), all non-zero field elements can be formed. Certain choices of (x) make the simle olynomial x the rimitive element. These olynomials are called rimitive, and one exists for every degree. For examle, x 4 + x + 1 is rimitive. So α = x is a rimitive element and successive owers of α will generate all non-zero elements of GF(16). Examle on next slide. Fall 2002 EECS150 Lec26-ECC Page 13 α 0 = 1 α 1 = x α 2 = x 2 α 3 = x 3 α 4 = x + 1 α 5 = x 2 + x α 6 = x 3 + x 2 α 7 = x 3 + x + 1 α 8 = x α 9 = x 3 + x α = x 2 + x + 1 α 11 = x 3 + x 2 + x α 12 = x 3 + x 2 + x + 1 α 13 = x 3 + x α 14 = x α 15 = 1 Note this attern of coefficients matches the bits from our 4-bit LFSR examle. α 4 = x 4 mod x 4 + x + 1 = x 4 xor x 4 + x + 1 = x + 1 In general finding rimitive olynomials is difficult. Most eole just look them u in a table, such as: Fall 2002 EECS150 Lec26-ECC Page 14 x 2 + x +1 x 3 + x +1 x 4 + x +1 x 5 + x 2 +1 x 6 + x +1 x 7 + x 3 +1 x 8 + x 4 + x 3 + x 2 +1 x 9 + x 4 +1 x + x 3 +1 x 11 + x 2 +1 Primitive Polynomials x 12 + x 6 + x 4 + x +1 x 13 + x 4 + x 3 + x +1 x 14 + x + x 6 + x +1 x 15 + x +1 x 16 + x 12 + x 3 + x +1 x 17 + x x 18 + x x 19 + x 5 + x 2 + x+ 1 x 20 + x x 21 + x x 22 + x +1 x 23 + x 5 +1 x 24 + x 7 + x 2 + x +1 x 25 + x 3 +1 x 26 + x 6 + x 2 + x +1 x 27 + x 5 + x 2 + x +1 x 28 + x x 29 + x +1 x 30 + x 6 + x 4 + x +1 x 31 + x x 32 + x 7 + x 6 + x 2 +1 Galois Field Hardware Multilication by x shift left Taking the result mod (x) XOR-ing with the coefficients of (x) when the most significant coefficient is 1. Obtaining all 2 n -1 non-zero Shifting and XOR-ing 2 n -1 times. elements by evaluating x k for k = 1,, 2 n -1 Fall 2002 EECS150 Lec26-ECC Page 15 Building an LFSR from a Primitive Polynomial For k-bit LFSR number the fli-flos with FF1 on the right. The feedback ath comes from the Q outut of the leftmost FF. Find the rimitive olynomial of the form x k The x 0 = 1 term corresonds to connecting the feedback directly to the D inut of FF 1. Each term of the form x n corresonds to connecting an xor between FF n and n+1. 4-bit examle, uses x 4 + x + 1 x 4 FF4 s Q outut x xor between FF1 and FF2 1 FF1 s D inut To build an 8-bit LFSR, use the rimitive olynomial x 8 + x 4 + x 3 + x and connect xors between FF2 and FF3, FF3 and FF4, and FF4 and FF5. Q8 Q7 Q6 Q5 Fall 2002 EECS150 Lec26-ECC Page 16

5 Error Correction with LFSRs message bits 4 check bits bit sequence: Fall 2002 EECS150 Lec26-ECC Page 17 serial_in Error Correction with LFSRs XOR with incoming bit sequence. Now values of shift-register don t follow a fixed attern. Deendent on inut sequence. Look at the value of the register after 15 cycles: Note the length of the inut sequence is = 15 (same as the number of different nonzero atters for the original LFSR) Binary message occuies only 11 bits, the remaining 4 bits are They would be relaced by the final result of our LFSR: If we run the sequence back through the LFSR with the relaced bits, we would get 0000 for the final result. 4 arity bits, neutralize the sequence with resect to the LFSR If arity bits not all zero, an error occurred in transmission. If number of arity bits = log total number of bits, then single bit errors can be corrected. Using more arity bits allows more errors to be detected. Ethernet uses 32 arity bits er frame (acket) with 16-bit LFSR. Fall 2002 EECS150 Lec26-ECC Page 18