CA3162. A/D Converters for 3-Digit Display. Features. Description. Ordering Information. Pinout FN April 2002

Transcription

1 CA April 00 A/D Converters for -Digit Disply Fetures Dul Slope A/D Conversion Multiplexe BCD Disply Ultr Stble Internl Bn Gp Voltge Reference Cpble of Reing mv Below Groun with Single Supply Differentil Input Internl Timing - No Externl Clock Require Choice of Low Spee (Hz) or High Spee (Hz) Conversion Rte Hol Inhibits Conversion but Mintins Dely Overrnge Iniction - EEE for Reing Greter thn +mv, - for Reing More Negtive thn -mv When Use With CAE Description The CAE n CAAE re I L monolithic A/D convertersthtprovieigitmultiplexebcdoutput. They re use with the CAE BCD-to-Seven-Segment Decoer/Driver n minimum of externl prts to implement complete -igit isply. The CAAE is ienticl to the CAE except for n extene operting temperture rnge. The CAE is escribe in the Disply Drivers section of this t book. Orering Informtion PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. NO. CAE 0 to 0 L PDIP E. Pinout CA (PDIP) TOP VIEW BCD 0 BCD NSD SELECT MSD LSD HOLD/ BYPASS 0 ADJ INTEGRATING CAP HIGH INPUT LOW INPUT ZERO ADJ ZERO ADJ CAUTION: These evices re sensitive to electrosttic ischrge; follow proper IC Hnling Proceures. --INTERSIL or -- Intersil (n esign) is registere tremrk of Intersil Americs Inc. Copyright Intersil Americs Inc. 00. All Rights Reserve FN00.

2 CA Functionl Block Digrm ZERO ADJ INTEGRATING CAP BCD 0 CONTROL LOGIC COUNTERS AND MULTIPLEX DRIVE SELECT =MSD HIGH INPUT V/I THRESHOLD DET. =LSD =NSD LOW INPUT 0 CONVERTER 0 REFERENCE CURRENT GENERATOR BAND GAP REFERENCE OSC HOLD/ BYPASS GATES CONVERSION CONTROL MSD = MOST SIGNIFICANT NSD = NEXT SIGNIFICANT LSD = LEAST SIGNIFICANT ADJ

3 CA Absolute Mximum Rtings DCSupplyVoltge(BetweenPinsn)...+V InputVoltge(Pin0ortoGroun)... ±V Operting Conitions Temperture Rnge CAE...0to o C Therml Informtion Therml Resistnce (Typicl, Note ) θ JA ( o C/W) PDIPPckge... 0 MximumJunctionTemperture...0 o C MximumStorgeTempertureRnge...- o Cto0 o C MximumLeTemperture(Solering0s)...00 o C CAUTION: Stresses bove those liste in Absolute Mximum Rtings my cuse permnent mge to the evice. This is stress only rting n opertion of the evice t these or ny other conitions bove those inicte in the opertionl sections of this specifiction is not implie. NOTE:. θ JA is mesure with the component mounte on low effective therml conuctivity test bor in free ir. See Tech Brief TB for etils.. Electricl Specifictions T A = o C, = V, Zero Pot Centere, Gin Pot =., Unless Otherwise Specifie PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Operting Supply Voltge Rnge,.. V Supply Current, I+ 00 to on Pins,, - - ma Input Impence, Z I MΩ Input Bis Current, I IB Pins 0 n na Unjuste Zero Offset V -V 0 = 0V, Re Decoe Output mv Unjuste Gin V -V 0 = 00mV, Re Decoe Output - mv Linerity Notes n Count Conversion Rte Slow Moe Pin = Open or - - Hz FstMoe Pin=V - - Hz Conversion Control Voltge (Hol Moe) t Pin 0... V Common Moe Input Voltge Rnge, V ICR Notes, V BCD Sink Current t Pins,,, V BCD 0.V, t Logic Zero Stte ma Digit Select Sink Current t Pins,, V Select = V t Logic Zero Stte.. - ma Zero Temperture Coefficient V I =0V,ZeroPotCentere µv/ o V Gin Temperture Coefficient V I = 00mV, Gin Pot = %/ o C NOTES:. Apply 0V cross V to V 0. Ajust zero potentiometer to give 000mV reing. Apply 00mV to input n just gin potentiometer to give 00mV reing.. Linerity is mesure s ifference from stright line rwn through zero n positive full scle. Limits o not inclue ±0. count bit igitizing error.. For pplictions where low input pin 0 is not operte t pin potentil, return pth of not more thn 00 resistnce must be provie for input bis currents.. The common moe input voltge bove groun cnnot excee +0.V if the full input signl rnge of mv is require t pin. Tht is, pin my not operte higher thn.v positive with respect to groun or 0.V negtive with respect to groun. If the mximum input signl is less thn mv, the common moe input voltge my be rise ccoringly.

4 CA Timing Digrm PIN NUMBER (LSD) (MSD) (NSD) Detile Description ms/div. FIGURE. HIGH SPEED MODE 00mV 00mV 00mV 00mV The Functionl Block Digrm of the CAE shows the V/I converter n reference current genertor, which is the hert of the system. The V/I converter converts the input voltge pplie between pins 0 n to current tht chrges the integrting cpcitor on pin for preetermine time intervl. At the en of the chrging intervl, the V/I converter is isconnecte from the integrting cpcitor, n bn gp reference constnt current source of opposite polrity is connecte. The number of clock counts tht elpse before the chrge is restore to its originl vlue is irect mesure of the signl inuce current. The restortion is sense by the comprtor, which in turn ltches the counter. The count is then multiplexe to the BCD outputs. The timing for the CAE is supplie by Hz ring oscilltor, n the input t pin etermines the smpling rte. A V input provies high spee smpling rte (Hz), n grouning or floting pin provies low spee (Hz) smpling rte. When pin is fixe t +.V (by plcing K resistor between pin n the +V supply) hol feture is vilble. While the CAE is in the hol moe, smpling continues t Hz but the isply t re ltche to the lst reing prior to the ppliction of the.v. Removl of the.v restores continuous isply chnges. Note, however, tht the smpling rte remins t Hz. Figure shows the timing of smpling n igit select pulses for the high spee moe. Note tht the bsic A/D conversion process requires pproximtely ms in both moes. The EEE or --- isplys inicte tht the rnge of the system hs been exceee in the positive or negtive irection, respectively. Negtive voltges to -mv re isplye with the minus sign in the MSD. The BCD coe is 00 for negtive overrnge (---) n 0 for positive overrnge (EEE). NOTE NOTE +V NORMAL LOW SPEED MODE: V = GROUND OR OPEN HOLD: V =.V HIGH SPEED MODE: V =V 0.µF 0. µf COMMON ANODE LED DISPLAYS MSD NSD LSD f b g e c f b g e c e f POWER N0, N0 OR EQUIV. b g c CAE DRIVERS BCD CAE INPUTS HIGH LOW 0 ADJ 0 0 CAE PINS,, R 0Ω CAE PINS,,, R 0Ω R 0Ω NOTES:. The cpcitor use here must be low ielectric bsorption type such s polyester or polystyrene type.. This cpcitor shoul be plce s close s possible to the power n groun Pins of the CAE. DRIVER Ω BCD SEGMENT DRIVERS FIGURE. BASIC AL READOUT SYSTEM USING THE CAE AND THE CAE

5 CA CAE Liqui Crystl Disply (LCD) Appliction Figure shows the CAE in typicl LCD ppliction. LCDs my be use in fvor of LED isplys in pplictions requiring lower power issiption, such s bttery-operte equipment, or when visibility in high-mbient-light conitions is esire. Multiplexing of LCD igits is not prcticl, since LCDs must be riven by n AC signl n the verge voltge cross ech segment is zero. Three CD0B liqui-crystl ecoer/rivers re therefore use. Ech CD0B contins n input ltch so tht the BCD t for ech igit my be ltche into the ecoer using the inverte igit-select outputs of the CAE s strobes. The cpcitors on the outputs of inverters G n G filter out the ecoe spikes on the MSD n NSD signls. The cpcitors n pull-up resistors connecte to the MSD, NSD n LSD outputs re there to shorten the igit rive signl thereby proviing proper timing for the CD0B ltches. Inverters G n G re use s n stble multivibrtor to provie the AC rive to the LCD bckplne. Inverters G, G n G re the igit-select inverters n require pull-up resistors to interfce the open-collector outputs of the CAE to CMOS logic. The BCD outputs of the CAE my be connecte irectly to the corresponing CD0B inputs (using pull-up resistors). In this rrngement, the CD0B ecoes the negtive sign (-) s n L n the positive overlo inictor (E) s n H. The circuit s shown in Figure using G, G n G will ecoe the negtive sign (-) s negtive sign (-), n the positive overlo inictor (E) s H. +V +V 0.0µF G 0.0µF CD0B TO MSD OF LCD 0 HOLD V IN + ZERO CAE 0.µF MSD NSD LSD 0 x 0 0.0µF 0.0 µf G 0.0 µf +V CD0B TO NSD OF LCD V IN x 00 G +V +V G - G: CD0UB HEX INVERTER G, G, G: CD0B TRIPLE INPUT NAND GATE G G G CD0B TO LSD OF LCD TO LCD BACKPLANE 00 0.µF FIGURE. TYPICAL LCD APPLICATION

6 CA CAE Common-Cthoe, LED Disply Appliction Figure shows the CAE connecte to CDB ecoe/river to operte common-cthoe LED isply. Unlike the CAE, the CDB remins blnk for ll BCD coes greter thn nine. After mv the isply blnks rther thn isplying EEE, s with the CAE. When isplying negtive voltge, the first igit remins blnk, inste of (-), n uring negtive or positive overrnge the isply blnks. The itionl logic shown within the otte re of Figure restores the negtive sign (-), llowing the isply of negtive numbers s low s -mv. Negtive overrnge is inicte by negtive sign (-) in the MSD position. The rest of the isply is blnke. During positive overrnge, only segment b of the MSD is isplye. One inverter from the CD0B is use to operte the eciml points. By connecting the inverter input to either the MSD or NSD line either DP or DP will be isplye. DP 00 / CD0UB DP / CD0UB CD0B / CD0UB / CD0UB B CAE D A C B C CDB f LT g BL LE/STROBE b D c A e DP DP c e c c P HP0- OR EQUIVALENT f g b c NSD MSD LSD HOLD INT HIGH 0.µF 0 ZERO LOW 0 ZERO BUFFERS ( CD00B) INPUT 0 FIGURE. TYPICAL COMMON-CATHODE LED APPLICATION