General Aptitude. Q. No. 1 5 Carry One Mark Each
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2 Generl Aptitude Q. No. 5 Crry One Mrk Ech. Five tems hve to compete in legue, with every tem plying every other tem ectly once before going to the net round. How mny mtches will hve to be held to complete the legue round of mtches? (A) (D) 5 For mtch to be plyed, we need tems No. of mtches = No. of wys of selections tems out of 5. Fill in the blnk with the correct idiom/phrse. Tht boy from the town ws in the sleepy villge. (A) dog out of herd fish out of wter 5 C 0 sheep from the hep (D) bird from the flock From the sttement, it ppers tht boy found it tough to dpt to very different sitution. 3. Choose the sttement where underlined word is used correctly. (A) When the techer eludes to different uthors, he is being elusive. When the thief keeps eluding the police, he is being elusive. Mtters tht re difficult to understnd, indentify or remember re llusive. (D) Mirges cn be llusive, but better wy to epress them is illusory. Ans: Elusive: Difficult to nswer. 4. Tny is older thn Eric. Cliff is older thn Tny. Eric is older thn Cliff. If the first two sttements re true, then the third sttement is: Ans: (A) True Flse Uncertin (D) Dt insufficient 5. Choose the pproprite word/phrse, out of the four options given below, to complete the following sentence: Apprent lifelessness dormnt life. (A) hrbours leds to supports (D) ffects (A) Apprent: looks like dormnt: hidden Hrbour: give shelter Effect (verb): results in
3 Q. No. 6 0 Crry Two Mrks Ech 6. A coin tossed thrice. Let X be the event tht hed occurs in ech of the first two tosses. Let Y be the event tht til occurs on the third toss. Let Z be the event tht two tils occurs in three tosses. Bsed on the bove informtion, which one of the following sttements is TRUE? (A) X nd Y re not independent Y nd Z re independent Y nd Z re dependent (D) X nd Z re independent Let y s til occurred in third toss nd z s two tils in third toss which cn be {TTH, THT, HTT} y = {TTH, TTT} both y nd z re dependent. 7. Given below re two sttements followed by two conclusions. Assuming these sttements to be true, decide which one logiclly follows. Sttements: I. No mnger is leder. II. All leders re eecutives. Conclusions: I. No mnger is n eecutive. II. No eecutive is mnger. (A) Only conclusion I follows. Neither conclusion I nor II follows. Only conclusion II follows. (D) Both conclusions I nd II follow. Eecutive L NL Therefore concluding digrm cn be It cn be mnger tht is mnger cn be eecutive lso. Some eecutives re lso leders tht is not mnger
4 8. In the given figure ngle Q is right ngle, PS:QS=3:, RT:QT=5: nd PU:UR=:. If re of tringle QTS is 0 cm, then the re of tringle PQR in cm is. R U T P S Q 80 Let re of tringle PQR be A SQ PQ 3 4 QT QR 5 7 le Are of QTS SQ QT PQ QR 4 7 PQ QR 4 7 Are of 4 given 0cm A 4 A cm le PQR 9. Select the pproprite option in plce of underlined prt of the sentence. Incresed productivity necessry reflects greter efforts mde by the employees. (A) Increse in productivity necessry Increse productivity is necessry Increse in productivity necessrily (D) No improvement required 0. Right tringle PQR is to be constructed in the y-plne so tht the right ngle is t P nd line PR is prllel to the -is. The nd y coordintes of P, Q, nd R re to be integers tht stisfy the inequlities: 4 5 nd 6 y 6. How mny different tringles could be constructed with these properties? (A) 0,00 9,900 (D) 0,000
5 X 4 X 5 Y 6 Y 6 X 9 chirs X X Y 0 chirs Y Y Totl tringles Instrumenttion Engineering Q. No. 5 Crry One Mrk Ech. The cpcitor shown in the figure is initilly chrged to +0 V. The switch closes t time t=0. Then the vlue of V (t) in volts t time t=0 ms is V. c t 0 C F V c(t) R 0k 3.67 It is source free network where cpcitor voltge t Vc t V0e ;t 0 c 0e 00t V 00 0e 3.67V RC 00. The voltge (E 0) developed cross glss electrode for ph mesurement is relted to the temperture (T) by the reltion (A) E0 E o E0 T T T (D) E0 T 3. Let 3+4j be zero of fourth order liner phse FIR filter. The comple number which is NOT zero of this filter is (A) 3 4j (D) 3 4 j j (D) j The property of FIR filter is tht if Z o is zero then the remining zeros re
6 , Z 0 *, * Z0 Z j, 3 4j, j So option (D) is not mtching with ny of this. 4. The bridge most suited for mesurement of four-terminl resistnce in the rnge of 0.00 to 0. is (A) Wien s bridge Mwell s bridge Kelvin double bridge (D) Schering bridge 5. A lod resistor R L is connected to bttery of voltge E with internl resistnce R i through resistnce R s s shown in the figure. For fied vlues of RL nd R i, the vlue of R 0 S for mimum power trnsfer to R L is R i R s E R L (A) 0 RL Ri R L (D) RL Ri (A) When lod is constnt, we should see for wht vlue of resistnce current will be mimum nd m. PR L 6. A mss-spring-dmper system with force s input nd displcement of the mss s output hs trnsfer function G(s) / s 4s 900. A force input F(t)=0 sin(70t) Newtons is pplied t time t = 0s. A bem from n opticl stroboscope is focused on the mss. In stedy stte, the strobe frequency in hertz t which the mss ppers to be sttionry is (A) 5/ 5 / 35 / (D) 50 /
7 7. A light detector circuit using n idel photo-diode is shown in the figure. The sensitivity of the photo-diode is 0.5A / W. With V r = 6V, the output voltge V0.0 for 0 W of incident light. If V r is chnged to 3V, keeping ll other prmeters the sme, the vlue of V o in volts is V. R Incident light V 0 V r - Here V o is independent of the vlue of V r It depends on the intensity of incident light. 8. The logic evluted by the circuit t the output is X Output Y (A) XY YX X YXY XY XY (D) XY XY X Y (A) Output of upper AND gte is XY Output of lower AND gte is XY Output of OR gte is XY XY. 9. The vlue of dz, where the contour is the unit circle trversed clockwise, is z (A) i 0 i Given dz where c is unit circle. z Let f (z) z (D) 4 i
8 f(z) is not nlytic t z = 0 By Lurent series, f(z) cn be epressed s f (z) (zero tens) 0.. z z Anlytic prt Principl prt Principl prt hs only two terms z 0 is pole of order Res f (z) z 0 coefficient of z b 0 By Cuchy s residue theorem dz i (sum of residues) z i Consider the mmeter-voltmeter method of determining the vlue of the resistnce R using the circuit shown in the figure. The mimum possible errors of the voltmeter nd mmeter re known to be % nd % of their redings, respectively. Neglecting the effects of meter resistnces, the mimum possible percentge error in the vlue of R determined from the mesurements, is %. Source V i Voltmeter V R Ammeter 3 V VI% R R 3% I I %. The highest frequency present in the signl (t) is f m. The highest frequency present in the signl (A) f m y(t) (t) is f m f m (D) 4f m Multipliction in time domin corresponds to convolution in frequency domin t f * f Using limit property of convolution (t) hve mimum frequency f m.
9 . Let A be n n n mtri with the rnk r0 r n. Then A=0 hs p independent solutions, where p is (A) r n n-r (D) n+r Given AX=0 A r 0 r n nn p = no. of independent solution i.e nullity = p We know tht rnk + nullity = n r p n p n r 3. The double integrl (A) 0 0 y 0 0 y f (, y) ddy is equivlent to f (, y) ddy f (, y) ddy (D) 0 Given double integrl 0 0 nd =0 to =y, y=0 to y= the digrm is y f (, y)d. dy y 0 y 0 0 f (, y) ddy f (, y) ddy (0,) 0 (,) y By pplying chnge of order of integrtion 0 f (,y)dyd y (0,0) (,0) 4. In the circuit shown, the switch is momentrily closed nd then opened. Assuming the logic gtes to hve non-zero dely, t stedy stte, the logic sttes of X nd Y re X Y
10 (A) X is ltched, Y toggles continuously Y is ltched, X toggles continuously (D) X nd Y re both ltched (D) X nd Y both toggle continuously The bove circuit is stble multivibrtor circuit, where odd numbers of inverter re there in the loop. In such circuit, irrespective of the position of output, it lwys toggles. Ltching mens X nd Y will be fied to sme vlue, in this cse it is not possible. 5. Consider the logic circuit with input signl TEST shown in the figure. All gtes in the figure shown hve identicl non-zero dely. The signl TEST which ws t logic LOW is switched to logic HIGH nd mintined t logic HIGH. The output TEST Output (A) stys HIGH throughout pulses from LOW to HIGH to LOW (D) stys LOW throughout (D) pulses from HIGH to LOW to HIGH For nlysis point of view, ssume dely of ech gte is 0 msec. However we cn tke ny vlue. By referring the circuit the upper input to the NAND gte is direct test signl. The lower input to NAND gte is TEST but with dely of 30 nsec. Assuming the dely of NAND gte is 0. First drw output wveform (idel cse) then shift tht by 0 msec. i.e. introduce the dely. Test 0 Test with dely 30n sec 0 Output with dely nsec Output with NAND gte dely 0 n sec 0 0 nsec 40 nsec
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