Eksamen Invulvraestel Kopiereg voorbehou. Examination Fill in paper Copyright reserved. Vakkursus ERS November 2008
|
|
- Jewel York
- 6 years ago
- Views:
Transcription
1 Departement Elektriese, Elektroniese en Rekenaar-Ingenieurswese Department of Electrical, Electronic and Computer Engineering Eksamen Invulvraestel Kopiereg voorbehou Vakkursus ERS November 2008 Examination Fill in paper Copyright reserved Course ERS November 2008 Student se besonderhede: Student's details: Van (opsioneel): Surname (optional): Voorname (opsioneel): First name (optional): Tel. nr. gedurende toetsreeks: Tel no. during test series: Studentenommer: Student number: Tel. nr. na toetsreeks: Tel. no. after test series: Toetsinligting: Test information: Maksimum punte: Maximum marks: 175 Duur van vraestel: Duration of paper: 3 Hours 3 Ure Totale aantal bladsye (hierdie blad ingesluit): Total numer of pages (including this page): 20 Punt: Mark: Volpunte: Full marks: 170 Open / closed book: Oopboek / toeboek: Closed Toe BELANGRIK- IMPORTANT 1. The examination regulations of the University of Pretoria apply. Die eksamenregulasies van die Universiteit van Pretoria geld. 2. No programmable calculators are allowed. Geen programmeerbaar sakrekenaars word toegelaat nie. 3. No notes are allowed. Geen notas word toegelaat nie. 4. Show all calculations. Toon all berekeninge. 5. Complete all the sections. Voltooi al die afdelings. Internal Examiner(s): Interne Eksaminator(e): S. Reddy External Examiner: Eksterne Eksaminator: D. V. Bhatt 1
2 Section A: Multiple Choice And Short Questions [18] 1. Tick the correct box / Tick die korrekte boks: (12) 1.1. Which statement best describes the behaviour of a Dynamic RAM / Watter verklaring beskryf die gedrag van 'n Dynamic RAM die beste a) Once a word is written at a location, it remains stored as long as power is applied to the baan, unless the same location is written again. / Sodra n woord geskrywe word by n plek, bly dit gestoor so lank as wat krag aangewend wordtot die baan tensy dieselfde opstelling is weer geskryf word. b) Once a word is written at a location, it remains stored as long as power is applied to the baan and even if the same location is written again. / Sodra 'n woord geskrf word by n plek bly dit gestoor so lank as wat krag aangewend word tot die baan selfs indien dieselfde opstellling weer geskrywe word. c) Once a word is written at a location, it remains stored, even after power is removed. / Sodra 'n woord is geskrywe word by 'n opstelling, bly dit gestoor, selfs nadat krag verwyder is. d) The data stored at each location must be refreshed periodically by reading it and then writing it back again, or else it disappears. / Die data gestoor by elke opstelling moet van tyd tot tyd verfris word deur dit te lees en dan terug te skryf, anders verdwyn dit. a b c d 1.2. Which of the following descriptions is not true? A combinational logic function can be represented by a / Watter van die volgende beskrywings is nie waar nie? 'n kombinatoriese logiese funksie kan verteenwoordig word deur 'n a) maxterm list using the Π notation. / maksterme lys deur gebruik te maak van die Π notasie. b) minterm list using the Π notation. / minterme lys deur gebruik te maak van die Π notasie. c) truth table. / waarheidstabel d) Karnaugh map(s). / Karnaugh kaart(e) a b c d 1.3. A sequential device that normally samples its inputs continuously and changes its output anytime is called a / 'n Sekwensiële baan wat normaalweg sy insette versamel aanhoudelik en sy uitsette verander enigetyd is genoem 'n a) flip-flop. / wipbaan. b) latch. / grendel c) latch with enable. / grendel met ontsper d) Either b) or c) / Een van beide b) of c) a b c d ERS 220 Examination
3 1.4. (DDR) SDRAM can double the data rate of SDRAM by / (DDR) SDRAM kan die data tempo van SDRAM verdubbel deur a) transferring data on the rising edge of the clock only. / verplaas data na die stygende rand van die klok alleen. b) transferring data on both edges of the clock, rising and falling. / verplaas data na beide kante van die klok, opstygend en vallend. c) transferring data anytime the clock is positive. / verplaas data enige tyd wat die klok positief is. d) doubling the clock of a standard DRAM and transferring data on the rising edge of the clock only. / verdubbel die horlosie van 'n standaard DRAM en verplaas die data na die stygende rand van die klok alleen. a b c d 1.5. A LSI / IC can contain / n LSI / IC kan bevat a) between 1 and 20 gates. / tussen 1 en 20 hekke. b) between 20 and 100 gates. / tussen 20 en 100 hekke. c) between 100 and 200 gates. / tussen 100 en 200 hekke. d) more than 200 gates. / meer as 200 hekke. a b c d 1.6. Which of the following commercial ROM types can be written to only one time? / Watter van die volgende kommersieël "ROM" tipe kan kan net eenkeer geskryf word? a) PROM b) Mask ROM c) Mask EEPROM d) Both a) and b) / beide a) en b) a b c d 1.7. If a devices input code has fewer bits than the output code, the device is usually called / As n digitale baan se insetkode minder bisse het as die uitsetkode, dan is die baan n a) a decoder. / n dekodeerder. b) an encoder. / n enkodeerder. c) Neither a) nor b) / Ook nie a) nie nog minder b) a b c ERS 220 Examination
4 1.8. Which statement best describes the behaviour of a Static RAM / Watter verklaring beskryf die gedrag van 'n Static RAM die beste a) Once a word is written at a location, it remains stored as long as power is applied to the circuit, unless the same location is written again. / Sodra n woord geskrywe word by n plek, bly dit gestoor so lank as wat krag aangewend wordtot die baan tensy dieselfde opstelling is weer geskryf word. b) Once a word is written at a location, it remains stored, even after power is removed. / Sodra 'n woord is geskrywe word by 'n opstelling, bly dit gestoor, selfs nadat krag verwyder is. c) Once a word is written at a location, it remains stored as long as power is applied to the circuit and even if the same location is written again. / Sodra 'n woord geskrf word by n plek bly dit gestoor so lank as wat krag aangewend word tot die baan selfs indien dieselfde opstellling weer geskrywe word. d) The data stored at each location must be refreshed periodically by reading it and then writing it back again, or else it disappears. / Die data gestoor by elke opstelling moet van tyd tot tyd verfris word deur dit te lees en dan terug te skryf, anders verdwyn dit. a b c d 2. Draw the general structure of a clocked synchronous Mealy state machine with pipelined outputs. / Skets die algemene struktuur van n geklokte sinkrone Mealy toestandsmasjien met pipelined afvoere. (6) ERS 220 Examination
5 Section B: Number Systems And Codes [23] 1. Use 2 s-complement partial product multiplication to multiply the following 6-bit 2 s- Complement numbers. Verify that your answer is correct. / Vermenigvuldig die volgende 6-bis 2 s- Complement getalle deur gebruik te maak van 2 s-complement partial product vermenigvuldig. Verifeer die korrektheid van jou antwoord. (8) ERS 220 Examination
6 2. Add the following numbers using Hexidecimal arithmetic. Show all calculations. / Voeg die volgende nommers gebruik Hexidecimal rekenkunde. Toon almal berekenings. (6) C X 16 C 3 9 B E Y 16 D A 1 F 7 X 16 + Y Convert the following base 8 number to base 16. / Skakel die volgende basis 8 nommer oor na basis 16. (3) ERS 220 Examination
7 4. In a system employing a 7-bit Hamming Code the codeword, , is received. The codeword is arranged in the same sequence as the parity-check matrix below. / In n stelsel wat gebruik maak van n 7-bis Hamming Kode word die volgende kodewoord ontavang, Die kodewoord is in die selfde volgorde as die parity-check matrix hieronder georganiseer Determine the syndrome (position of the error bit) of the codeword. / Bepaal die sindroom (posisie van die vout-bis) van die kodewoord. (4) 4.2. Determine the correct transmitted codeword arranged in same sequence as the parity check matrix above. / Bepaal die korrekte kodewoord wat oorspronklik versend is in die selfde volgorde as die parity-check matrix bo georganiseer. (2) ERS 220 Examination
8 Section C: Digital Circuits [20] 1. The following figure shows a CMOS circuit. / Die volgende figuur toon n CMOS stroombaan Construct a Truth Table (Q = ON or OFF, Z = H or L). / Stel n waarheidstabel saam (Q = ON or OFF, Z = H of L). (8) A B C Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Z ERS 220 Examination
9 2. The following diagram shows the equivalent circuit for analysing transition times of a CMOS output. The typical on resistances of the PMOS transistor is R p = 225 Ω and for the NMOS R n = 115 Ω. The load capacitance of AC load can be modelled as C L = 120pF, the load voltage as V L = 1.7 V, and the load resistance as R L = 650 Ω. Assume GND = 0 V and VDD = 4.7 V. / Die volgende diagram wys die ekwivalente stroombaan om die transisie tye van 'n CMOS uitset te analiseer. Die tipiese aan weerstand van die PMOS transistor is R p = 225Ω en vir die NMOS R n = 115Ω. Die las kapasitansie van die AC las kan beskou word as C L = 120pF, die las spanning as V L = 1.7 V, en die las weerstand as R L = 650 Ω. Aanvaar GND = 0 V en VDD = 4.7 V Determine the Thevenin equivalent of the Voltage (V Thev ), Current (I Thev ) and Resistance (R Thev ) in the LOW state. N.B. R L 0 Ω and V L 0 V. / Bepaal diethevenin ekwivalente van die Spanning (V Thev ), Huidige (I Thev ) en Weerstand (R Thev ) in die LAAG toestand. (6) V Thev I Thev R Thev V ma Ω ERS 220 Examination
10 2.2. Determine the Thevenin equivalent of the Voltage (V Thev ), Current (I Thev ) and Resistance (R Thev ) in the HIGH state. N.B. R L 0 Ω and V L 0 V. / Bepaal diethevenin ekwivalente van die Spanning (V Thev ), Huidige (I Thev ) en Weerstand (R Thev ) in die HOOG toestand. (6) V Thev I Thev R Thev V ma Ω ERS 220 Examination
11 Section D: Combinational Logic Design Principles [15] 1. For the sum-of-products function H below, use the Karnaugh maps to derive the minimum sumof-products expression. / Vir die som-van-produkte funksie H hieronder, gebruik die Karnaugh diagram om af te lei die minimum som-van-produkte uitdrukking aft te lei. (15) H = ΣABCD ABCDEF EF(9, 12, 14, 15, 28, 29, 31, 37, 39, 44, 46, 47, 53, 55, 56, 57, 58, 60, 61, 62) + d (1, 3, 6, 7, 8, 13, 17, 19, 24, 25, 30, 33, 35, 42, 45, 59, 63) H = ERS 220 Examination
12 Section E: Combinational Logic Design Practices [20] 1. Given the following Boolean function / Gegee die volgende Boolse funksie F = ΠABCDE ABCDE (0, 3, 5, 6, 8, 9, 14, 15, 16, 19, 21, 22, 24, 27, 29, 30) Implement function F using one 74x151 MUX, one 74x138 decoder, one inverting gate and one multiple input NAND gate. / Implementeer die funksie F deur gebruik te maak van n enkele 74x151 MUX, enkele 74x138 dekodeerder, een omkerende hek en een meervoudige inset NEN hekke. (20) A B C D E F ERS 220 Examination
13 ERS 220 Examination
14 Section F: Sequential Logic Design Principles [44] 1. The following figure shows a clocked synchronous state machine. / Die volgende figuur toon n geklode sinkrone toestandsmasjien Determine the transition and output equations. / Bepaal die oordrag en uitset vergelykings. (10) Q1* = Q2* = Q3* = MAX = ERS 220 Examination
15 1.2. Compile the transition/ output table. / Stel die oordrag/ uitset tabel op. (8) Q1 Q2 Q EN 0 1 Q1* Q2* Q3*, MAX Useful Expressions / Nuttige Uitdrukkings Flip-Flop Characteristic Equations / Wipbaan Karaktertrek Vergelyking Edge Triggered D Flip-Flop Q* = D Edge Triggered D Flip-Flop with Enable Q* = EN. D + EN. Q Edge Triggered T Flip-Flop Q* = Q Edge Triggered T Flip-Flop with Enable Q* = EN. Q + EN. Q ERS 220 Examination
16 2. The following figure shows a state diagram of a clocked synchronous state machine. / Die volgende figuur toon n toestandsdiagram van n geklokde sinkrone toestandsmasjien. Y A Z1Z2 = 00 Y B Z1Z2 = 10 Y X.Y.Y Y Y D Z1Z2 = 01 X Y E X.Y C X Z1Z2 = 10 Z1Z2 = 01 X 2.1. What type of machine is represented by the above state diagram? / Watter soort masjien is verteenwoordig by die boonste toestandsdiagram? (2) ERS 220 Examination
17 2.2. Compile the state/ output table. / Stel die toestand/ uitset tabel saam. (8) S A B C D E XY S* Z1Z Compile the transition/ output table. / Stel die oordrag/ uitset tabel saam. (6) A = 000, B = 100, C = 101, D = 110, E = 111 Q1 Q2 Q XY Q1* Q2* Q3* Z1Z2 ERS 220 Examination
18 2.4. Determine the simplified transition equations, Q2* and Q3*, and the simplified output equation for Z1. / Bepaal die vereenvoudigde oordrag vergelykings, Q2* en Q3*, en die vereenvoudigde uitset vergelyking vir Z1. Q2* = (4) Q3* = (4) Z1 = (2) ERS 220 Examination
19 Section G: Sequential Logic Design Practices [35] 1. Design a circuit with output (QA, QB, QC and QD) sequence 0, 8, 4, 10, 5, 14, 7, 15, 0, 8,... using a 74x194 shift register, two 2 Input NAND gates, a 2 input AND gate, and a 2 Input NOR gate. No other gates may be used. Assume the CLR input is recognised only on the CLK pulse. / Ontwerp 'n stroombaan met die volgorde 0, 8, 4, 10, 5, 14, 7, 15, 0, 8,... gebruik n 74x193 skuifregister, twee 2 inset NAND hekke, n 2 inset AND hek, en n 2 inset NOR hek. Geen addisionele hekke mag gebruik word nie. Neem aan die CLR inset is herken alleen op die CLK pols. (20) Function Inputs Next State S1 S0 QA* QB* QC* QD* Hold 0 0 QA QB QC QD Shift right 0 1 RIN QA QB QC Shift left 1 0 QB QC QD LIN Load 1 1 A B C D ERS 220 Examination
20 2. Design a modulo-9 counter circuit with the counting sequence 0, 1, 2, 3, 9, 10, 11, 13, 14, 0, 1,... using a 74x163 4-bit binary counter and two 2-input NAND gates. No additional gates or components may be used. / Ontwerp 'n modulo-9 teller stroombaan met die tel volgorde 0, 1, 2, 3, 9, 10, 11, 13, 14, 0, 1,... gebruik n 74x163 4-bit binere teller en twee 2-inset NEN hekke. Geen addisioneel hekke of komponente mag gebruik word nie. (15) ******************* END / EINDE ******************* ERS 220 Examination
Studentenommer: Student number: Volpunte: Full marks: 160 Open / closed book: Oopboek / toeboek: 21 Punt: Mark: BELANGRIK- IMPORTANT
Departement Elektriese, Elektroniese en Rekenaar-Ingenieurswese Department of Electrical, Electronic and Computer Engineering Eksamen Invulvraestel Kopiereg voorbehou Vakkursus ERS220 20 November 2007
More informationExamination Copyright reserved. Eksamen Kopiereg voorbehou. Module EBN122 Elektrisiteit en Elektronika 13 November 2009
Departement Elektriese, Elektroniese en Rekenaar-Ingenieurswese Eksamen Kopiereg voorbehou Module EBN Elektrisiteit en Elektronika 3 November 009 Department of Electrical, Electronic and Computer Engineering
More informationEksterne eksaminator / External examiner: Dr. P Ntumba Interne eksaminatore / Internal examiners: Prof. I Broere, Prof. JE vd Berg, Dr.
VAN / SURNAME: UNIVERSITEIT VAN PRETORIA / UNIVERSITY OF PRETORIA FAKULTEIT NATUUR- EN LANDBOUWETENSKAPPE / FACULTY OF NATURAL AND AGRICULTURAL SCIENCES DEPARTEMENT WISKUNDE EN TOEGEPASTE WISKUNDE / DEPARTMENT
More informationSemester Test 1. Semestertoets 1. Module EIR221 Elektriese Ingenieurswese 20 Augustus Module EIR221 Electrical Engineering 20 August 2010
Departement Elektriese, Elektroniese en Rekenaar-Ingenieurswese Semestertoets 1 Kopiereg voorbehou Module EIR221 Elektriese Ingenieurswese 20 Augustus 2010 Department of Electrical, Electronic and Computer
More informationWTW 158 : CALCULUS EKSAMEN / EXAMINATION Eksterne eksaminator / External examiner: Me/Ms R Möller
Outeursreg voorbehou UNIVERSITEIT VAN PRETORIA Departement Wiskunde en Toegepaste Wiskunde Copyright reserved UNIVERSITY OF PRETORIA Department of Mathematics and Applied Maths Junie / June 005 Maksimum
More informationWTW 158 : CALCULUS EKSAMEN / EXAMINATION Eksterne eksaminator / External examiner: Prof NFJ van Rensburg
Outeursreg voorbehou UNIVERSITEIT VAN PRETORIA Departement Wiskunde en Toegepaste Wiskunde Copyright reserved UNIVERSITY OF PRETORIA Department of Mathematics and Applied Maths 4 Junie / June 00 Punte
More informationUNIVERSITEIT VAN PRETORIA / UNIVERSITY OF PRETORIA DEPT WISKUNDE EN TOEGEPASTE WISKUNDE DEPT OF MATHEMATICS AND APPLIED MATHEMATICS
UNIVERSITEIT VAN PRETORIA / UNIVERSITY OF PRETORIA DEPT WISKUNDE EN TOEGEPASTE WISKUNDE DEPT OF MATHEMATICS AND APPLIED MATHEMATICS VAN/SURNAME: VOORNAME/FIRST NAMES: WTW 218 - CALCULUS SEMESTERTOETS /
More informationOplos van kwadratiese vergelykings: die vind van die vergelyking *
OpenStax-CNX module: m39143 1 Oplos van kwadratiese vergelykings: die vind van die vergelyking * Free High School Science Texts Project Based on Solving quadratic equations: nding the equation by Free
More informationWinter Examination Copyright reserved. Wintereksamen Kopiereg voorbehou. Analoogelektronika ENE Junie 2004
Departement Elektriese, Elektroniese en Rekenaar-Ingenieurswese Department of Electrical, Electronic and Computer Engineering Wintereksamen Kopiereg voorbehou Analoogelektronika ENE310 18 Junie 2004 Winter
More information3. (d) None of these / Geen van hierdie
SECTION A (24 marks) / AFDELING A (24 punte) The questions in Section A must be completed on SIDE 2 of the optical reader form in SOFT PENCIL. First circle your answers on this paper and then transfer
More informationEksamen Invulvraestel Kopiereg voorbehou. Exam Fill in paper Copyright reserved. Linear Systems ELI November 2010
Departement Elektriese, Elektroniese en Rekenaar-Ingenieurswese Eksamen Invulvraestel Kopiereg voorbehou Lineêre Stelsels ELI0 4 November 010 Department of Electrical, Electronic and Computer Engineering
More informationVAN / SURNAME: VOORNAME / FIRST NAMES: STUDENTENOMMER / STUDENT NUMBER: FOONNO. GEDURENDE EKSAMENPERIODE / PHONE NO. DURING EXAM PERIOD:
UNIVERSITEIT VAN PRETORIA / UNIVERSITY OF PRETORIA DEPT WISKUNDE EN TOEGEPASTE WISKUNDE DEPT OF MATHEMATICS AND APPLIED MATHEMATICS WTW 220 - ANALISE / ANALYSIS EKSAMEN / EXAM 12 November 2012 TYD/TIME:
More informationSEMESTERTOETS 1 / SEMESTER TEST 1
UNIVERSITEIT VAN PRETORIA / UNIVERSITY OF PRETORIA FAKULTEIT NATUUR- EN LANDBOUWETENSKAPPE / FACULTY OF NATURAL AND AGRICULTURAL SCIENCES DEPARTEMENT WISKUNDE EN TOEGEPASTE WISKUNDE DEPARTMENT OF MATHEMATICS
More informationVAN/SURNAME: VOORNAME/FIRST NAMES: STUDENTENOMMER/STUDENT NUMBER: Totaal / Total:
UNIVERSITEIT VAN PRETORIA / UNIVERSITY OF PRETORIA DEPARTMENT OF MATHEMATICS AND APPLIED MATHEMATICS DEPARTEMENT WISKUNDE EN TOEGEPASTE WISKUNDE WTW 15 - WISKUNDIGE MODELLERING / MATHEMATICAL MODELLING
More informationEKSAMEN / EXAMINATION Q1 Q2 Q3 Q4 Q5 TOTAL. 2. No pencil work or any work in red ink will be marked.
0 UNIVERSITEIT VAN PRETORIA / UNIVERSITY OF PRETORIA FAKULTEIT NATUUR- EN LANDBOUWETENSKAPPE / FACULTY OF NATURAL AND AGRICULTURAL SCIENCES DEPARTEMENT WISKUNDE EN TOEGEPASTE WISKUNDE DEPARTMENT OF MATHEMATICS
More informationUNIVERSITEIT VAN PRETORIA / UNIVERSITY OF PRETORIA WTW263 NUMERIESE METODES WTW263 NUMERICAL METHODS EKSAMEN / EXAMINATION
VAN/SURNAME : UNIVERSITEIT VAN PRETORIA / UNIVERSITY OF PRETORIA VOORNAME/FIRST NAMES : WTW26 NUMERIESE METODES WTW26 NUMERICAL METHODS EKSAMEN / EXAMINATION STUDENTENOMMER/STUDENT NUMBER : HANDTEKENING/SIGNATURE
More informationJUNE 2005 TYD/TIME: 90 min PUNTE / MARKS: 50 VAN/SURNAME: VOORNAME/FIRST NAMES: STUDENTENOMMER/STUDENT NUMBER:
UNIVERSITEIT VAN PRETORIA / UNIVERSITY OF PRETORIA DEPT WISKUNDE EN TOEGEPASTE WISKUNDE DEPT OF MATHEMATICS AND APPLIED MATHEMATICS WTW 63 - NUMERIESE METHODE / NUMERICAL METHODS EKSAMEN / EXAMINATION
More informationVAN / SURNAME: VOORNAME / FIRST NAMES: STUDENTENOMMER / STUDENT NUMBER: HANDTEKENING / SIGNATURE: TELEFOON / TELEPHONE:
UNIVERSITEIT VAN PRETORIA / UNIVERSITY OF PRETORIA FAKULTEIT NATUUR- EN LANDBOUWETENSKAPPE / FACULTY OF NATURAL AND AGRICULTURAL SCIENCES DEPARTEMENT WISKUNDE EN TOEGEPASTE WISKUNDE DEPARTMENT OF MATHEMATICS
More informationNovember 2005 TYD/TIME: 90 min PUNTE / MARKS: 35 VAN/SURNAME: VOORNAME/FIRST NAMES: STUDENTENOMMER/STUDENT NUMBER: HANDTEKENING/SIGNATURE:
UNIVERSITEIT VAN PRETORIA / UNIVERSITY OF PRETORIA DEPT WISKUNDE EN TOEGEPASTE WISKUNDE DEPT OF MATHEMATICS AND APPLIED MATHEMATICS WTW 263 - NUMERIESE METODES / NUMERICAL METHODS EKSAMEN / EXAMINATION
More informationWTW 263 NUMERIESE METODES / NUMERICAL METHODS
UNIVERSITEIT VAN PRETORIA / UNIVERSITY OF PRETORIA FAKULTEIT NATUUR- EN LANDBOUWETENSKAPPE / FACULTY OF NATURAL AND AGRICULTURAL SCIENCES DEPARTEMENT WISKUNDE EN TOEGEPASTE WISKUNDE DEPARTMENT OF MATHEMATICS
More information[1a] 1, 3 [1b] 1, 0 [1c] 1, 3 en / and 1, 5 [1d] 1, 0 en / and 1, 0 [1e] Geen van hierdie / None of these
AFDELING A : MEERVOUDIGE KEUSE VRAE. 20 PUNTE Beantwoord vrae 1 tot 10 op die MERKLEESVORM se KANT 2. Indien kant 1 gebruik word sal dit nie nagesien word nie. Gebruik n sagte potlood. Jy mag nie verkeerde
More informationEXAMINATION / EKSAMEN 19 JUNE/JUNIE 2013 AT / OM 08:00
UNIVERSITY OF PRETORIA / UNIVERSITEIT VAN PRETORIA FACULTY OF NATURAL AND AGRICULTURAL SCIENCES / FAKULTEIT NATUUR- EN LANDBOUWETENSKAPPE DEPARTMENT OF MATHEMATICS AND APPLIED MATHEMATICS / DEPARTEMENT
More informationCAMI EDUCATION. Graad 12 Vraestel I : Rekord eksamen Punte. Lees die volgende instruksies noukeurig deur voordat die vrae beantwoord word:
CAMI Education (Pty) Ltd Reg. No. 1996/017609/07 CAMI House Fir Drive, Northcliff P.O. Bo 160 CRESTA, 118 Tel: +7 (11) 476-00 Fa : 086 601 4400 web: www.camiweb.com e-mail: info@camiweb.com CAMI EDUCATION
More informationEXAMINATION / EKSAMEN 17 JUNE/JUNIE 2011 AT / OM 12:00 Q1 Q2 Q3 Q4 Q5 Q6 TOTAL
UNIVERSITY OF PRETORIA / UNIVERSITEIT VAN PRETORIA FACULTY OF NATURAL AND AGRICULTURAL SCIENCES / FAKULTEIT NATUUR- EN LANDBOUWETENSKAPPE DEPARTMENT OF MATHEMATICS AND APPLIED MATHEMATICS / DEPARTEMENT
More informationWTW 161 : ALGEBRA. EKSAMEN / EXAMINATION Eksterne eksaminator / External examiner: Dr F Theron
Outeursreg voorbehou UNIVERSITEIT VAN PRETORIA Departement Wiskunde en Toegepaste Wiskunde Copyright reserved UNIVERSITY OF PRETORIA Department of Mathematics and Applied Maths November 006 Maks Punte
More informationHOëRSKOOL STRAND WISKUNDE NOVEMBER 2016 GRAAD 11 VRAESTEL 2
HOëRSKOOL STRAND WISKUNDE NOVEMBER 2016 TOTAAL: 150 Eksaminator: P. Olivier GRAAD 11 VRAESTEL 2 TYD: 3UUR Moderator: E. Loedolff INSTRUKSIES: 1. Hierdie vraestel bestaan uit 8 bladsye en n DIAGRAMBLAD
More informationDepartment of Mathematics and Applied Mathematics Departement Wiskunde en Toegepaste Wiskunde
Department of Mathematics and Applied Mathematics Departement Wiskunde en Toegepaste Wiskunde GRADES 10 AND 11 GRADE 10 EN 11 30 July 3 Aug 2018 30 Julie 3 Aug 2018 TIME: 2 HOURS TYD: 2 URE 2012 OUTEURSREG
More informationMATHEMATICS GRADE 10 TASK 1 INVESTIGATION Marks: 55
WISKUNDE GRAAD 10 TAAK 1 ONDERSOEK Punte: 55 MATHEMATICS GRADE 10 TASK 1 INVESTIGATION Marks: 55 INSTRUKSIES: 1. Die taak moet ingehandig word op 2 Maart 2015. 2. Beantwoord al die vrae. 3. Slegs vrae
More informationQuestion 1. The van der Waals equation of state is given by the equation: a
Kopiereg voorbehou Universiteit van retoria University of retoria Copyright reserved Departement Chemiese Ingenieurswese Department of Chemical Engineering CHEMICAL ENGINEERING CIR EKSAMEN Volpunte: Tydsduur:
More informationKwadratiese rye - Graad 11
OpenStax-CNX module: m38240 1 Kwadratiese rye - Graad 11 Wiehan Agenbag Free High School Science Texts Project Based on Quadratic Sequences - Grade 11 by Rory Adams Free High School Science Texts Project
More informationFAKULTEIT INGENIEURSWESE FACULTY OF ENGINEERING. Volpunte: Full marks: Instruksies / Instructions
FAKULTEIT INGENIEURSWESE FACULTY OF ENGINEERING Elektrotegniek 143 Electro-techniques 143 Tydsduur: Duration Eksaminatore: Prof H C Reader Prof J B de Swardt Mnr P-J Randewijk 1.5 h 1 Beantwoord al die
More informationModule ELX May 2009
Departement Elektriese, Elektroniese en Rekenaar-Ingenieurswese Eksamenvraestel Kopiereg voorbehou Module ELX 311 27 Mei 2009 Department of Electrical, Electronic and Computer Engineering Examination Question
More informationFunksies en Verwantskappe
UITDRUKKINGS Funksies en Verwantskappe n funksie is n verhouding tussen waardes Elke inset waarde het n spesifieke uitset waarde a) Bereken die -waardes (uitset) b) Bereken die -waarde (inset) Die vloeidiagram
More informationFAKULTEIT INGENIEURSWESE FACULTY OF ENGINEERING
FAKULTEIT INGENIEURSWESE FACULTY OF ENGINEERING Vakkursus / Subject course: Toegepaste Wiskunde B264 Applied Mathematics B264 Tweede Eksamen: Desember 2010 Second Examination: December 2010 Volpunte /
More informationDepartment of Mathematics and Applied Mathematics Departement Wiskunde en Toegepaste Wiskunde
Department of Mathematics and Applied Mathematics Departement Wiskunde en Toegepaste Wiskunde GRADES 0 AND GRADE 0 EN AUGUST 206 AUGUSTUS 206 TIME: 2 HOURS TYD: 2 URE 202 OUTEURSREG VOORBEHOU, UNIVERSITEIT
More informationGraad 12: Rye en Reekse
Graad 1: Rye en Reekse Opgestel vir LitNet deur Jeanne-Mari du Plessis In hierdie inligtingstuk gaan ons kyk na: 1. Rekenkundige rye. Meetkundige rye 3. Rekenkundige reekse 4. Meetkundige reekse 5. Sigma-notasie
More informationUNIVERSITEIT VAN PRETORIA / UNIVERSITY OF PRETORIA DEPT WISKUNDE EN TOEGEPASTE WISKUNDE DEPT OF MATHEMATICS AND APPLIED MATHEMATICS
UNIVERSITEIT VAN PRETORIA / UNIVERSITY OF PRETORIA DEPT WISKUNDE EN TOEGEPASTE WISKUNDE DEPT OF MATHEMATICS AND APPLIED MATHEMATICS WTW 211 : LINEÊRE ALGEBRA / LINEAR ALGEBRA SEMESTERTOETS 1 / SEMESTER
More informationPunte: Intern Marks: Internal WTW 168 : CALCULUS. EKSAMEN / EXAMINATION Eksterne eksaminator / External examiner: Me / Ms R Möller
Outeursreg voorbehou UNIVERSITEIT VAN PRETORIA Departement Wiskunde en Toegepaste Wiskunde Copright reserved UNIVERSITY OF PRETORIA Department of Mathematics and Applied Maths November 005 Punte / Marks:35
More informationLIMPOPO DEPARTEMENT VAN ONDERWYS LIMPOPO DEPARTMENT OF EDUCATION- LAERSKOOL WARMBAD
LIMPOPO DEPARTEMENT VAN ONDERWYS LIMPOPO DEPARTMENT OF EDUCATION- LAERSKOOL WARMBAD NSTRUKSIES: kryf jou naam en van op elke antwoordblad en jou nommer SUMMATIEWE ASSESSERING SUMMATIVE ASSESSMENT. Voltooi
More informationVAN / SURNAME: VOORNAME / FIRST NAMES: STUDENTENOMMER / STUDENT NUMBER: HANDTEKENING / SIGNATURE: SEL NR / CELL NO:
UNIVERSITEIT VAN PRETORIA / UNIVERSITY OF PRETORIA FAKULTEIT NATUUR- EN LANDBOUWETENSKAPPE / FACULTY OF NATURAL AND AGRICULTURAL SCIENCES DEPARTEMENT WISKUNDE EN TOEGEPASTE WISKUNDE / DEPARTMENT OF MATHEMATICS
More informationa b
GRDE - FIRST ROUND QUESTIONS - 0 GRD - EERSTE RONDTE VRE - 0 QUESTION/ VRG s a decimal number, 3,% is equal to: s n desimale breuk, word 3,% geskryf as: 0,03 B 0,3 C 3, D 3, E 3 QUESTION/ VRG a63 67 73
More informationDepartment of Mathematics and Applied Mathematics Departement Wiskunde en Toegepaste Wiskunde
Department of Mathematics and Applied Mathematics Departement Wiskunde en Toegepaste Wiskunde GRADES 10 AND 11 GRADE 10 EN 11 31 July 5 Aug 2017 31 July 5 Aug 2017 TIME: 2 HOURS TYD: 2 URE 2012 OUTEURSREG
More informationDEPARTEMENT SIVIELE EN BIOSISTEEM-INGENIEURSWESE DEPARTMENT OF CIVIL AND BIOSYSTEMS ENGINEERING MEGANIKA SWK 122 EKSAMEN MECHANICS SWK 122 EXAMINATION
UNIVERSITEIT VAN PRETORIA UNIVERSITY OF PRETORIA Kopiereg voorbehou / Copyright reserved DEPARTEMENT SIVIELE EN BIOSISTEEM-INGENIEURSWESE DEPARTMENT OF CIVIL AND BIOSYSTEMS ENGINEERING MEGANIKA SWK 122
More informationUNIVERSITY OF PRETORIA
UNIVERSITY OF PRETORIA FACULTY OF ENGINEERING, BUILT ENVIRONMENT AND INFORMATION TECHNOLOGY Student Number: Name: Surname: Email: Contact Number: Signature: Subject: MPR212: Programming and Date Processing
More informationGRADE 11 - FINAL ROUND QUESTIONS GRAAD 11 - FINALE RONDTE VRAE
GRE - FINL ROUN QUESTIONS - 9 GR - FINLE RONTE VRE - 9 QUESTION/ VRG 6 Which of the following is not a factor of x? 6 Watter een van die volgende is nie 'n faktor van x nie? x + x x + x + x+ E x QUESTION/
More informationHuiswerk Hoofstuk 22 Elektriese velde Homework Chapter 22 Electric fields
1 Huiswerk Hoofstuk Elektriese velde Homework Chapter Electric fields 8 th / 8 ste HRW 1, 5, 7, 10 (0), 43, 45, 47, 53 9 th / 9 de HRW (9.6 10 18 N left, 30 N/C), 3, 8 (0), 11, 39, 41, 47, 49 Elektriese
More informationReg. No. Question Paper Code : B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER Second Semester. Computer Science and Engineering
Sp 6 Reg. No. Question Paper Code : 27156 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2015. Second Semester Computer Science and Engineering CS 6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN (Common
More informationMAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI
DEPARTMENT: ECE MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI 6 QUESTION BANK SUBJECT NAME: DIGITAL ELECTRONICS UNIT : Design of Sequential Circuits PART A ( Marks). Draw the logic diagram 4: Multiplexer.(AUC
More informationUNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017
UNIVERSITY OF BOLTON TW35 SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER 2-2016/2017 INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS MODULE NO: EEE5002
More informationDIGITAL LOGIC CIRCUITS
DIGITAL LOGIC CIRCUITS Introduction Logic Gates Boolean Algebra Map Specification Combinational Circuits Flip-Flops Sequential Circuits Memory Components Integrated Circuits Digital Computers 2 LOGIC GATES
More informationInitials & Surname / Voorletters & Van :...
UNIVERSITY OF PRETORIA / UNIVERSITEIT VAN PRETORIA Dept. of Electrical, Electronic & Computer Eng. / Dept. Elektriese, Elektroniese & Rekenaar-Ing. EIR 221 - NOVEMBER 2012 EXAM PART A1 / EKSAMEN DEEL A1
More informationCHM 215 Eksamen / Examination
CHM 215 Eksamen / Examination Fakulteit Natuur- & Landbouwetenskappe Departement Chemie 09/06/2009 Tyd / Time: 150 min Punte / Marks: 100 (+2) INTERNE EKSAMINATRE / INTERNAL EXAMINERS: EKSTERNE EKSAMINATRE
More informationGRADE 9 - FINAL ROUND QUESTIONS GRAAD 9 - FINALE RONDTE VRAE
GRADE 9 - FINAL ROUND QUESTIONS - 009 GRAAD 9 - FINALE RONDTE VRAE - 009 QUESTION/ VRAAG Find the final value if an amount of R7500 is increased by 5% and then decreased by 0%. Bepaal die finale waarde
More informationTW 214 TOETS 2 - VOORBEREIDING 2018 TEST 2 - PREPARATION
TW 214 TOETS 2 - VOORBEREIDING 2018 TEST 2 - PREPARATION Die toets gaan oor die volgende onderwerpe: REFLEKSIES (GEKROMDE SPIEËLS) DETERMINANTE EIEWAARDES EN EIEWAARDE-ONTBINDING (A = SΛS 1 ) STELSELS
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Digital IC packages TTL (transistor-transistor
More informationNATIONAL SENIOR CERTIFICATE/NASIONALE SENIOR SERTIFIKAAT GRADE/GRAAD 10
NATIONAL SENIOR CERTIFICATE/NASIONALE SENIOR SERTIFIKAAT GRADE/GRAAD 10 TECHNICAL SCIENCES: PHYSICS (P1)/ TEGNIESE WETENSKAPPE: FISIKA (V1) EXEMPLAR/MODEL 2016 MARKS/PUNTE: 150 This memorandum consists
More informationHoofstuk 29 Magnetiese Velde a.g.v Elektriese Strome
Hoofstuk 29 Magnetiese Velde a.g.v Elektriese Strome Nadat hierdie hoofstuk afghandel is, moet die student: Magnetiese veld as gevolg van n stroom kan bereken; Die regterhandreëls kan neerskryf en toepas;
More informationFAKULTEIT INGENIEURSWESE FACULTY OF ENGINEERING
FAKULTEIT INGENIEURSWESE FACULTY OF ENGINEERING Ingenieurschemie 123 Engineering Chemistry 123 Toets (Eerste geleentheid) Test (First opportunity) 11 / 03 / 2010 Tydsduur / Duration 2 h Volpunte / Full
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified)
WINTER 17 EXAMINATION Subject Name: Digital Techniques Model Answer Subject Code: 17333 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given
More informationCMY 127 EKSAMEN / EXAMINATION
DEPARTEMENT CHEMIE DEPARTMENT OF CHEMISTRY CMY 127 EKSAMEN / EXAMINATION DATUM / DATE: 20 November 2012 EKSAMINATORE: Prof. WJ Schoeman EXAMINERS: Prof. M Potgieter TYD / TIME: 3 ure / hours Prof. R Vleggaar
More informationon candidate s understanding. 7) For programming language papers, credit may be given to any other program based on equivalent concept.
WINTER 17 EXAMINATION Subject Name: Digital Techniques Model Answer Subject Code: 17333 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given
More informationNATIONAL SENIOR CERTIFICATE NASIONALE SENIOR SERTIFIKAAT GRADE/GRAAD 12 JUNE/JUNIE 2018 MATHEMATICS P1/WISKUNDE V1 MARKING GUIDELINE/NASIENRIGLYN
NATIONAL SENIOR CERTIFICATE NASIONALE SENIOR SERTIFIKAAT GRADE/GRAAD JUNE/JUNIE 08 MATHEMATICS P/WISKUNDE V MARKING GUIDELINE/NASIENRIGLYN MARKS/PUNTE: 50 This marking guideline consists of 5 pages./ Hierdie
More informationKing Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department
King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department Page of COE 22: Digital Logic Design (3--3) Term (Fall 22) Final Exam Sunday January
More informationSIR C.R.REDDY COLLEGE OF ENGINEERING ELURU DIGITAL INTEGRATED CIRCUITS (DIC) LABORATORY MANUAL III / IV B.E. (ECE) : I - SEMESTER
SIR C.R.REDDY COLLEGE OF ENGINEERING ELURU 534 007 DIGITAL INTEGRATED CIRCUITS (DIC) LABORATORY MANUAL III / IV B.E. (ECE) : I - SEMESTER DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING DIGITAL
More informationUNIVERSITY OF PRETORIA DEPT SlVlELE INGENIEURSWESE / DEPT OF CIVIL ENGINEERING
1 UNIVERSCTEIT VAN PRETORIA I UNIVERSITY OF PRETORIA DEPT SlVlELE INGENIEURSWESE / DEPT OF CIVIL ENGINEERING STRENGTH OF MATERIALS SWK210 STERKTELEER SWK210 FINAL EXAMINATION - EiNDEKSAMEN VAN en VOORLETTERS
More informationKing Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department
King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department Page 1 of 13 COE 202: Digital Logic Design (3-0-3) Term 112 (Spring 2012) Final
More informationCMY 127 FINALE EKSAMEN / FINAL EXAMINATION AFDELING A / SECTION A
DEPARTEMENT CHEMIE DEPARTMENT OF CHEMISTRY CMY 127 FINALE EKSAMEN / FINAL EXAMINATION AFDELING A / SECTION A DATUM / DATE: 12 November 2009 EKSAMINATORE / Mrs. AC Botha TYD / TIME: 2 ½ uur / hours EXAMINERS:
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 17: March 23, 2017 Energy and Power Optimization, Design Space Exploration, Synchronous MOS Logic Lecture Outline! Energy and Power Optimization
More informationvidyarthiplus.com vidyarthiplus.com vidyarthiplus.com ANNA UNIVERSITY- COMBATORE B.E./ B.TECH. DEGREE EXAMINATION - JUNE 2009. ELECTRICAL & ELECTONICS ENGG. - FOURTH SEMESTER DIGITAL LOGIC CIRCUITS PART-A
More informationSemester Test 1 Semestertoets 1 FSK March 2011 / 16 Maart Time 2½ hours Max. Total 85 Marks Max Tyd 2½ ure Maks. Totaal 85 punte Maks
Physics Department Fisika Departement Semester Test 1 Semestertoets 1 FSK116 16 March 011 / 16 Maart 011 Surname and initials Van en voorletters Signature Handtekening MEMO Student number Studentenommer
More informationCHW 261: Logic Design
CHW 26: Logic Design Instructors: Prof. Hala Zayed Dr. Ahmed Shalaby http://www.bu.edu.eg/staff/halazayed4 http://bu.edu.eg/staff/ahmedshalaby4# Slide Digital Fundamentals Digital Concepts Slide 2 What?
More informationCMY 117 SEMESTERTOETS 2 / SEMESTER TEST 2
DEPARTEMENT CHEMIE DEPARTMENT OF CHEMISTRY CMY 117 SEMESTERTOETS 2 / SEMESTER TEST 2 DATUM / DATE: 13 May / Mei 2013 PUNTE / MARKS: 100 TYD / TIME: 3 ure / hours Afdeling A / Section A: 40 Afdeling B /
More informationUniversiteit Stellenbosch / Stellenbosch University Toegepaste Wiskunde / Applied Mathematics B252 Assessering 1 / Assessment 1:
Universiteit Stellenbosch / Stellenbosch University Toegepaste Wiskunde / Applied Mathematics B252 Assessering 1 / Assessment 1: 2017-09-01 STUDENTENOMMER / STUDENT NUMBER NEEM KENNIS VAN DIE INLIGTING
More informationQuestion / Vraag 1: [12]
1 Question / Vraag 1: [12] The following questions are multiple choice questions. There is only one correct answer from the choices given. Select the correct option by marking the option with a cross (X).
More informationVoorletters en Van Initials and Surname Studente nommer Student number Datum / Date
Voorletters en Van Initials and Surname Studente nommer Student number Datum / Date MTX221 2011 KLASTOETS 3E / CLASSTES 3E 25 min. (14 punte/marks) *Sal herwerk tot 10 punte vir klaslys doeleindes * Will
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Total Power. Energy and Power Optimization. Worksheet Problem 1
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 20, 2018 Energy and Power Optimization, Design Space Exploration Lecture Outline! Energy and Power Optimization " Tradeoffs! Design
More informationDE58/DC58 LOGIC DESIGN DEC 2014
Q.2 a. In a base-5 number system, 3 digit representations is used. Find out (i) Number of distinct quantities that can be represented.(ii) Representation of highest decimal number in base-5. Since, r=5
More informationSample Test Paper - I
Scheme G Sample Test Paper - I Course Name : Computer Engineering Group Marks : 25 Hours: 1 Hrs. Q.1) Attempt any THREE: 09 Marks a) Define i) Propagation delay ii) Fan-in iii) Fan-out b) Convert the following:
More informationChapter 7. Sequential Circuits Registers, Counters, RAM
Chapter 7. Sequential Circuits Registers, Counters, RAM Register - a group of binary storage elements suitable for holding binary info A group of FFs constitutes a register Commonly used as temporary storage
More informationTopics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics Dynamic CMOS Sequential Design Memory and Control Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance
More informationS.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques
S.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 100 Q.1(a) Attempt any SIX of the following : [12] Q.1(a) (i) Derive AND gate and OR gate
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) State any two Boolean laws. (Any 2 laws 1 mark each)
Subject Code: 17333 Model Answer Page 1/ 27 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model
More informationS.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques
S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 100 Q.1(a) Attempt any SIX of the following : [12]
More informationUNIVERSITY OF PRETORIA / UNIVERSITEIT VAN PRETORIA DEPT WISKUNDE EN TOEGEPASTE WISKUNDE DEPT OF MATHEMATICS AND APPLIED MATHEMATICS
UNIVERSITY OF PRETORIA / UNIVERSITEIT VAN PRETORIA DEPT WISKUNDE EN TOEGEPASTE WISKUNDE DEPT OF MATHEMATICS AND APPLIED MATHEMATICS WTW 285 DISCRETE STRUCTURES DISKRETE STRUKTURE EXAMINATION EKSAMEN Internal
More informationALU A functional unit
ALU A functional unit that performs arithmetic operations such as ADD, SUB, MPY logical operations such as AND, OR, XOR, NOT on given data types: 8-,16-,32-, or 64-bit values A n-1 A n-2... A 1 A 0 B n-1
More informationVidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution
. (a) (i) ( B C 5) H (A 2 B D) H S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution ( B C 5) H (A 2 B D) H = (FFFF 698) H (ii) (2.3) 4 + (22.3) 4 2 2. 3 2. 3 2 3. 2 (2.3)
More informationDHANALAKSHMI COLLEGE OF ENGINEERING, CHENNAI DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN
DHANALAKSHMI COLLEGE OF ENGINEERING, CHENNAI DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT I : BOOLEAN ALGEBRA AND LOGIC GATES PART - A (2 MARKS) Number
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Outline Combinational logic circuits Output
More informationDept. of ECE, CIT, Gubbi Page 1
Verification: 1) A.B = A + B 7404 7404 7404 A B A.B A.B 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 A B A B A + B 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 1 0 0 0 2) A+B = A. B 7404 7404 7404 A B A+B A+B 0 0 0 1 0 1 1 0 1
More information3 Logic Function Realization with MSI Circuits
3 Logic Function Realization with MSI Circuits Half adder A half-adder is a combinational circuit with two binary inputs (augund and addend bits) and two binary outputs (sum and carry bits). It adds the
More informationGRADE 9 - FIRST ROUND QUESTIONS GRAAD 9 - EERSTE RONDTE VRAE
GRADE 9 - FIRST ROUND QUESTIONS - 009 GRAAD 9 - EERSTE RONDTE VRAE - 009 QUESTION/ VRAAG On Saturday, a store gives a discount of 0% on a computer valued at R9 000. On Monday, the store decides to add
More informationDepartment of Electrical & Electronics EE-333 DIGITAL SYSTEMS
Department of Electrical & Electronics EE-333 DIGITAL SYSTEMS 1) Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction (a) X -Y and (b) Y - X using 2's complements. a) X = 1010100
More informationAppendix B. Review of Digital Logic. Baback Izadi Division of Engineering Programs
Appendix B Review of Digital Logic Baback Izadi Division of Engineering Programs bai@engr.newpaltz.edu Elect. & Comp. Eng. 2 DeMorgan Symbols NAND (A.B) = A +B NOR (A+B) = A.B AND A.B = A.B = (A +B ) OR
More informationGRADE 11 - FINAL ROUND QUESTIONS GRAAD 11 - FINALE RONDTE VRAE
GR 11 - FINL ROUN QUSTIONS - 007 GR 11 - FINL RONT VR - 007 1 QUSTION/ VRG 1 Three persons, Mr. X, Ms. Y, and Mr. Z, went fishing. Mr. X caught NO fish, Ms. Y caught five fish, and Mr. Z caught three fish
More informationAnalysis of clocked sequential networks
Analysis of clocked sequential networks keywords: Mealy, Moore Consider : a sequential parity checker an 8th bit is added to each group of 7 bits such that the total # of 1 bits is odd for odd parity if
More informationDigital Electronics Circuits 2017
JSS SCIENCE AND TECHNOLOGY UNIVERSITY Digital Electronics Circuits (EC37L) Lab in-charge: Dr. Shankraiah Course outcomes: After the completion of laboratory the student will be able to, 1. Simplify, design
More informationWORKBOOK. Try Yourself Questions. Electrical Engineering Digital Electronics. Detailed Explanations of
27 WORKBOOK Detailed Eplanations of Try Yourself Questions Electrical Engineering Digital Electronics Number Systems and Codes T : Solution Converting into decimal number system 2 + 3 + 5 + 8 2 + 4 8 +
More informationGRAAD 11 NOVEMBER 2012 WISKUNDIGE GELETTERDHEID V1 MEMORANDUM
Province of the EASTERN CAPE EDUCATION NASIONALE SENIOR SERTIFIKAAT GRAAD 11 NOVEMBER 2012 WISKUNDIGE GELETTERDHEID V1 MEMORANDUM MARKS: 100 SIMBOOL A CA C J M MA P R RT/RG S SF O VERDUIDELIKING Akkuraatheid
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) SUMMER 14 EXAMINATION Model Answer
MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC 27001 2005 Certified) SUMMER 14 EXAMINATION Model Answer Subject Code : 17320 Page No: 1/34 Important Instructions to examiners: 1)
More informationDigital Logic. CS211 Computer Architecture. l Topics. l Transistors (Design & Types) l Logic Gates. l Combinational Circuits.
CS211 Computer Architecture Digital Logic l Topics l Transistors (Design & Types) l Logic Gates l Combinational Circuits l K-Maps Figures & Tables borrowed from:! http://www.allaboutcircuits.com/vol_4/index.html!
More information