CE Optimized State Machines

Size: px
Start display at page:

Download "CE Optimized State Machines"

Transcription

1 C 1911 Optimized State Machines

2 Un-used states o we care about un-used states? YS! Start-up Bit errors 2 tj

3 Un-used states Mod 5 counter reset tj

4 Un-used states Mod 5 counter What happens if an event causes the state to become corrupted reset tj

5 Un-used states Mod 5 counter Recovery solution reset tj

6 Un-used states Mod 5 counter Recovery solution reset tj

7 Un-used states Mod 5 counter self starting reset not required reset may not work in simulation 7 tj

8 Redundant states lead to more logic than necessary 2 States are equivalent if Outputs are the same Transition to the same next state if the inputs are the same 8 tj

9 Informal analysis Redundant states lead to more logic than necessary 3 state variables 3 output bits x y A 100 x+y x y x+y B 010 y x y x y C y 101 y x y 9 tj

10 Informal analysis States and have the same output (101) both go to C when y is true both go to when y is true Combine and 10 tj

11 Informal analysis Redundant states lead to more logic than necessary 3 state variables 2 state variables 3 output bits re-encoded to 2 bits x y A x+y x y x+y B 010 y x x y C y 11 x y 11 tj

12 Successive Partitions State Input Next State A 0 B A 1 C B 0 B 1 C 0 C 1 0 B 1 G 0 1 C 0 1 G 0 G 1 G State Output A 1 B 1 C G 0 State Input Next State Output A 0 B 1 A 1 C 1 B 0 1 B 1 1 C 0 0 C B 1 1 G C G 0 0 G 1 G 0 12 tj

13 Successive Partitions Partitions Next States Action P0 ABCG Identify states and outputs 13 tj

14 Successive Partitions Partitions Next States Action P0 ABCG Partition into sets with same outputs AB, CG 14 tj

15 Successive Partitions Partitions Next States Action P0 P1 In = 0 In = 1 AB BB CG ABCG CG CG AB, CG Identify next states based on current state and inputs 15 tj

16 Successive Partitions Partitions Next States Action P0 P1 In = 0 In = 1 AB BB CG ABCG CG CG Identify any groups of next states that are not part of an existing partition those groups by current state AB, CG CG and 16 tj

17 Successive Partitions Partitions Next States Action P0 P1 In = 0 In = 1 P2 In = 0 In = 1 AB BB CG AB BB CG ABCG CG CG CG CG AB, CG CG and Identify next states based on current state and inputs 17 tj

18 Successive Partitions Partitions Next States Action P0 P1 In = 0 In = 1 P2 In = 0 In = 1 AB BB CG AB BB CG ABCG CG CG CG CG Identify any groups of next states that are not part of an existing partition AB, CG CG and A and B those groups by current state 18 tj

19 Successive Partitions Partitions Next States Action P0 P1 In = 0 In = 1 P2 In = 0 In = 1 P2 In = 0 In = 1 A BB CG AB BB CG AB BB CG B ABCG CG CG CG CG CG CG AB, CG A and B CG and 19 tj A and B Identify next states based on current state and inputs

20 Successive Partitions Partitions Next States Action P0 P1 In = 0 In = 1 P2 In = 0 In = 1 P2 In = 0 In = 1 ABCG AB, CG AB CG Identify any groups of next states that are not BB A and B part of an existing partition CG CG CG and AB those groups by CG current state BB CG CG A BB CG B CG CG A and B No more reduction 20 tj

21 Successive Partitions Partitions Next States Action P0 P1 In = 0 In = 1 P2 In = 0 In = 1 P2 In = 0 In = 1 A BB CG AB BB CG AB BB CG B ABCG CG CG CG CG CG CG Pfinal A B CG AB, CG A and B CG and 21 tj A and B No more reduction

22 Successive Partitions State Input Next State Output A 0 B 1 7 states 4 states A 1 C 1 B 0 1 B 1 1 C 0 0 C B 1 1 G C G 0 0 G 1 G 0 State Input Next State Output A 0 B 1 A 1 CG 1 B 0 A 1 B 1 1 CG 0 0 CG 1 CG 0 0 CG 0 1 A 0 State Input Next State Output P 0 Q 1 P 1 R 1 Q 0 P 1 Q 1 S 1 R 0 S 0 R 1 R 0 S 0 R 0 S 1 P 0 22 tj

23 Implication Chart A B C G A B C G 23 tj

24 Implication Chart compare pairs of states If outputs are different out box A B C G A B C G 24 tj

25 Implication Chart write in the implicants to all empty boxes The two states would be the same I the implicants are the same A B C G B- C- B-B C-G B- -G - C G States A and B would be the same ONLY if B and are the same and C and are the same - C- - C-G - -G A B C G 25 tj

26 Implication Chart Traverse the structure and out any boxes whose implicants are already d out This indicates the implicant is not true A B C G B- C- B-B C-G B- -G - C G - C- - C-G - -G A B C G 26 tj

27 Implication Chart Traverse the structure and out any boxes whose implicants are already d out This indicates the implicant is not true A B C G B- C- B-B C-G B- -G - C- - -G - C-G A B C G 27 tj

28 Implication Chart Traverse the structure and out any boxes whose implicants are already d out This indicates the implicant is not true A B C G B-B C-G - C- - -G - C-G A B C G 28 tj

29 Implication Chart Remaining un- d boxes indicate equivalent states A B C G B-B C-G - C- - -G A B - C-G A B C G CG 29 tj

30 Implication Chart State Input Next State Output A 0 B 1 7 states 4 states A 1 C 1 B 0 1 B 1 1 C 0 0 C B 1 1 G C G 0 0 G 1 G 0 State Input Next State Output A 0 B 1 A 1 CG 1 B 0 A 1 B 1 1 CG 0 0 CG 1 CG 0 0 CG 0 1 A 0 State Input Next State Output P 0 Q 1 P 1 R 1 Q 0 P 1 Q 1 S 1 R 0 S 0 R 1 R 0 S 0 R 0 S 1 P 0 30 tj

31 esign Process Circuit esign 1) Identify the states collectively these make a state variable 2) Identify the Inputs and Outputs 3) Assign values for each input/output (encoding) 4) Create a state transition diagram / table 5) Optimize the state transition table 6) Assign values for the state variable for each state (encoding) 7) Create truth tables for the combinational logic blocks in the machine model: next state, output 8) Minimize the next state and output equations using K-maps or Boolean Algebra techniques 9) raw the circuit schematic 10) Verify the solution 11) Build the physical circuit 12) Test the physical circuit to ensure correct operation esign Process HL 1) Identify the states collectively these make a state variable 2) Identify the Inputs and Outputs 3) Create a state transition diagram / table 4) Optimize the state transition table 5) Create the HL to match the state transition table 6) Choose an encoding scheme (or let the tool decide) 7) Synthesize the design 8) Verify the solution 9) Build the physical circuit 10) Test the physical circuit to ensure correct operation 31 tj

Time Allowed 3:00 hrs. April, pages

Time Allowed 3:00 hrs. April, pages IGITAL ESIGN COEN 32 Prof. r. A. J. Al-Khalili Time Allowed 3: hrs. April, 998 2 pages Answer All uestions No materials are allowed uestion a) esign a half subtractor b) esign a full subtractor c) Using

More information

EE 209 Spiral 1 Exam Solutions Name:

EE 209 Spiral 1 Exam Solutions Name: EE 29 Spiral Exam Solutions Name:.) Answer the following questions as True or False a.) A 4-to- multiplexer requires at least 4 select lines: true / false b.) An 8-to- mux and no other logic can be used

More information

Digital Design. Sequential Logic

Digital Design. Sequential Logic Principles Of igital esign Chapter 6 Sequential Logic Chapter preview Boolean algebra 3 Logic gates and flip-flops 3 Finite-state machine 6 Logic design techniques 4 Sequential design techniques 6 Binary

More information

Chapter 2. Digital Logic Basics

Chapter 2. Digital Logic Basics Chapter 2 Digital Logic Basics 1 2 Chapter 2 2 1 Implementation using NND gates: We can write the XOR logical expression B + B using double negation as B+ B = B+B = B B From this logical expression, we

More information

Different encodings generate different circuits

Different encodings generate different circuits FSM State Encoding Different encodings generate different circuits no easy way to find best encoding with fewest logic gates or shortest propagation delay. Binary encoding: K states need log 2 K bits i.e.,

More information

Sequential Logic Circuits

Sequential Logic Circuits Chapter 4 Sequential Logic Circuits 4 1 The defining characteristic of a combinational circuit is that its output depends only on the current inputs applied to the circuit. The output of a sequential circuit,

More information

Chapter 4. Sequential Logic Circuits

Chapter 4. Sequential Logic Circuits Chapter 4 Sequential Logic Circuits 1 2 Chapter 4 4 1 The defining characteristic of a combinational circuit is that its output depends only on the current inputs applied to the circuit. The output of

More information

Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University

Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University Original Source: Aby K George, ECE Department, Wayne State University Contents The Map method Two variable

More information

Random Number Generator Digital Design - Demo

Random Number Generator Digital Design - Demo Understanding Digital Design The Digital Electronics 2014 Digital Design - Demo This presentation will Review the oard Game Counter block diagram. Review the circuit design of the sequential logic section

More information

Sequential Circuit Design

Sequential Circuit Design Sequential Circuit esign esign Procedure. Specification 2. Formulation Obtain a state diagram or state table 3. State Assignment Assign binary codes to the states 4. Flip-Flop Input Equation etermination

More information

Lecture 14 Finite state machines

Lecture 14 Finite state machines Lecture 14 Finite state machines Finite state machines are the foundation of nearly all digital computation. The state diagram captures the desired system behavior A formulaic process turns this diagram

More information

Lecture 8: Sequential Networks and Finite State Machines

Lecture 8: Sequential Networks and Finite State Machines Lecture 8: Sequential Networks and Finite State Machines CSE 140: Components and Design Techniques for Digital Systems Spring 2014 CK Cheng, Diba Mirza Dept. of Computer Science and Engineering University

More information

Sequential Logic Optimization. Optimization in Context. Algorithmic Approach to State Minimization. Finite State Machine Optimization

Sequential Logic Optimization. Optimization in Context. Algorithmic Approach to State Minimization. Finite State Machine Optimization Sequential Logic Optimization! State Minimization " Algorithms for State Minimization! State, Input, and Output Encodings " Minimize the Next State and Output logic Optimization in Context! Understand

More information

Combinatorial Logic Design Principles

Combinatorial Logic Design Principles Combinatorial Logic Design Principles ECGR2181 Chapter 4 Notes Logic System Design I 4-1 Boolean algebra a.k.a. switching algebra deals with boolean values -- 0, 1 Positive-logic convention analog voltages

More information

Simplifying Logic Circuits with Karnaugh Maps

Simplifying Logic Circuits with Karnaugh Maps Simplifying Logic Circuits with Karnaugh Maps The circuit at the top right is the logic equivalent of the Boolean expression: f = abc + abc + abc Now, as we have seen, this expression can be simplified

More information

Boolean cubes EECS150. Mapping truth tables onto cubes. Simplification. The Uniting Theorem. Three variable example

Boolean cubes EECS150. Mapping truth tables onto cubes. Simplification. The Uniting Theorem. Three variable example EES5 Section 5 Simplification and State Minimization Fall 2 -cube X oolean cubes Visual technique for indentifying when the uniting theorem can be applied n input variables = n-dimensional "cube" Y 2-cube

More information

COMPUTER SCIENCE TRIPOS

COMPUTER SCIENCE TRIPOS CST.2014.2.1 COMPUTER SCIENCE TRIPOS Part IA Tuesday 3 June 2014 1.30 to 4.30 pm COMPUTER SCIENCE Paper 2 Answer one question from each of Sections A, B and C, and two questions from Section D. Submit

More information

Mealy & Moore Machines

Mealy & Moore Machines Mealy & Moore Machines Moore Machine is a finite-state machine whose output values are determined solely by its current state and can be defined as six elements (S, S 0, Σ, Λ, T, G), consisting of the

More information

Lecture 10: Synchronous Sequential Circuits Design

Lecture 10: Synchronous Sequential Circuits Design Lecture 0: Synchronous Sequential Circuits Design. General Form Input Combinational Flip-flops Combinational Output Circuit Circuit Clock.. Moore type has outputs dependent only on the state, e.g. ripple

More information

ENGG 1203 Tutorial _03 Laboratory 3 Build a ball counter. Lab 3. Lab 3 Gate Timing. Lab 3 Steps in designing a State Machine. Timing diagram of a DFF

ENGG 1203 Tutorial _03 Laboratory 3 Build a ball counter. Lab 3. Lab 3 Gate Timing. Lab 3 Steps in designing a State Machine. Timing diagram of a DFF ENGG 1203 Tutorial _03 Laboratory 3 Build a ball counter Timing diagram of a DFF Lab 3 Gate Timing difference timing for difference kind of gate, cost dependence (1) Setup Time = t2-t1 (2) Propagation

More information

EGR224 F 18 Assignment #4

EGR224 F 18 Assignment #4 EGR224 F 18 Assignment #4 ------------------------------------------------------------------------------------------------------------- Due Date: Friday (Section 10), October 19, by 5 pm (slide it under

More information

CSC9R6 Computer Design. Practical Digital Logic

CSC9R6 Computer Design. Practical Digital Logic CSC9R6 Computer Design Practical Digital Logic 1 References (for this part of CSC9R6) Hamacher et al: Computer Organization App A. In library Floyd: Digital Fundamentals Ch 1, 3-6, 8-10 web page: www.prenhall.com/floyd/

More information

Sequential logic and design

Sequential logic and design Principles Of Digital Design Sequential logic and design Analysis State-based (Moore) Input-based (Mealy) FSM definition Synthesis State minimization Encoding Optimization and timing Copyright 20-20by

More information

EXPERIMENT #4: SIMPLIFICATION OF BOOLEAN FUNCTIONS

EXPERIMENT #4: SIMPLIFICATION OF BOOLEAN FUNCTIONS EXPERIMENT #4: SIMPLIFICATION OF BOOLEAN FUNCTIONS OBJECTIVES: Simplify Boolean functions using K-map method Obtain Boolean expressions from timing diagrams Design and implement logic circuits Equipment

More information

Introduction to Karnaugh Maps

Introduction to Karnaugh Maps Introduction to Karnaugh Maps Review So far, you (the students) have been introduced to truth tables, and how to derive a Boolean circuit from them. We will do an example. Consider the truth table for

More information

Overview. Design Example: Automobile Lock

Overview. Design Example: Automobile Lock Overview Last Lecture: What is the course all about & why is it important? What is a digital system? What is a binary digital system? Boolean lgebra, Truth tables Operators: inversion, and, or, xor, xnor

More information

Number System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary

Number System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary Number System Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary BOOLEAN ALGEBRA BOOLEAN LOGIC OPERATIONS Logical AND Logical OR Logical COMPLEMENTATION

More information

UNIT 5 KARNAUGH MAPS Spring 2011

UNIT 5 KARNAUGH MAPS Spring 2011 UNIT 5 KRNUGH MPS Spring 2 Karnaugh Maps 2 Contents Minimum forms of switching functions Two- and three-variable Four-variable Determination of minimum expressions using essential prime implicants Five-variable

More information

5 State Minimisation. university of applied sciences hamburg. Digital Systems. Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz

5 State Minimisation. university of applied sciences hamburg. Digital Systems. Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz 5 State Minimisation In an early design phase when a word description of a sequential circuit's function is transformed into a FSM state diagram or state table redundant states may arise. State minimisation

More information

Finite State Machine (FSM)

Finite State Machine (FSM) Finite State Machine (FSM) Consists of: State register Stores current state Loads next state at clock edge Combinational logic Computes the next state Computes the outputs S S Next State CLK Current State

More information

Practice Final Exam Solutions

Practice Final Exam Solutions The University of Michigan Department of Electrical Engineering and Computer Science EECS 270 Fall 2003 Practice Final Exam Solutions Name: UM ID: For all questions, show all work that leads to your answer.

More information

Review for B33DV2-Digital Design. Digital Design

Review for B33DV2-Digital Design. Digital Design Review for B33DV2 The Elements of Modern Behaviours Design Representations Blocks Waveforms Gates Truth Tables Boolean Algebra Switches Rapid Prototyping Technologies Circuit Technologies TTL MOS Simulation

More information

Digital Electronics Final Examination. Part A

Digital Electronics Final Examination. Part A Digital Electronics Final Examination Part A Spring 2009 Student Name: Date: Class Period: Total Points: /50 Converted Score: /40 Page 1 of 13 Directions: This is a CLOSED BOOK/CLOSED NOTES exam. Select

More information

(Boolean Algebra, combinational circuits) (Binary Codes and -arithmetics)

(Boolean Algebra, combinational circuits) (Binary Codes and -arithmetics) Task 1. Exercises: Logical Design of Digital Systems Seite: 1 Self Study (Boolean Algebra, combinational circuits) 1.1 Minimize the function f 1 a ab ab by the help of Boolean algebra and give an implementation

More information

Sequential Synchronous Circuit Analysis

Sequential Synchronous Circuit Analysis Sequential Synchronous Circuit Analysis General Model Current State at time (t) is stored in an array of flip-flops. Next State at time (t+1) is a Boolean function of State and Inputs. Outputs at time

More information

Lecture 17: Designing Sequential Systems Using Flip Flops

Lecture 17: Designing Sequential Systems Using Flip Flops EE210: Switching Systems Lecture 17: Designing Sequential Systems Using Flip Flops Prof. YingLi Tian April 11, 2019 Department of Electrical Engineering The City College of New York The City University

More information

DESIGN AND IMPLEMENTATION OF ENCODERS AND DECODERS. To design and implement encoders and decoders using logic gates.

DESIGN AND IMPLEMENTATION OF ENCODERS AND DECODERS. To design and implement encoders and decoders using logic gates. DESIGN AND IMPLEMENTATION OF ENCODERS AND DECODERS AIM To design and implement encoders and decoders using logic gates. COMPONENTS REQUIRED S.No Components Specification Quantity 1. Digital IC Trainer

More information

Simplify the following Boolean expressions and minimize the number of literals:

Simplify the following Boolean expressions and minimize the number of literals: Boolean Algebra Task 1 Simplify the following Boolean expressions and minimize the number of literals: 1.1 1.2 1.3 Task 2 Convert the following expressions into sum of products and product of sums: 2.1

More information

Learning Objectives:

Learning Objectives: Learning Objectives: t the end of this topic you will be able to; draw a block diagram showing how -type flip-flops can be connected to form a synchronous counter to meet a given specification; explain

More information

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 5 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter

More information

Philadelphia University Faculty of Engineering

Philadelphia University Faculty of Engineering Philadelphia University Faculty of Engineering Marking Scheme Exam Paper BSc CE Logic Circuits (630211) Final Exam First semester ate: 03/02/2019 Section 1 Weighting 40% of the module total Lecturer: Coordinator:

More information

ECE 545 Digital System Design with VHDL Lecture 1. Digital Logic Refresher Part A Combinational Logic Building Blocks

ECE 545 Digital System Design with VHDL Lecture 1. Digital Logic Refresher Part A Combinational Logic Building Blocks ECE 545 Digital System Design with VHDL Lecture Digital Logic Refresher Part A Combinational Logic Building Blocks Lecture Roadmap Combinational Logic Basic Logic Review Basic Gates De Morgan s Law Combinational

More information

Boolean Algebra. Digital Logic Appendix A. Postulates, Identities in Boolean Algebra How can I manipulate expressions?

Boolean Algebra. Digital Logic Appendix A. Postulates, Identities in Boolean Algebra How can I manipulate expressions? Digital Logic Appendix A Gates Combinatorial Circuits Sequential Circuits Other operations NAND A NAND B = NOT ( A ANDB) = AB NOR A NOR B = NOT ( A ORB) = A + B Truth tables What is the result of the operation

More information

EEE2135 Digital Logic Design

EEE2135 Digital Logic Design EEE2135 Digital Logic Design Chapter 7. Sequential Circuits Design 서강대학교 전자공학과 1. Model of Sequential Circuits 1) Sequential vs. Combinational Circuits a. Sequential circuits: Outputs depend on both the

More information

Boolean Algebra. Digital Logic Appendix A. Boolean Algebra Other operations. Boolean Algebra. Postulates, Identities in Boolean Algebra

Boolean Algebra. Digital Logic Appendix A. Boolean Algebra Other operations. Boolean Algebra. Postulates, Identities in Boolean Algebra Digital Logic Appendix A Gates Combinatorial Circuits Sequential Circuits George Boole ideas 1854 Claude Shannon, apply to circuit design, 1938 (piirisuunnittelu) Describe digital circuitry function programming

More information

15.1 Elimination of Redundant States

15.1 Elimination of Redundant States 15.1 Elimination of Redundant States In Ch. 14 we tried not to have unnecessary states What if we have extra states in the state graph/table? Complete the table then eliminate the redundant states Chapter

More information

DIGITAL LOGIC CIRCUITS

DIGITAL LOGIC CIRCUITS DIGITAL LOGIC CIRCUITS Digital logic circuits BINARY NUMBER SYSTEM electronic circuits that handle information encoded in binary form (deal with signals that have only two values, and ) Digital. computers,

More information

04. What is the Mod number of the counter circuit shown below? Assume initially reset.

04. What is the Mod number of the counter circuit shown below? Assume initially reset. . Which of the following is the state diagram for the Meale machine shown below. 4. What is the Mod number of the counter circuit shown below? Assume initiall reset. input CLK D output D D a. b. / / /

More information

Homework 1. Part(a) Due: 15 Mar, 2018, 11:55pm

Homework 1. Part(a) Due: 15 Mar, 2018, 11:55pm ENGG1203: Introduction to Electrical and Electronic Engineering Second Semester, 2017 18 Homework 1 Due: 15 Mar, 2018, 11:55pm Instruction: Submit your answers electronically through Moodle. In Moodle,

More information

Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps

Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps EE210: Switching Systems Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps Prof. YingLi Tian Feb. 21/26, 2019 Department of Electrical Engineering The City College of New York

More information

Combinational Logic. Review of Combinational Logic 1

Combinational Logic. Review of Combinational Logic 1 Combinational Logic! Switches -> Boolean algebra! Representation of Boolean functions! Logic circuit elements - logic gates! Regular logic structures! Timing behavior of combinational logic! HDLs and combinational

More information

Synchronous Sequential Circuit Design. Digital Computer Design

Synchronous Sequential Circuit Design. Digital Computer Design Synchronous Sequential Circuit Design Digital Computer Design Races and Instability Combinational logic has no cyclic paths and no races If inputs are applied to combinational logic, the outputs will always

More information

Analysis and Design of Sequential Circuits: Examples

Analysis and Design of Sequential Circuits: Examples COSC3410 Analysis and Design of Sequential Circuits: Examples J. C. Huang Department of Computer Science University of Houston Sequential machine slide 1 inputs combinational circuit outputs memory elements

More information

Propositional Logic. Logical Expressions. Logic Minimization. CNF and DNF. Algebraic Laws for Logical Expressions CSC 173

Propositional Logic. Logical Expressions. Logic Minimization. CNF and DNF. Algebraic Laws for Logical Expressions CSC 173 Propositional Logic CSC 17 Propositional logic mathematical model (or algebra) for reasoning about the truth of logical expressions (propositions) Logical expressions propositional variables or logical

More information

Faculty of Engineering. FINAL EXAMINATION FALL 2008 (December2008) ANSWER KEY

Faculty of Engineering. FINAL EXAMINATION FALL 2008 (December2008) ANSWER KEY 1 McGill University Faculty of Engineering DIGITAL SYSTEM DESIGN ECSE-323 FINAL EXAMINATION FALL 2008 (December2008) ANSWER KEY STUDENT NAME McGILL I.D. NUMBER Examiner: Prof. J. Clark Signature: Associate

More information

CprE 281: Digital Logic

CprE 281: Digital Logic CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Synchronous Sequential Circuits Basic Design Steps CprE 281: Digital Logic Iowa State University, Ames,

More information

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department Page 1 of 13 COE 202: Digital Logic Design (3-0-3) Term 112 (Spring 2012) Final

More information

EECE 202 (Network I) & EECE 208 (Lab)

EECE 202 (Network I) & EECE 208 (Lab) Group 1 EECE 202 (Network I) & EECE 208 (Lab) Final Project Lucky Adike Itotoh Akhigbe Jason Alexis 4/25/2008 Method summary 1. Analysis of the different resistor configurations 2. Binary encoding of the

More information

Outcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps

Outcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps -. -. Spiral / Unit Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand latency, throughput, and at least technique to improve

More information

Spiral 1 / Unit 5. Karnaugh Maps

Spiral 1 / Unit 5. Karnaugh Maps -. Spiral / Unit Karnaugh Maps -. Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand latency, throughput, and at least technique to improve

More information

BER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO

BER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO UN IVERSIT Y O F CA LIFO RNI A AT BERKELEY BER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO SAN TA BARBA RA S AN TA CRUZ De p a r tm en t of Ele ctr i ca l En gin e e rin g a

More information

NP-Completeness. NP-Completeness 1

NP-Completeness. NP-Completeness 1 NP-Completeness x x x 2 x 2 x 3 x 3 x 4 x 4 2 22 32 3 2 23 3 33 NP-Completeness Outline and Reading P and NP ( 3.) Definition of P Definition of NP Alternate definition of NP NP-completeness ( 3.2) Definition

More information

Chapter 6. Synchronous Sequential Circuits

Chapter 6. Synchronous Sequential Circuits Chapter 6 Synchronous Sequential Circuits In a combinational circuit, the values of the outputs are determined solely by the present values of its inputs. In a sequential circuit, the values of the outputs

More information

Outcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps

Outcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps -. -. Spiral / Unit Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand latency, throughput, and at least technique to improve

More information

MECH 1500 Final Part 2 Review

MECH 1500 Final Part 2 Review Name: Class: Date: MECH 1500 Final Part 2 Review True/False Indicate whether the statement is true or false. 1. Programmed counters can serve the same function as mechanical counters. 2. Every PLC model

More information

Computer Science Final Examination Friday December 14 th 2001

Computer Science Final Examination Friday December 14 th 2001 Computer Science 03 60 265 Final Examination Friday December 14 th 2001 Dr. Robert D. Kent and Dr. Alioune Ngom Last Name: First Name: Student Number: INSTRUCTIONS EXAM DURATION IS 3 HOURs. CALCULATORS,

More information

Sequential Circuit Analysis

Sequential Circuit Analysis Sequential Circuit Analysis Last time we started talking about latches and flip-flops, which are basic one-bit memory units. Today we ll talk about sequential circuit analysis and design. First, we ll

More information

SOLUTION. Homework 1. Part(a) Due: 15 Mar, 2018, 11:55pm

SOLUTION. Homework 1. Part(a) Due: 15 Mar, 2018, 11:55pm ENGG1203: Introduction to Electrical and Electronic Engineering Second Semester, 2017 18 Homework 1 Due: 15 Mar, 2018, 11:55pm Instruction: Submit your answers electronically through Moodle. In Moodle,

More information

CSEE W3827 Fundamentals of Computer Systems Homework Assignment 3

CSEE W3827 Fundamentals of Computer Systems Homework Assignment 3 CSEE W3827 Fundamentals of Computer Systems Homework Assignment 3 Prof. Martha A. Kim Columbia University Due October 10, 2013 at 10:10 AM Write your name and UNI on your solutions Show your work for each

More information

COEN 312 DIGITAL SYSTEMS DESIGN - LECTURE NOTES Concordia University

COEN 312 DIGITAL SYSTEMS DESIGN - LECTURE NOTES Concordia University 1 OEN 312 DIGIAL SYSEMS DESIGN - LEURE NOES oncordia University hapter 6: Registers and ounters NOE: For more examples and detailed description of the material in the lecture notes, please refer to the

More information

ECE 545 Digital System Design with VHDL Lecture 1A. Digital Logic Refresher Part A Combinational Logic Building Blocks

ECE 545 Digital System Design with VHDL Lecture 1A. Digital Logic Refresher Part A Combinational Logic Building Blocks ECE 545 Digital System Design with VHDL Lecture A Digital Logic Refresher Part A Combinational Logic Building Blocks Lecture Roadmap Combinational Logic Basic Logic Review Basic Gates De Morgan s Laws

More information

Digital Logic Design - Chapter 5

Digital Logic Design - Chapter 5 Digital Logic Design - Chapter 5 S. Design a 2-bit binary up counter a) using positive-edge-triggered D flip-flops. b) using positive-edge-triggered T flip-flops. c) using positive-edge-triggered JK flip-flops.

More information

Discrete Mathematics. CS204: Spring, Jong C. Park Computer Science Department KAIST

Discrete Mathematics. CS204: Spring, Jong C. Park Computer Science Department KAIST Discrete Mathematics CS204: Spring, 2008 Jong C. Park Computer Science Department KAIST Today s Topics Combinatorial Circuits Properties of Combinatorial Circuits Boolean Algebras Boolean Functions and

More information

XOR - XNOR Gates. The graphic symbol and truth table of XOR gate is shown in the figure.

XOR - XNOR Gates. The graphic symbol and truth table of XOR gate is shown in the figure. XOR - XNOR Gates Lesson Objectives: In addition to AND, OR, NOT, NAND and NOR gates, exclusive-or (XOR) and exclusive-nor (XNOR) gates are also used in the design of digital circuits. These have special

More information

Chapter 4 Part 2 Sequential Circuits

Chapter 4 Part 2 Sequential Circuits University of Wisconsin - Madison ECE/Comp Sci 352 Digital Systems Fundamentals Kewal K. Saluja and Yu Hen Hu Spring 2002 Chapter 4 Part 2 Sequential Circuits Originals by: Charles R. Kime and Tom Kamisnski

More information

Karnaugh Maps Objectives

Karnaugh Maps Objectives Karnaugh Maps Objectives For Karnaugh Maps of up to 5 variables Plot a function from algebraic, minterm or maxterm form Obtain minimum Sum of Products and Product of Sums Understand the relationship between

More information

Principles of Computer Architecture. Appendix B: Reduction of Digital Logic. Chapter Contents

Principles of Computer Architecture. Appendix B: Reduction of Digital Logic. Chapter Contents B-1 Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix B: Reduction of Digital Logic B-2 Chapter Contents B.1 Reduction of Combinational Logic and Sequential Logic B.2 Reduction

More information

L10 State Machine Design Topics

L10 State Machine Design Topics L State Machine Design Topics States Machine Design Other topics on state machine design Equivalent sequential machines Incompletely specified machines One Hot State Machines Ref: text Unit 15.4, 15.5,

More information

2 Application of Boolean Algebra Theorems (15 Points - graded for completion only)

2 Application of Boolean Algebra Theorems (15 Points - graded for completion only) CSE140 HW1 Solution (100 Points) 1 Introduction The purpose of this assignment is three-fold. First, it aims to help you practice the application of Boolean Algebra theorems to transform and reduce Boolean

More information

Models for representing sequential circuits

Models for representing sequential circuits Sequential Circuits Models for representing sequential circuits Finite-state machines (Moore and Mealy) Representation of memory (states) Changes in state (transitions) Design procedure State diagrams

More information

LOGIC GATES. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.

LOGIC GATES. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D. Basic Eperiment and Design of Electronics LOGIC GATES Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Outline Boolean algebra Logic gates Karnaugh maps

More information

Why digital? Overview. Number Systems. Binary to Decimal conversion

Why digital? Overview. Number Systems. Binary to Decimal conversion Why digital? Overview It has the following advantages over analog. It can be processed and transmitted efficiently and reliably. It can be stored and retrieved with greater accuracy. Noise level does not

More information

Last lecture Counter design Finite state machine started vending machine example. Today Continue on the vending machine example Moore/Mealy machines

Last lecture Counter design Finite state machine started vending machine example. Today Continue on the vending machine example Moore/Mealy machines Lecture 2 Logistics HW6 due Wednesday Lab 7 this week (Tuesday exception) Midterm 2 Friday (covers material up to simple FSM (today)) Review on Thursday Yoky office hour on Friday moved to Thursday 2-:2pm

More information

CE1911 LECTURE FSM DESIGN PRACTICE DAY 1

CE1911 LECTURE FSM DESIGN PRACTICE DAY 1 REVIEW MATERIAL 1. Combinational circuits do not have memory. They calculate instantaneous outputs based only on current inputs. They implement basic arithmetic and logic functions. 2. Sequential circuits

More information

Ch 7. Finite State Machines. VII - Finite State Machines Contemporary Logic Design 1

Ch 7. Finite State Machines. VII - Finite State Machines Contemporary Logic Design 1 Ch 7. Finite State Machines VII - Finite State Machines Contemporary Logic esign 1 Finite State Machines Sequential circuits primitive sequential elements combinational logic Models for representing sequential

More information

Sequential Equivalence Checking - I

Sequential Equivalence Checking - I Sequential Equivalence Checking - I Virendra Singh Associate Professor Computer Architecture and Dependable Systems Lab. Dept. of Electrical Engineering Indian Institute of Technology Bombay viren@ee.iitb.ac.in

More information

Gates and Flip-Flops

Gates and Flip-Flops Gates and Flip-Flops Chris Kervick (11355511) With Evan Sheridan and Tom Power December 2012 On a scale of 1 to 10, how likely is it that this question is using binary?...4? What s a 4? Abstract The operation

More information

Fundamentals of Computer Systems

Fundamentals of Computer Systems Fundamentals of Computer Systems Review for the Midterm Stephen A. Edwards Columbia University Spring 22 The Midterm 75 minutes 4 5 problems Closed book Simple calculators are OK, but unnecessary One double-sided

More information

Chapter 7 Combinational Logic Networks

Chapter 7 Combinational Logic Networks Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips Chapter 7 Combinational Logic Networks SKEE223 Digital Electronics Mun im/rif/izam KE, Universiti Teknologi Malaysia

More information

ELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10)

ELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10) ELEC 2200-002 Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

More information

CSEE W3827 Fundamentals of Computer Systems Homework Assignment 3 Solutions

CSEE W3827 Fundamentals of Computer Systems Homework Assignment 3 Solutions CSEE W3827 Fundamentals of Computer Systems Homework Assignment 3 Solutions Prof. Martha A. Kim Columbia University Due October 10, 2013 at 10:10 AM Write your name and UNI on your solutions Show your

More information

Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions

Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions EE210: Switching Systems Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions Prof. YingLi Tian Feb. 15, 2018 Department of Electrical Engineering The City College of New York The

More information

ENGIN 112 Intro to Electrical and Computer Engineering

ENGIN 112 Intro to Electrical and Computer Engineering ENGIN 112 Intro to Electrical and Computer Engineering Lecture 17 Encoders and Decoders Overview Binary decoders Converts an n-bit code to a single active output Can be developed using AND/OR gates Can

More information

The Design Procedure. Output Equation Determination - Derive output equations from the state table

The Design Procedure. Output Equation Determination - Derive output equations from the state table The Design Procedure Specification Formulation - Obtain a state diagram or state table State Assignment - Assign binary codes to the states Flip-Flop Input Equation Determination - Select flipflop types

More information

Binary Logic and Gates

Binary Logic and Gates 1 COE 202- Digital Logic Binary Logic and Gates Dr. Abdulaziz Y. Barnawi COE Department KFUPM 2 Outline Introduction Boolean Algebra Elements of Boolean Algebra (Binary Logic) Logic Operations & Logic

More information

Synchronous Sequential Logic

Synchronous Sequential Logic 1 IT 201 DIGITAL SYSTEMS DESIGN MODULE4 NOTES Synchronous Sequential Logic Sequential Circuits - A sequential circuit consists of a combinational circuit and a feedback through the storage elements in

More information

Minimization techniques

Minimization techniques Pune Vidyarthi Griha s COLLEGE OF ENGINEERING, NSIK - 4 Minimization techniques By Prof. nand N. Gharu ssistant Professor Computer Department Combinational Logic Circuits Introduction Standard representation

More information

Digital Logic: Boolean Algebra and Gates. Textbook Chapter 3

Digital Logic: Boolean Algebra and Gates. Textbook Chapter 3 Digital Logic: Boolean Algebra and Gates Textbook Chapter 3 Basic Logic Gates XOR CMPE12 Summer 2009 02-2 Truth Table The most basic representation of a logic function Lists the output for all possible

More information

Combinational Logic. By : Ali Mustafa

Combinational Logic. By : Ali Mustafa Combinational Logic By : Ali Mustafa Contents Adder Subtractor Multiplier Comparator Decoder Encoder Multiplexer How to Analyze any combinational circuit like this? Analysis Procedure To obtain the output

More information

COMPUTER SCIENCE TRIPOS

COMPUTER SCIENCE TRIPOS CST0.2017.2.1 COMPUTER SCIENCE TRIPOS Part IA Thursday 8 June 2017 1.30 to 4.30 COMPUTER SCIENCE Paper 2 Answer one question from each of Sections A, B and C, and two questions from Section D. Submit the

More information